Detailed Action
summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on March 05, 2025.
2. Claims 1-9 are pending and has been examined.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d), which the certified copy has been placed in the record of the file.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 03/05/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. Drawings are objected because of the followings informalities:
Blurry and faded of text and numbers make the drawings difficult to read. Clear and good quality of drawings are required.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “at least one of ” the coupling capacitor in line 9 should be “the at least one of “ .
Claims 1 and 5 recite “the voltage difference” in lines 15 and 10 . There are insufficient antecedent basis for these limitations.
Claims 6 and 7 recite “an input reference voltage” , “a sub-threshold gate “ “resistor ladder” and “voltage difference” in lines 3-4 and 6 should be “the input reference voltage” ,”the sub-threshold gate “, “the resistor ladder” and “ the voltage difference” respectively.
Claims 6-7 recite “the voltage level” in line 8 . There are insufficient antecedent basis for these limitations.
Claims 6-7 recite “AC-coupling an output transition” in line 10 should be “the AC-coupling of the output transition” .
Claims 6-7 recite “a plurality of coupling capacitors” in line 10 should be “ the a plurality of coupling capacitors”
Claims 8-9 recite “AC coupling” should be “ the AC coupling”
Claims 2-4 are depend on claim 1, thus are also rejected because of their dependency.
Allowable Subject Matter
7. Claim 1 and 5 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 1, the prior art in the record fails to discloses or suggest a feedforward circuit including the limitation of “a bias generator operatively connected to the voltage regulator for generating a sub-threshold gate bias; a plurality of coupling capacitors ,at least one of the coupling capacitors operatively connected to the bias generator for reading the sub-threshold gate bias; and a feedforward amplifier operatively coupled with at least one of the coupling capacitors; characterized in that wherein the plurality of coupling capacitors being configured to direct AC-couple an output transition of CMOS logic gates; wherein the output transition of CMOS logic gates is driven by a plurality of data signals onto the gate bias of the feedforward amplifier; wherein the feedforward amplifier acts upon the voltage differences between the gate bias of the feedforward amplifier and the sub-threshold gate bias of the bias generator for current injection or current discharge.”
In regards to claim 5, the prior arts in the record fails to discloses or suggest a method for regulating voltage in feedforward circuitry including the limitation of “regulating voltage according to an input reference voltage from a bandgap or a resistor ladder; generating a sub-threshold gate bias by a bias generator; characterized by AC-coupling an output transition of CMOS logic gates by a plurality of coupling capacitors based on a plurality of data signals onto a gate bias of a feedforward amplifier ;wherein the feedforward amplifier acts upon the voltage differences between the gate bias of the feedforward amplifier and the sub-threshold gate bias of the bias generator for current injection or current discharge.”
Claims 2-4 depend on claim 1, thus are also allowed because of their dependency .
Claims 6-9 depend on claim 5, thus are also allowed because of their dependency .
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fagnani “20250343485” the present invention includes an apparatus includes a constant amplitude ramp generator having a differential output and first and second generator inputs, in which the first generator input is coupled to a power terminal. The apparatus also includes an input voltage feed-forward circuit having a feed-forward input and a feed-forward output, in which the feed-forward input is coupled to an input voltage terminal, and the feed-forward output is coupled to the second generator input.
Chew “20250253771” a method for regulating power supply of a circuitry system using a feedforward amplifier.
Deng “20230266783” the present invention includes a power supply noise reduction methods and low drop out (LDO) voltage regulators with capacitively coupled supply noise-reducing components are disclosed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838
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