CTNF 19/070,991 CTNF 90374 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Office Action is responsive to communication(s) filed on 03/05/2025. Claims 1-20 have been examined and are pending in this application. Information Disclosure Statement 06-52 The information disclosure statement (IDS) was submitted on 03/18/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 11-12 and 17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Step 1 Analysis : Claims 11-12 are drawn to a device which is within the four statutory categories (i.e., machine). Claim 17 is drawn to a device which is within the four statutory categories (i.e., machine). Regarding claim 11 , Step 2A Prong 1 : The claim recites abstract ideas as explained below. The claim recites: a processor operable to program pages in the channels in different orders – These limitations, as drafted, is a process that, under its broadest reasonable interpretation, cover the abstract idea(s) of a mental process because they recite a process that could be practically performed in the human mind. Accordingly, the claim is directed to an abstract idea. Step 2A Prong 2 : The claim recites the additional elements of: a plurality of channels of memory, each including a plurality of dies, each of the dies having a plurality of page types – The additional elements, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using generic computer components [see MPEP §2106.05(f)]. Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application. Step 2B : The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. A claim having broad applicability across many fields of endeavor may not provide meaningful limitations that integrate a judicial exception into a practical application or amount to significantly more. For instance, a claim that generically recites an effect of the judicial exception or claims every mode of accomplishing that effect, amounts to a claim that is merely adding the words "apply it" to the judicial exception. See Internet Patents Corporation v. Active Network, Inc., 790 F.3d 1343, 1348, 115 USPQ2d 1414, 1418 (Fed. Cir. 2015) (The recitation of maintaining the state of data in an online form without restriction on how the state is maintained and with no description of the mechanism for maintaining the state describes "the effect or result dissociated from any method by which maintaining the state is accomplished" and does not provide a meaningful limitation because it merely states that the abstract idea should be applied to achieve a desired result). See also O’Reilly v. Morse, 56 U.S. 62 (1854) (finding ineligible a claim for "the use of electromagnetism for transmitting signals at a distance"); The Telephone Cases, 126 U.S. 1, 209 (1888) (finding a method of "transmitting vocal or other sound telegraphically ... by causing electrical undulations, similar in form to the vibrations of the air accompanying the said vocal or other sounds," to be ineligible, because it "monopolize[d] a natural force" and "the right to avail of that law by any means whatever."). MPEP §2106.05(f), Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than generally linking the use of a judicial exception to a particular technological environment or field of use. As explained by the Supreme Court, a claim directed to a judicial exception cannot be made eligible "simply by having the applicant acquiesce to limiting the reach of the patent for the formula to a particular technological use." Diamond v. Diehr, 450 U.S. 175, 192 n.14, 209 USPQ 1, 10 n. 14 (1981). Thus, limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application. MPEP §2106.05(h). Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible. Regarding claim 12 , Step 2A Prong 1 : The claim depends from claim 11, so is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea. Step 2A Prong 2 : The claim recites the additional elements of: wherein the plurality of page types include lower page (LP), upper page (UP), and extra page (XP) - The additional elements, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using generic computer components [see MPEP §2106.05(f)]. Accordingly, the claim does not include any additional elements that would integrate the judicial exception into a practical application. Step 2B : The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the claim amounts to no more than applying an exception using generic computer components. Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible. Regarding claim 17 , Step 2A Prong 1 : The claim recites abstract ideas as explained below. The claim recites: a processor operable to program pages in the dies in different orders – These limitations, as drafted, is a process that, under its broadest reasonable interpretation, cover the abstract idea(s) of a mental process because they recite a process that could be practically performed in the human mind. Accordingly, the claim is directed to an abstract idea. Step 2A Prong 2 : The claim recites the additional elements of: a plurality of dies, each of the dies having a plurality of page types – The additional elements, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using generic computer components [see MPEP §2106.05(f)]. Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application. Step 2B : The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. A claim having broad applicability across many fields of endeavor may not provide meaningful limitations that integrate a judicial exception into a practical application or amount to significantly more. For instance, a claim that generically recites an effect of the judicial exception or claims every mode of accomplishing that effect, amounts to a claim that is merely adding the words "apply it" to the judicial exception. See Internet Patents Corporation v. Active Network, Inc., 790 F.3d 1343, 1348, 115 USPQ2d 1414, 1418 (Fed. Cir. 2015) (The recitation of maintaining the state of data in an online form without restriction on how the state is maintained and with no description of the mechanism for maintaining the state describes "the effect or result dissociated from any method by which maintaining the state is accomplished" and does not provide a meaningful limitation because it merely states that the abstract idea should be applied to achieve a desired result). See also O’Reilly v. Morse, 56 U.S. 62 (1854) (finding ineligible a claim for "the use of electromagnetism for transmitting signals at a distance"); The Telephone Cases, 126 U.S. 1, 209 (1888) (finding a method of "transmitting vocal or other sound telegraphically ... by causing electrical undulations, similar in form to the vibrations of the air accompanying the said vocal or other sounds," to be ineligible, because it "monopolize[d] a natural force" and "the right to avail of that law by any means whatever."). MPEP §2106.05(f), Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than generally linking the use of a judicial exception to a particular technological environment or field of use. As explained by the Supreme Court, a claim directed to a judicial exception cannot be made eligible "simply by having the applicant acquiesce to limiting the reach of the patent for the formula to a particular technological use." Diamond v. Diehr, 450 U.S. 175, 192 n.14, 209 USPQ 1, 10 n. 14 (1981). Thus, limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application. MPEP §2106.05(h). Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. As enumerated in the table below, instant independent claims 1, 11, and 17 are anticipated by independent claims 1 and 6 of US Patent 12,248,705. Status Instant Application US Patent 12,248,705 Anticipation 1. A device, comprising: memory cells configured as superpages, wherein each of the superpages includes a plurality of pages programmable in a first mode of programming the pages parallel or in a second mode of programming the pages sequentially; and a processor configured to schedule a first superpage for programming in the first mode and a second superpage for programming in the second mode. 1. A device comprising: at least one memory array configured on a plurality of dies; and at least one processor configured to: select a write policy of programming a plurality of pages of data to the at least one memory array, wherein the write policy is selected from a plurality of schemes including: a first addressing scheme in which the plurality of pages are programmed on one of the plurality of dies sequentially one page after another; and a second addressing scheme in which the plurality of pages are distributed to the plurality of dies for programming in parallel for the plurality of pages; reserve a memory buffer according to the write policy selected to program the data into the memory array, wherein the memory buffer is of a first size for programming the data according to the first addressing scheme and of a second size different from the first size for programming the data according to the second addressing scheme; and program the data, received from a host using the memory buffer, according to the write policy. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 2. The device of claim 1, wherein the second superpage includes a plurality of channels, each of the channels including a plurality of dies, and each of the dies having a lower page (LP), an upper page (UP) and an extra page (XP). Claim 1. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 3. The device of claim 2, wherein the second mode is configured to program a page of a first type from a first die from each of the plurality of channels sequentially before programming a page of the first type from a second die from each of the plurality of channels sequentially. Claim 1. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 4. The device of claim 3, wherein the first type is lower page (LP), upper page (UP), or extra page (XP). Claim 1. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 5. The device of claim 2, wherein the second mode is configured to program a page of a first type from each die from the channels sequentially before programming a page of a second type from each die from the channels sequentially. Claim 1. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 6. The device of claim 5, wherein the first type and the second type are different ones from: lower page (LP), upper page (UP) and extra page (XP). Claim 1. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 7. The device of claim 2, wherein the second mode is configured to program a page of each of a plurality of types from a first die from each of the plurality of channels sequentially before programming a page of each of the plurality of types from a second die from each of the plurality of channels sequentially. Claim 1. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 8. The device of claim 7, wherein the plurality of types include lower page (LP), upper page (UP), and extra page (XP). Claim 1. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 9. The device of claim 2, wherein the second mode is configured to program a page of each of a plurality of types from a first die from a first channel sequentially before programming sequentially a page of each of the plurality of types from a second die from the first channel among the plurality of channels. Claim 1. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 10. The device of claim 9, wherein the plurality of types include lower page (LP), upper page (UP), and extra page (XP). Claim 1. Anticipation 11. A device, comprising: a plurality of channels of memory, each including a plurality of dies, each of the dies having a plurality of page types; and a processor operable to program pages in the channels in different orders. 6. A system comprising: a memory device comprising at least one memory array configured on a plurality of dies; input/output control circuitry; and at least one processor configured to: select a write policy of programming a plurality of pages of data to the at least one memory array, wherein the write policy is selected from a plurality of schemes including: a first addressing scheme in which the plurality of pages are programmed on one of the plurality of dies sequentially one page after another; and a second addressing scheme in which the plurality of pages are distributed to the plurality of dies for programming; reserve a memory buffer according to the write policy selected to program the data into the memory array, wherein the memory buffer is of a first size for programming the data according to the first addressing scheme and of a second size different from the first size for programming the data according to the second addressing scheme; and program the data, received from a host using the memory buffer, according to the write policy. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 12. The device of claim 11, wherein the plurality of page types include lower page (LP), upper page (UP), and extra page (XP). Claim 6. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 13. The device of claim 12, wherein the processor is operable to program a page of a first type from a first die from each of the plurality of channels sequentially before programming a page of the first type from a second die from each of the plurality of channels sequentially. Claim 6. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 14. The device of claim 12, wherein the processor is operable to program a page of a first type from each die from the channels sequentially before programming a page of a second type from each die from the channels sequentially. Claim 6. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 15. The device of claim 12, wherein the processor is operable to program a page of each of a plurality of types from a first die from each of the plurality of channels sequentially before programming a page of each of the plurality of types from a second die from each of the plurality of channels sequentially. Claim 6. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 16. The device of claim 12, wherein the processor is operable to program a page of each of a plurality of types from a first die from a first channel sequentially before programming sequentially a page of each of the plurality of types from a second die from the first channel among the plurality of channels. Claim 6. Anticipation 17. A device, comprising: a plurality of dies, each of the dies having a plurality of page types; and a processor operable to program pages in the dies in different orders. 1. A device comprising: at least one memory array configured on a plurality of dies; and at least one processor configured to: select a write policy of programming a plurality of pages of data to the at least one memory array, wherein the write policy is selected from a plurality of schemes including: a first addressing scheme in which the plurality of pages are programmed on one of the plurality of dies sequentially one page after another; and a second addressing scheme in which the plurality of pages are distributed to the plurality of dies for programming in parallel for the plurality of pages; reserve a memory buffer according to the write policy selected to program the data into the memory array, wherein the memory buffer is of a first size for programming the data according to the first addressing scheme and of a second size different from the first size for programming the data according to the second addressing scheme; and program the data, received from a host using the memory buffer, according to the write policy. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 18. The device of claim 17, wherein the processor is operable to program a page of a first type from each of the plurality of dies sequentially before programming a page of a second type from a second die from each of the plurality of dies sequentially. Claim 1. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 19. The device of claim 18, wherein the first type and tie second type are different ones of: lower page (LP), upper page (UP), and extra page (XP). Claim 1. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 20. The device of claim 17, wherein the plurality of dies include a first die and a second die; and the processor is operable to program a page of each of the plurality of page types from the first die sequentially before programming a page of each of the plurality of page types from the second die sequentially. Claim 1. 08-36 AIA Claim s 2-10, 12-16, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1 and 6 of U.S. Patent No. 12,248,705 in view of Fuxa et al. US 2011/0040927 (“Fuxa”) and in further view of Papandreou et al. US 2020/0066355 (“Papandreou”) . As per dependent claims 2, 4, 6, 8, 10, 12, and 19, taking claim 2 as exemplary, Fuxa teaches wherein the second superpage includes a plurality of channels, each of the channels including a plurality of dies (“Referring to FIG. 1, … the physical memory chips 0a-9b that make up the memory array 14 are divided into ten groups of two chips. For purposes of the physical addressing scheme, each group of two chips [dies] forms a ‘Lane,’ also sometimes referred to as a ‘Channel,’ such that there are ten Lanes or Channels within the memory array 14 (LANE0-LANE9).” Para 0046). Given the teaching of Fuxa, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of US Patent 12,248,705 with “wherein the second superpage includes a plurality of channels, each of the channels including a plurality of dies”. Fuxa may not explicitly disclose, but in an analogous art in the same field of endeavor, Papandreou teaches and each of the dies having (“blocks from different dies and/or flash channels are grouped together, such that blocks from the same group can be read or written in parallel, thereby increasing overall bandwidth.” Para 0046) a lower page (LP), an upper page (UP) and an extra page (XP) (“In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076). Given the teaching of Papandreou, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of US Patent 12,248,705 with “and each of the dies having a lower page (LP), an upper page (UP) and an extra page (XP)”. As per dependent claims 3, 5, 7, 9, 13-16, 18, and 20, taking claim 3 as exemplary, Fuxa in combination with Papandreou teaches wherein the second mode is configured to program a page of a first type from a first die from each of the plurality of channels sequentially before programming a page of the first type from a second die from each of the plurality of channels sequentially (“Page Stripes are stored such that the Pages associated with the Page Stripe are written sequentially across the Lanes, but with the first Data Page of the Page Stripe written into a physical location associated with a Lane other than LANE0. These embodiments are illustrated in FIGS. 9A-9D” para 0085. Papandreou teaches “In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076. Based on this teaching of Papandreou, a page of a first type (for example, a lower page, or an upper page or an extra page) is programmed). Given the teaching of the combination of Fuxa and Papandreou, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of US Patent 12,248,705 with “wherein the second mode is configured to program a page of a first type from a first die from each of the plurality of channels sequentially before programming a page of the first type from a second die from each of the plurality of channels sequentially”. As enumerated in the table below, instant independent claims 1, 11, and 17 are anticipated by independent claim 16 of US Patent 11,435,944. Status Instant Application US Patent 11,435,944 Anticipation 1. A device, comprising: memory cells configured as superpages, wherein each of the superpages includes a plurality of pages programmable in a first mode of programming the pages parallel or in a second mode of programming the pages sequentially; and a processor configured to schedule a first superpage for programming in the first mode and a second superpage for programming in the second mode. 16. A memory system comprising: a memory device comprising memory arrays forming a first and a second superpage, input/output control circuitry, and control logic circuitry; at least one processor coupled to the input/output control circuitry and the control logic circuitry, wherein the at least one processor (i) receives status information regarding the memory device from the input/output control circuitry, and (ii) generates control signals transmitted to the control logic circuitry; firmware, coupled to the at least one processor, comprising at least one of a write detector, a host bandwidth detector, a host queue depth detector, and an endurance monitor, the firmware configured to monitor one or more of memory performance parameters; wherein the at least one processor is configured to perform operations involving: creating rules based on successful programming behavior; assessing information regarding the rules to determine a write policy used to write data to the one or more memory arrays, wherein the write policy includes a first addressing scheme and a second addressing scheme; selecting the write policy based on the memory performance parameters monitored; reserving, during a single programming sequence, a memory buffer of a first size for writing data when the first addressing scheme is used and reserving a memory buffer of a second size different from the first size for writing data when the second addressing scheme is used; and writing, during the single programming sequence, to a first die and a second die of a same page within the first superpage sequentially using the first addressing scheme, and writing to a first page and a second page of a same die within the second superpage sequentially using the second addressing scheme. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 2. The device of claim 1, wherein the second superpage includes a plurality of channels, each of the channels including a plurality of dies, and each of the dies having a lower page (LP), an upper page (UP) and an extra page (XP). Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 3. The device of claim 2, wherein the second mode is configured to program a page of a first type from a first die from each of the plurality of channels sequentially before programming a page of the first type from a second die from each of the plurality of channels sequentially. Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 4. The device of claim 3, wherein the first type is lower page (LP), upper page (UP), or extra page (XP). Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 5. The device of claim 2, wherein the second mode is configured to program a page of a first type from each die from the channels sequentially before programming a page of a second type from each die from the channels sequentially. Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 6. The device of claim 5, wherein the first type and the second type are different ones from: lower page (LP), upper page (UP) and extra page (XP). Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 7. The device of claim 2, wherein the second mode is configured to program a page of each of a plurality of types from a first die from each of the plurality of channels sequentially before programming a page of each of the plurality of types from a second die from each of the plurality of channels sequentially. Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 8. The device of claim 7, wherein the plurality of types include lower page (LP), upper page (UP), and extra page (XP). Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 9. The device of claim 2, wherein the second mode is configured to program a page of each of a plurality of types from a first die from a first channel sequentially before programming sequentially a page of each of the plurality of types from a second die from the first channel among the plurality of channels. Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 10. The device of claim 9, wherein the plurality of types include lower page (LP), upper page (UP), and extra page (XP). Claim 16. Anticipation 11. A device, comprising: a plurality of channels of memory, each including a plurality of dies, each of the dies having a plurality of page types; and a processor operable to program pages in the channels in different orders. 16. A memory system comprising: a memory device comprising memory arrays forming a first and a second superpage, input/output control circuitry, and control logic circuitry; at least one processor coupled to the input/output control circuitry and the control logic circuitry, wherein the at least one processor (i) receives status information regarding the memory device from the input/output control circuitry, and (ii) generates control signals transmitted to the control logic circuitry; firmware, coupled to the at least one processor, comprising at least one of a write detector, a host bandwidth detector, a host queue depth detector, and an endurance monitor, the firmware configured to monitor one or more of memory performance parameters; wherein the at least one processor is configured to perform operations involving: creating rules based on successful programming behavior; assessing information regarding the rules to determine a write policy used to write data to the one or more memory arrays, wherein the write policy includes a first addressing scheme and a second addressing scheme; selecting the write policy based on the memory performance parameters monitored; reserving, during a single programming sequence, a memory buffer of a first size for writing data when the first addressing scheme is used and reserving a memory buffer of a second size different from the first size for writing data when the second addressing scheme is used; and writing, during the single programming sequence, to a first die and a second die of a same page within the first superpage sequentially using the first addressing scheme, and writing to a first page and a second page of a same die within the second superpage sequentially using the second addressing scheme. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 12. The device of claim 11, wherein the plurality of page types include lower page (LP), upper page (UP), and extra page (XP). Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 13. The device of claim 12, wherein the processor is operable to program a page of a first type from a first die from each of the plurality of channels sequentially before programming a page of the first type from a second die from each of the plurality of channels sequentially. Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 14. The device of claim 12, wherein the processor is operable to program a page of a first type from each die from the channels sequentially before programming a page of a second type from each die from the channels sequentially. Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 15. The device of claim 12, wherein the processor is operable to program a page of each of a plurality of types from a first die from each of the plurality of channels sequentially before programming a page of each of the plurality of types from a second die from each of the plurality of channels sequentially. Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 16. The device of claim 12, wherein the processor is operable to program a page of each of a plurality of types from a first die from a first channel sequentially before programming sequentially a page of each of the plurality of types from a second die from the first channel among the plurality of channels. Claim 16. Anticipation 17. A device, comprising: a plurality of dies, each of the dies having a plurality of page types; and a processor operable to program pages in the dies in different orders. 16. A memory system comprising: a memory device comprising memory arrays forming a first and a second superpage, input/output control circuitry, and control logic circuitry; at least one processor coupled to the input/output control circuitry and the control logic circuitry, wherein the at least one processor (i) receives status information regarding the memory device from the input/output control circuitry, and (ii) generates control signals transmitted to the control logic circuitry; firmware, coupled to the at least one processor, comprising at least one of a write detector, a host bandwidth detector, a host queue depth detector, and an endurance monitor, the firmware configured to monitor one or more of memory performance parameters; wherein the at least one processor is configured to perform operations involving: creating rules based on successful programming behavior; assessing information regarding the rules to determine a write policy used to write data to the one or more memory arrays, wherein the write policy includes a first addressing scheme and a second addressing scheme; selecting the write policy based on the memory performance parameters monitored; reserving, during a single programming sequence, a memory buffer of a first size for writing data when the first addressing scheme is used and reserving a memory buffer of a second size different from the first size for writing data when the second addressing scheme is used; and writing, during the single programming sequence, to a first die and a second die of a same page within the first superpage sequentially using the first addressing scheme, and writing to a first page and a second page of a same die within the second superpage sequentially using the second addressing scheme. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 18. The device of claim 17, wherein the processor is operable to program a page of a first type from each of the plurality of dies sequentially before programming a page of a second type from a second die from each of the plurality of dies sequentially. Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 19. The device of claim 18, wherein the first type and tie second type are different ones of: lower page (LP), upper page (UP), and extra page (XP). Claim 16. Obvious in view of Fuxa et al. US 2011/0040927 and in further view of Papandreou et al. US 2020/0066355 20. The device of claim 17, wherein the plurality of dies include a first die and a second die; and the processor is operable to program a page of each of the plurality of page types from the first die sequentially before programming a page of each of the plurality of page types from the second die sequentially. Claim 16 . 08-36 AIA Claim s 2-10, 12-16, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. 11,435,944 in view of Fuxa and in further view of Papandreou . For the obviousness type double patenting rejections with secondary references, see pages 10-12 of this Office Action . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 11 and 17 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Fuxa et al. US 2011/0040927 (“Fuxa”) . As per independent claim 11, Fuxa teaches A device (“a memory storage system 100” para 0033 and FIG. 1), comprising : a plurality of channels of memory (“there are ten Lanes or Channels within the memory array 14 (LANE0-LANE9).” Para 0046), each including a plurality of dies (“each group of two chips [dies] forms a ‘Lane,’ also sometimes referred to as a ‘Channel,’” para 0046), each of the dies having a plurality of page types (“data is written to the memory array 14 using associated Pages of data known as ‘Page Stripes.’” Para 0060); a processor (“CPU 15” para 0034) operable to program pages in the channels in different orders (“As generally reflected in FIG. 7A, this embodiment allows for efficient writing and reading of a Page Stripe to the memory array since it allows all of the Pages of data that make up the Page Stripe to be written to the memory array 14 simultaneously or near-simultaneously by having the FLASH controller 10 issue commands to the various Lanes at, or close to, the same time.” Para 0078. Further, “Page Stripes are stored such that the Pages associated with the Page Stripe are written sequentially across the Lanes,” para 0085). As per independent claim 17, this claim is rejected based on arguments provided above for similar rejected independent claim 11 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Fuxa . As per independent claim 1, Fuxa teaches A device (“a memory storage system 100” para 0033 and FIG. 1), comprising : memory cells (“FLASH memory storage cell (or groups of cells).” Para 0161) configured as superpages (“a Page Stripe represents a grouping of associated information, stored in a particular manner within the memory array 14.” Para 0060), wherein each of the superpages includes a plurality of pages programmable in a first mode of programming the pages parallel (“As generally reflected in FIG. 7A, this embodiment allows for efficient writing and reading of a Page Stripe to the memory array since it allows all of the Pages of data that make up the Page Stripe to be written to the memory array 14 simultaneously or near-simultaneously by having the FLASH controller 10 issue commands to the various Lanes at, or close to, the same time.” Para 0078) or in a second mode of programming the pages sequentially (“Page Stripes are stored such that the Pages associated with the Page Stripe are written sequentially across the Lanes,” para 0085). Fuxa discloses all of the claim limitations from above, but does not explicitly teach “a first mode” and “a second mode” as claimed. Further, Fuxa does not explicitly teach “schedule” for programming. Hence, Fuxa does not explicitly teach “a processor configured to schedule a first superpage for programming in the first mode and a second superpage for programming in the second mode”. However, Fuxa teaches programming of memory pages simultaneously (para 0078 as cited above) and sequentially (para 0085 as cited above). Note that, as claimed, in the first mode, pages are programmed simultaneously; and in the second mode, pages are programmed sequentially. Further, Fuxa teaches “CPU 15” para 0034, and “Page Stripe 700 can be written ” para 0081, i.e., it can be written at a future time which means Page Stripe 700 can be scheduled for writing at a future time. Hence, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Fuxa with “a processor configured to schedule a first superpage for programming in the first mode and a second superpage for programming in the second mode”. The motivation would be that the invention improves the ability of efficiently and effectively protect, store, and retrieve data in a storage system, para 0005 of Fuxa . 07-21-aia AIA Claim s 2-10, 12-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Fuxa in view of Papandreou et al. US 2020/0066355 (“Papandreou”) . As per dependent claim 2, Fuxa discloses the device of claim 1. Fuxa teaches wherein the second superpage includes a plurality of channels, each of the channels including a plurality of dies (“Referring to FIG. 1, … the physical memory chips 0a-9b that make up the memory array 14 are divided into ten groups of two chips. For purposes of the physical addressing scheme, each group of two chips [dies] forms a ‘Lane,’ also sometimes referred to as a ‘Channel,’ such that there are ten Lanes or Channels within the memory array 14 (LANE0-LANE9).” Para 0046). Fuxa may not explicitly disclose, but in an analogous art in the same field of endeavor, Papandreou teaches and each of the dies having (“blocks from different dies and/or flash channels are grouped together, such that blocks from the same group can be read or written in parallel, thereby increasing overall bandwidth.” Para 0046) a lower page (LP), an upper page (UP) and an extra page (XP) (“In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076). Given the teaching of Papandreou, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Fuxa with “and each of the dies having a lower page (LP), an upper page (UP) and an extra page (XP)”. The motivation would be that the invention increases overall bandwidth of memory, para 0046 of Papandreou. As per dependent claim 3, Fuxa in combination with Papandreou discloses the device of claim 2. Fuxa teaches wherein the second mode is configured to program a page of a first type from a first die from each of the plurality of channels sequentially before programming a page of the first type from a second die from each of the plurality of channels sequentially (“Page Stripes are stored such that the Pages associated with the Page Stripe are written sequentially across the Lanes, but with the first Data Page of the Page Stripe written into a physical location associated with a Lane other than LANE0. These embodiments are illustrated in FIGS. 9A-9D” para 0085. Papandreou teaches “In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076. Based on this teaching of Papandreou, a page of a first type (for example, a lower page, or an upper page or an extra page) is programmed). The same motivation that was utilized for combining Fuxa and Papandreou as set forth in claim 2 is equally applicable to claim 3. As per dependent claim 4, Fuxa in combination with Papandreou discloses the device of claim 3. Fuxa may not explicitly disclose, but Papandreou teaches wherein the first type is lower page (LP), upper page (UP), or extra page (XP) (“In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076). The same motivation that was utilized for combining Fuxa and Papandreou as set forth in claim 3 is equally applicable to claim 4. As per dependent claim 5, Fuxa in combination with Papandreou discloses the device of claim 2. Fuxa teaches wherein the second mode is configured to program a page of a first type from each die from the channels sequentially before programming a page of a second type from each die from the channels sequentially (“Page Stripes are stored such that the Pages associated with the Page Stripe are written sequentially across the Lanes, but with the first Data Page of the Page Stripe written into a physical location associated with a Lane other than LANE0. These embodiments are illustrated in FIGS. 9A-9D” para 0085. Papandreou teaches “In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076. Based on this teaching of Papandreou, a page of a first type and a second type (for example, a lower page, or an upper page or an extra page) are programmed). The same motivation that was utilized for combining Fuxa and Papandreou as set forth in claim 2 is equally applicable to claim 5. As per dependent claim 6, Fuxa in combination with Papandreou discloses the device of claim 5. Fuxa may not explicitly disclose, but Papandreou teaches wherein the first type and the second type are different ones from: lower page (LP), upper page (UP) and extra page (XP) (“In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076). The same motivation that was utilized for combining Fuxa and Papandreou as set forth in claim 5 is equally applicable to claim 6. As per dependent claim 7, Fuxa in combination with Papandreou discloses the device of claim 2. Fuxa teaches wherein the second mode is configured to program a page of each of a plurality of types from a first die from each of the plurality of channels sequentially before programming a page of each of the plurality of types from a second die from each of the plurality of channels sequentially (“Page Stripes are stored such that the Pages associated with the Page Stripe are written sequentially across the Lanes, but with the first Data Page of the Page Stripe written into a physical location associated with a Lane other than LANE0. These embodiments are illustrated in FIGS. 9A-9D” para 0085. Papandreou teaches “In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076. Based on this teaching of Papandreou, a page of each type (for example, a lower page, and an upper page and an extra page) are programmed). The same motivation that was utilized for combining Fuxa and Papandreou as set forth in claim 2 is equally applicable to claim 7. As per dependent claim 8, Fuxa in combination with Papandreou discloses the device of claim 7. Fuxa may not explicitly disclose, but Papandreou teaches wherein the plurality of types include lower page (LP), upper page (UP), and extra page (XP) (“In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076). The same motivation that was utilized for combining Fuxa and Papandreou as set forth in claim 7 is equally applicable to claim 8. As per dependent claim 9, Fuxa in combination with Papandreou discloses the device of claim 2. Fuxa teaches wherein the second mode is configured to program a page of each of a plurality of types from a first die from a first channel sequentially before programming sequentially a page of each of the plurality of types from a second die from the first channel among the plurality of channels (“Page Stripes are stored such that the Pages associated with the Page Stripe are written sequentially across the Lanes, but with the first Data Page of the Page Stripe written into a physical location associated with a Lane other than LANE0. These embodiments are illustrated in FIGS. 9A-9D” para 0085. Papandreou teaches “In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076. Based on this teaching of Papandreou, a page of each type (for example, a lower page, and an upper page and an extra page) are programmed). The same motivation that was utilized for combining Fuxa and Papandreou as set forth in claim 2 is equally applicable to claim 9. As per dependent claim 10, Fuxa in combination with Papandreou discloses the device of claim 9. Fuxa may not explicitly disclose, but Papandreou teaches wherein the plurality of types include lower page (LP), upper page (UP), and extra page (XP) (“In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076). The same motivation that was utilized for combining Fuxa and Papandreou as set forth in claim 9 is equally applicable to claim 10. As per dependent claims 12-16, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 2, 3, 5, 7, and 9. As per dependent claims 18-19, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 5 and 6. As per dependent claim 20, Fuxa discloses the device of claim 17. The combination of Fuxa and Papandreou teaches wherein the plurality of dies include a first die and a second die; and the processor is operable to program a page of each of the plurality of page types from the first die sequentially before programming a page of each of the plurality of page types from the second die sequentially (“Page Stripes are stored such that the Pages associated with the Page Stripe are written sequentially across the Lanes, but with the first Data Page of the Page Stripe written into a physical location associated with a Lane other than LANE0. These embodiments are illustrated in FIGS. 9A-9D” para 0085. Papandreou teaches “In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0076. Based on this teaching of Papandreou, a page of each type (for example, a lower page, and an upper page and an extra page) are programmed). Given the teaching of Papandreou, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Fuxa with “page types”. The motivation would be that the invention increases overall bandwidth of memory, para 0046 of Papandreou. Conclusion Additional prior art references were considered by the Examiner but not applied in the art rejection. The references are Hinz US 2010/0030944 (“Hinz”), Sanders et al. US 7,627,712 (“Sanders”) and Tomic et al. US 2020/0117527 (“Tomic”). The references collectively negate the allowability of the claims of the instant invention. Hinz teaches “a page in plane 140 can be read or programmed parallel, i.e., at the same time, when a page of plane 141 is programmed.” Para 0019. Hinz further teaches “Another characteristic is that pages of an erase block must be written sequentially.” Para 0027. Therefore, Hinz negates the patentability of the independent claims and the dependent claims. Sanders teaches “writing of the second virtual page is performed substantially simultaneously to the writing of the first virtual page.” See independent claim 11. Therefore, Sanders also negates the patentability of the instant claims. Tomic teaches “blocks from different dies and/or flash channels are grouped together, such that blocks from the same group can be read or written in parallel,” para 0043. Tomic further teaches “In TLC, each wordline in a block contains 3 physical pages (i.e., a lower page, an upper page, and an extra page)” para 0069. Overall the additional references do not suggest that the instant claims are allowable. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUBAIR AHMED whose telephone number is (571)272-1655. The examiner can normally be reached 7:30AM - 5:00PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, HOSAIN T. ALAM can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZUBAIR AHMED/Examiner, Art Unit 2132 /HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132 Application/Control Number: 19/070,991 Page 2 Art Unit: 2132 Application/Control Number: 19/070,991 Page 3 Art Unit: 2132
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