DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/05/25 has considered by the examiner.
Drawings
The drawings received on 03/05/25 are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3,12 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 2024/0063720 A1).
Yang et al. disclose a control circuit and method for use in stackable multiphase power converter in Figures 2A-24.
Regarding claim 1. A multiphase power supply (Figure 2A), comprising: a master circuit (15) and n slave circuits (25, 35, 45), coupled in parallel with each other, n is an integer larger than zero; wherein the master circuit and all of the slave circuits each comprises: a first synchronous port (Y#), a second synchronous port (R#), a control stage, and a power stage; and wherein: the master circuit is configured to provide 1) a first clock signal (SYNC) via the first synchronous port, and 2) a second clock signal (RST) via the second synchronous port; and each of the slave circuits is configured to receive 1) the first clock signal via the first synchronous port, and 2) the second clock signal via the second synchronous port (see paragraphs 64-70).
Regarding claim 2. The multiphase power supply of claim 1, wherein: the second clock signal has a frequency that is (n+1) times of the first clock signal (see paragraph 99)
Regarding claim 3. The multiphase power supply of claim 1, wherein: the first clock signal has a first rising edge align to a first rising edge of the second clock signal (see paragraph 99).
Regarding claim 12. A multiphase power supply (Figure 2A), comprising: a circuit, having: a first synchronous port (Y#) and a second synchronous port (R#), wherein the first synchronous port is configured to receive an external clock signal (SYNC), and the second synchronous port is selectively configured to output a synchronized clock signal (RST); a power stage, configured to receive an input voltage; and a control stage, configured to control the power stage based on the external clock signal (see paragraphs 64-70).
Regarding claim 13. The multiphase power supply of claim 12, wherein the control stage comprises: a clock signal generator (91), coupled to the first synchronous port.
Allowable Subject Matter
Claims 17-20 are allowed over the cited prior art of record.
Claims 4-11 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 17 is allowed because the prior art of record fails to disclose or suggest a method including the limitation “generating a first clock signal and a second clock signal at the master circuit, and receiving the first clock signal and the second clock signal at each of the slave circuits; and initiating a master phase clock signal in response to a first rising edge of the first clock signal, to control a power stage at the master circuit; and initiating n slave phase clock signals in response to different rising edges of the second clock signal, to control a corresponding power stage at each of the slave circuits; wherein the master phase clock signal and all of the n slave phase clock signals are first reset in response to the first rising edge of the first clock signal before being initiated“ in addition to other limitations recited therein.
Dependent claims 18-20 are allowable by virtue of their dependency.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 is allowed because the prior art of record fails to disclose or suggest a multiphase power supply including the limitation “wherein: the master circuit and all the slave circuits each has a phase clock signal, which is configured to be reset in response to a first rising edge of the first clock signal“ in addition to other limitations recited therein.
Dependent claims 5-8 are allowable by virtue of their dependency.
Claim 9 is allowed because the prior art of record fails to disclose or suggest a multiphase power supply including the limitation “wherein the control stage in the master circuit comprises: a clock signal generator, configured to generate the first clock signal and the second clock signal; and a clock process circuit, configured to generate a master phase clock signal based on the first clock signal and the second clock signal; wherein the control stage is configured to control the power stage based on the master phase clock signal’ in addition to other limitations recited therein.
Claim 10 is allowed because the prior art of record fails to disclose or suggest a multiphase power supply including the limitation “wherein the control stage in each of the slave circuits comprises: a clock process circuit, configured to generate a corresponding slave phase clock signal in response to the first clock signal and the second clock signal“ in addition to other limitations recited therein.
Claim 11 is allowed because the prior art of record fails to disclose or suggest a multiphase power supply including the limitation “ the master circuit and all of the slave circuits each further comprises: a fault detect circuit, configured to detect a fault condition; and a connect switch, coupled between the first synchronous port and a reference ground“ in addition to other limitations recited therein.
Claim 14 is allowed because the prior art of record fails to disclose or suggest a multiphase power supply including the limitation “wherein the circuit is a master circuit, and wherein the multiphase power supply further comprises n slave circuits, each of the n slave circuits is coupled in parallel with the master circuit, wherein n is an integer larger than zero, and wherein each of the slave circuits respectively comprises: a first synchronous port, configured to receive a first clock signal provided by the master circuit; a second synchronous port, configured to receive a second clock signal provided by the master circuit; a control stage; and a power stage” in addition to other limitations recited therein.
Dependent claims 15-16 are allowable by virtue of their dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Azim et al. (US 6,952,789 B1) disclose a system and method for synchronizing a selected master circuit with a slave circuit by receiving and forwarding a control signal between the circuits and operating the circuits based on their received control signal.
Hsu (US 2025/0048408 A1) discloses a driving system having multiple driver circuits for cooperatively driving display panel and driver circuit thereof,
Huang et al. (US 12,470,145 B2) disclose a multiphase switching converter with stackable controllers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7 AM - 10 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADOLF D BERHANE/Primary Examiner, Art Unit 2838
