CTNF 19/071,090 CTNF 86657 DETAILED ACTION Claims 1-20 are pending. Priority: 5/24/2019(Provisional) Assignee: Texas Instruments Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after Ma19071090rch 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim (s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim (s) 1-20 of U.S. Patent No. 12,265,477 . Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations are obvious variations of each other as shown below . 19/071,090(Instant) 12,265,477(parent) A system, comprising: a first sub-cache; and a second sub-cache corresponding to a cache level same as the first sub-cache and configured to: receive a first write memory command that is associated with a write miss in the first sub-cache, the first write memory command associated with a first eviction tag; store first data associated with the first write memory command in a cache line of the second sub-cache; store the first eviction tag to indicate that the first data is associated with a write miss in the first sub-cache; receive a second write memory command for the cache line, the second write memory command associated with a second eviction tag; and merge the second eviction tag with the first eviction tag to generate a merged eviction tag. (additionally claim(s) 8 and 15) A system, comprising: a first sub-cache; and a second sub-cache, comprising : a set of cache lines configured to store data evicted from the first sub-cache; and a memory configured to store a set of eviction tags each corresponding to a respective cache line of the set of cache lines, wherein the second sub-cache is configured to: receive a first write memory command for a memory address, the first write memory command associated with a first eviction tag; store first data associated with the first write memory command in a cache line of the second sub-cache; store the first eviction tag in the memory; receive a second write memory command for the cache line, the second write memory command associated with a second eviction tag; and merge the second eviction tag with the first eviction tag to generate a merged eviction tag. 2 . The system of claim 1, wherein the first eviction tag is same as the second eviction tag, and wherein the merged eviction tag is same as the first eviction tag. (additionally claim(s) 9 and 17) 2. The system of claim 1, wherein the first eviction tag is same as the second eviction tag, and wherein the merged eviction tag is same as the first eviction tag. 3 . The system of claim 1, wherein the first eviction tag is different from the second eviction tag, and wherein the merged eviction tag includes both the first and second eviction tags. (additionally claim(s) 10 and 18) 3. The system of claim 1, wherein the first eviction tag is different from the second eviction tag, and wherein the merged eviction tag includes both the first and second eviction tags. 4 . The system of claim 3, wherein the second sub-cache is configured to evict the cache line based on the first eviction tag or the second eviction tag. 4. The system of claim 3, wherein the second sub-cache is configured to evict the first data of the cache line based on the first eviction tag or the second eviction tag 5 . The system of claim 1, wherein the first and second eviction tags are represented by respective values of a first bit field and a second bit field in an entry of a memory. (additionally claim(s) 12 and 19) 5. The system of claim 1, wherein the first and second eviction tags are represented by respective values of a first bit field and a second bit field in an entry of the memory. 6 . The system of claim 5, wherein the entry comprises one or more additional fields configured to store values indicating modified, exclusive, shared, and invalid (MESI) states of the first data of the cache line. (additionally claim(s) 13) 6. The system of claim 5, wherein the entry comprises one or more additional fields configured to store values indicating modified, exclusive, shared, and invalid (MESI) states of the first data of the cache line. 7 . The system of claim 1, wherein the second sub-cache is further configured to store data evicted from the first sub-cache. (additionally claim(s) 14 and 20) 7. The system of claim 6, wherein the one or more additional fields comprises a field storing a value that indicates whether the first data is associated with a write memory command that misses in the first sub-cache . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim (s) 1-20 are allowed. The following is an examiner’s statement of reasons for allowance. Claim(s) 1, 8 and 15 each contain the following limitations that distinguish the claims from the prior art: “…A system, comprising: a first sub-cache; and a second sub-cache corresponding to a cache level same as the first sub-cache and configured to: receive a first write memory command that is associated with a write miss in the first sub-cache, the first write memory command associated with a first eviction tag; store first data associated with the first write memory command in a cache line of the second sub-cache; store the first eviction tag to indicate that the first data is associated with a write miss in the first sub-cache; receive a second write memory command for the cache line, the second write memory command associated with a second eviction tag; and merge the second eviction tag with the first eviction tag to generate a merged eviction tag.…”. A related prior art is Pong(20060277352) where a new canonicalization tag is generated based on at least the current portion of tag field of a physical address. A data cache line is retrieved based on new tag when cache hit occurs. A cache hit and cache miss occurs when at least a portion of retrieved data cache line is about equal and not equal to the current portion of tag field, respectively by comparing at least the portion of retrieved data cache line and current portion of tag field. Stored data is retrieved from main memory when cache miss occurs. Die size of processor integrated circuit (IC) is reduced by reducing the amount of chip area dedicated to maintaining and storing tags. Smaller dies size reduces probability of defects, thus resulting in improved IC yield. 13-03 Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARVIND TALUKDAR whose telephone number is (303)297-4475. The examiner can normally be reached M-F, 10 am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Arvind Talukdar Primary Examiner Art Unit 2132 /ARVIND TALUKDAR/Primary Examiner, Art Unit 2132 Application/Control Number: 19/071,090 Page 2 Art Unit: 2132 Application/Control Number: 19/071,090 Page 3 Art Unit: 2132 Application/Control Number: 19/071,090 Page 4 Art Unit: 2132
Prosecution Insights