DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-10, 18 and 20 of U.S. Patent No. 12,166,184 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 are obvious variants and encompassed by claims 1, 3-10, 18 and 20 of U.S. Patent No. 12,166,184 B2, as shown in the table below.
Instant Application
U.S. Patent No. 12,166,184 B2
1. A device, comprising:
an array of memory cells, each of the memory cells programmable in a first mode to store more than one bit of data and programmable in a second mode to store one bit of weight usable in multiplication and accumulation operations performed at least in part in an analog form;
voltage drivers;
current digitizers; and
a circuit operable to perform the multiplication and accumulation operations using the memory cells, the voltage drivers and the current digitizers, when the memory cells are programmed in the second mode.
1. A device, comprising:
an image sensing pixel array operable to generate first data representative of an input image;
a memory cell array having memory cells, wherein threshold voltages of the memory cells are programmable in a first mode to store weight matrices and programmable in a second mode to store second data representative of an output image generated from the input image;
voltage drivers;
current digitizers;
an inference logic circuit operable to perform operations of multiplication and accumulation using the voltage drivers, the current digitizers, and a first portion of the memory cells when the first portion of the memory cells is programmed in the first mode to store the weight matrices used in generation of the output image;
a transceiver; and
a microprocessor configured to use the transceiver to communicate, to a computer system, a report identifying the output image stored in the memory cell array;
wherein the first portion of the memory cells programmed in the first mode to store the weight matrices is erasable and programmed in the second mode to store image data.
3. The device of claim 2, wherein each respective memory cell in the memory cell array is configured to store one bit per cell when programmed in the first mode; and the respective memory cell in the memory cell array is configured to store more than one bit per cell when programmed in the second mode.
2. The device of claim 1, further comprising:
an image sensing pixel array operable to generate first data representative of an input image;
wherein the circuit is further configured to generate an output image from the input image using weight data programmed in a portion of the memory cells in the second mode.
1. A device, comprising:
an image sensing pixel array operable to generate first data representative of an input image;
a memory cell array having memory cells, wherein threshold voltages of the memory cells are programmable in a first mode to store weight matrices and programmable in a second mode to store second data representative of an output image generated from the input image;
voltage drivers;
current digitizers;
an inference logic circuit operable to perform operations of multiplication and accumulation using the voltage drivers, the current digitizers, and a first portion of the memory cells when the first portion of the memory cells is programmed in the first mode to store the weight matrices used in generation of the output image;
a transceiver; and
a microprocessor configured to use the transceiver to communicate, to a computer system, a report identifying the output image stored in the memory cell array;
wherein the first portion of the memory cells programmed in the first mode to store the weight matrices is erasable and programmed in the second mode to store image data.
3. The device of claim 2, further comprising:
a transceiver; and
a microprocessor configured to use the transceiver to communicate, to a computer system, a report identifying the output image stored in the memory cell array in the first mode.
1. A device, comprising:
an image sensing pixel array operable to generate first data representative of an input image;
a memory cell array having memory cells, wherein threshold voltages of the memory cells are programmable in a first mode to store weight matrices and programmable in a second mode to store second data representative of an output image generated from the input image;
voltage drivers;
current digitizers;
an inference logic circuit operable to perform operations of multiplication and accumulation using the voltage drivers, the current digitizers, and a first portion of the memory cells when the first portion of the memory cells is programmed in the first mode to store the weight matrices used in generation of the output image;
a transceiver; and
a microprocessor configured to use the transceiver to communicate, to a computer system, a report identifying the output image stored in the memory cell array;
wherein the first portion of the memory cells programmed in the first mode to store the weight matrices is erasable and programmed in the second mode to store image data.
4. The device of claim 3, wherein the microprocessor is configured to receive, via the transceiver, weight matrices from the computer system to program the weight matrices in the second mode in a portion of the memory cells.
7. The device of claim 5, wherein the microprocessor is configured to receive, via the transceiver, the weight matrices from the computer system.
5. The device of claim 3, further comprising:
a first integrated circuit die having the image sensing pixel array;
a second integrated circuit die having the circuit;
a third integrated circuit die having the memory cells; and
an integrated circuit package configured to enclose at least the second integrated circuit die and the third integrated circuit die.
10. The device of claim 9, further comprising:
a first integrated circuit die having the image sensing pixel array;
a second integrated circuit die having the inference logic circuit;
a third integrated circuit die having the memory cell array; and
an integrated circuit package configured to enclose at least the second integrated circuit die and the third integrated circuit die.
6. The device of claim 1, wherein each respective memory cell in the memory cell array is configured to output, when programmed in the second mode and in response to a predetermined read voltage, a predetermined amount of current to represent a value of one stored in the respective memory cell.
4. The device of claim 3, wherein the respective memory cell in the memory cell array is configured to output, when programmed in the first mode and in response to a predetermined read voltage, a predetermined amount of current to represent a value of one stored in the respective memory cell.
7. The device of claim 6, wherein the respective memory cell in the memory cell array is configured to output, when programmed in the first mode and in response to a lower read voltage of a voltage region, a negligible amount of current and to output, when programmed in the first mode and in response to a higher read voltage of the voltage region, more than a threshold amount of current, to represent a value associated with the voltage region.
5. The device of claim 4, wherein the respective memory cell in the memory cell array is configured to output, when programmed in the second mode and in response to a lower read voltage of a voltage region, a negligible amount of current and to output, when programmed in the second mode and in response to a higher read voltage of the voltage region, more than a threshold amount of current, to represent a value associated with the voltage region.
8. The device of claim 6,
wherein the current digitizers are configured to convert currents, generated by memory cells programmed in the second mode and summed in bitlines, into column outputs representative of sums of bitwise multiplications.
9. The device of claim 8, wherein the memory cell array includes wordlines and bitlines; and the current digitizers are configured to convert currents, generated by memory cells programmed in the first mode and summed in bitlines, into column outputs representative of sums of bitwise multiplications.
9. The device of claim 1, wherein a portion of the memory cells is programmed in the first mode to store backup data usable to restore weight data programmed in the second mode into a second portion of the memory cells.
6. The device of claim 5, wherein a third portion of the memory cells is programmed in the second mode to store backup data usable to restore the weight matrices into the second portion of the memory cells.
10. The device of claim 1,
wherein the circuit comprises a plurality of parallel logic circuits each configured to evaluate an activation function of an artificial neuron.
8. The device of claim 5, wherein the inference logic circuit further comprises a plurality of parallel logic circuits each configured to evaluate an activation function of an artificial neuron; and the weight matrices include weight matrices of artificial neurons in an artificial neural network.
11. A method, comprising:
providing an array of memory cells in a device, each of the memory cells programmable in a first mode to store more than one bit of data and programmable in a second mode to store one bit of weight usable in multiplication and accumulation operations performed at least in part in an analog form;
performing, by a circuit configured in the device, the multiplication and accumulation operations using the memory cells, voltage drivers and current digitizers, when the memory cells are programmed in the second mode.
1. A device, comprising:
an image sensing pixel array operable to generate first data representative of an input image;
a memory cell array having memory cells, wherein threshold voltages of the memory cells are programmable in a first mode to store weight matrices and programmable in a second mode to store second data representative of an output image generated from the input image;
voltage drivers;
current digitizers;
an inference logic circuit operable to perform operations of multiplication and accumulation using the voltage drivers, the current digitizers, and a first portion of the memory cells when the first portion of the memory cells is programmed in the first mode to store the weight matrices used in generation of the output image;
a transceiver; and
a microprocessor configured to use the transceiver to communicate, to a computer system, a report identifying the output image stored in the memory cell array;
wherein the first portion of the memory cells programmed in the first mode to store the weight matrices is erasable and programmed in the second mode to store image data.
3. The device of claim 2, wherein each respective memory cell in the memory cell array is configured to store one bit per cell when programmed in the first mode; and the respective memory cell in the memory cell array is configured to store more than one bit per cell when programmed in the second mode.
12. The method of claim 11, further comprising:
generating, using an image sensing pixel array configured in the device, first data representative of an input image;
generating, by the circuit, an output image from the input image using weight data programmed in a portion of the memory cells in the second mode.
1. A device, comprising:
an image sensing pixel array operable to generate first data representative of an input image;
a memory cell array having memory cells, wherein threshold voltages of the memory cells are programmable in a first mode to store weight matrices and programmable in a second mode to store second data representative of an output image generated from the input image;
voltage drivers;
current digitizers;
an inference logic circuit operable to perform operations of multiplication and accumulation using the voltage drivers, the current digitizers, and a first portion of the memory cells when the first portion of the memory cells is programmed in the first mode to store the weight matrices used in generation of the output image;
a transceiver; and
a microprocessor configured to use the transceiver to communicate, to a computer system, a report identifying the output image stored in the memory cell array;
wherein the first portion of the memory cells programmed in the first mode to store the weight matrices is erasable and programmed in the second mode to store image data.
13. The method of claim 12, further comprising:
communicating, by a microprocessor configured in the device using a transceiver and to a computer system, a report identifying the output image stored in the memory cell array in the first mode.
1. A device, comprising:
an image sensing pixel array operable to generate first data representative of an input image;
a memory cell array having memory cells, wherein threshold voltages of the memory cells are programmable in a first mode to store weight matrices and programmable in a second mode to store second data representative of an output image generated from the input image;
voltage drivers;
current digitizers;
an inference logic circuit operable to perform operations of multiplication and accumulation using the voltage drivers, the current digitizers, and a first portion of the memory cells when the first portion of the memory cells is programmed in the first mode to store the weight matrices used in generation of the output image;
a transceiver; and
a microprocessor configured to use the transceiver to communicate, to a computer system, a report identifying the output image stored in the memory cell array;
wherein the first portion of the memory cells programmed in the first mode to store the weight matrices is erasable and programmed in the second mode to store image data.
14. The method of claim 13, further comprising:
receiving, by the microprocessor and via the transceiver, weight matrices from the computer system to program the weight matrices in the second mode in a portion of the memory cells.
7. The device of claim 5,
wherein the microprocessor is configured to receive, via the transceiver, the weight matrices from the computer system.
15. The method of claim 13,
wherein the image sensing pixel array is configured in a first integrated circuit die in the device;
wherein the circuit is configured in a second integrated circuit die in the device;
wherein the memory cells are configured in a third integrated circuit die in the device; and
wherein an integrated circuit package is configured to enclose at least the second integrated circuit die and the third integrated circuit die.
10. The device of claim 9, further comprising:
a first integrated circuit die having the image sensing pixel array;
a second integrated circuit die having the inference logic circuit;
a third integrated circuit die having the memory cell array; and
an integrated circuit package configured to enclose at least the second integrated circuit die and the third integrated circuit die.
16. The method of claim 11, wherein each respective memory cell in the memory cell array is configured to output, when programmed in the second mode and in response to a predetermined read voltage, a predetermined amount of current to represent a value of one stored in the respective memory cell.
4. The device of claim 3, wherein the respective memory cell in the memory cell array is configured to output, when programmed in the first mode and in response to a predetermined read voltage, a predetermined amount of current to represent a value of one stored in the respective memory cell.
17. The method of claim 16, wherein the respective memory cell in the memory cell array is configured to output, when programmed in the first mode and in response to a lower read voltage of a voltage region, a negligible amount of current and to output, when programmed in the first mode and in response to a higher read voltage of the voltage region, more than a threshold amount of current, to represent a value associated with the voltage region.
5. The device of claim 4, wherein the respective memory cell in the memory cell array is configured to output, when programmed in the second mode and in response to a lower read voltage of a voltage region, a negligible amount of current and to output, when programmed in the second mode and in response to a higher read voltage of the voltage region, more than a threshold amount of current, to represent a value associated with the voltage region.
18. The method of claim 16, further comprising:
converting, by the current digitizers, currents generated by memory cells programmed in the second mode and summed in bitlines, into column outputs representative of sums of bitwise multiplications.
9. The device of claim 8,
wherein the memory cell array includes wordlines and bitlines; and the current digitizers are configured to convert currents, generated by memory cells programmed in the first mode and summed in bitlines, into column outputs representative of sums of bitwise multiplications.
19. An apparatus, comprising:
a surveillance camera, comprising:
an integrated circuit device, having:
an array of memory cells, each of the memory cells programmable in a first mode to store more than one bit of data and programmable in a second mode to store one bit of weight usable in multiplication and accumulation operations performed at least in part in an analog form;
voltage drivers;
current digitizers; and
a circuit operable to perform the multiplication and accumulation operations using the memory cells, the voltage drivers and the current digitizers, when the memory cells are programmed in the second mode;
a transceiver;
a microprocessor configured to receive weight matrices for programming the weight matrices in the second mode in a portion of the memory cells.
18. An apparatus, comprising:
a surveillance camera, comprising:
a lens;
an integrated circuit device, having:
a first integrated circuit die having an image sensing pixel array operable to generate first data representative of input images projected by the lens on the image sensing pixel array;
a second integrated circuit die having an image processing logic circuit, and an inference logic circuit;
a third integrated circuit die having a plurality of layers, each containing wordlines, bitlines, and memory cells connected to the wordlines to receive voltages and connected to bitlines to output currents;
an integrated circuit package configured to enclose the first integrated circuit die, the second integrated circuit die and the third integrated circuit die; and
an interface;
a transceiver;
a microprocessor; and
an interconnect connected to the interface, the transceiver, and the microprocessor;
wherein threshold voltages of first memory cells in a first plurality of layers in the third integrated circuit die are programmable in a first mode to store weight matrices;
wherein threshold voltages of second memory cells in a second plurality of layers in the third integrated circuit die are programmable in a second mode to store second data representative of output images generated from the input images;
wherein the inference logic circuit is configured to perform operations of multiplication and accumulation using the first memory cells programmed in the first mode to store the weight matrices;
wherein the image processing logic circuit is configured to generate the second data based on results of the operations of multiplication and accumulation; and
wherein the microprocessor configured to use the transceiver to communicate, to a computer system, reports identifying the output images stored in the third integrated circuit die.
20. The apparatus of claim 19, wherein a respective memory cell in the third integrated circuit die is configured to store one bit per cell when programmed in the first mode; and the respective memory cell is configured to store more than one bit per cell when programmed in the second mode; and
wherein the respective memory cell is configured to output, when programmed in the first mode and in response to a predetermined read voltage, a predetermined amount of current to represent a value of one stored in the respective memory cell; and the respective memory cell is configured to output, when programmed in the second mode and in response to a lower read voltage of a voltage region, a negligible amount of current and to output, when programmed in the second mode and in response to a higher read voltage of the voltage region, more than a threshold amount of current, to represent a value associated with the voltage region.
20. The apparatus of claim 19, wherein the integrated circuit device is configured to store an output image, generated from an input image captured by the surveillance camera in a portion of the memory cells in the first mode.
18. An apparatus, comprising:
a surveillance camera, comprising:
a lens;
an integrated circuit device, having:
a first integrated circuit die having an image sensing pixel array operable to generate first data representative of input images projected by the lens on the image sensing pixel array;
a second integrated circuit die having an image processing logic circuit, and an inference logic circuit;
a third integrated circuit die having a plurality of layers, each containing wordlines, bitlines, and memory cells connected to the wordlines to receive voltages and connected to bitlines to output currents;
an integrated circuit package configured to enclose the first integrated circuit die, the second integrated circuit die and the third integrated circuit die; and
an interface;
a transceiver;
a microprocessor; and
an interconnect connected to the interface, the transceiver, and the microprocessor;
wherein threshold voltages of first memory cells in a first plurality of layers in the third integrated circuit die are programmable in a first mode to store weight matrices;
wherein threshold voltages of second memory cells in a second plurality of layers in the third integrated circuit die are programmable in a second mode to store second data representative of output images generated from the input images;
wherein the inference logic circuit is configured to perform operations of multiplication and accumulation using the first memory cells programmed in the first mode to store the weight matrices;
wherein the image processing logic circuit is configured to generate the second data based on results of the operations of multiplication and accumulation; and
wherein the microprocessor configured to use the transceiver to communicate, to a computer system, reports identifying the output images stored in the third integrated circuit die.
With respect to independent claims 1, 11 and 19 of the application, the claims are not patentably distinct from claims 1-10 and 19-20 of U.S. Patent No. 12,266,184 B1. The instant claims recite the memory cells as being programmable in a “first mode” to store more than one it of data and programmable in a “second mode” to store one bit of weight usable in multiplication and accumulation operations, whereas the labels “first mode” and “second mode” are reversed in the claims of U.S. Patent No. 12,266,184 B1.
The instant dependent claims 1, 11 and 19 are broader than the patented claims in that they omit certain limitations expressly recited in the patented claims; however, the patent claims claim the same underlying architecture of memory cells selectively usable for multi-bit data storage and one-bit weight storage. Therefore, the claims are directed to an obvious variant of the same invention claimed in U.S. Patent No. 12,266,184 B1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6-8, 10-11 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran (US 2023/0053608 A1) in view of Roohparvar (US 2007/0133249 A1).
As to claim 1, Tran discloses a device (Fig.34, 35A and 35B: VMM system 3400 and hybrid memory systems 3500/3550), comprising:
an array of memory cells (Fig.35A: hybrid array 3501), each of the memory cells programmable in a first mode to store more than one bit of data ([0146]: “In the first mode, hybrid array 3501 operates as a non-volatile memory storage to store or retrieve weight data in multi-bit digital form”) and programmable in a second mode ([0148]: “In the second mode, hybrid array 3501 operates as a VMM in an analog neural memory to store weight data in analog multi-level form, meaning each cell stores analog multilevels that has continuous analog values between levels”) 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer.”);
voltage drivers (Fig.4: row decoder 3402, high-voltage decoder 3403, column decoder 3404, bitline drivers 3405, input circuit 3406 bias generator 3409, and high-voltage generation block 3410);
current digitizers ([0140]: “The output circuit 3407 may include circuits such as a ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), APC (analog to pulse(s) converter, analog to time modulated pulse converter), or any other type of converters.”); and
a circuit operable to perform the multiplication and accumulation operations (Fig.34: analog circuitry 3415 and control engine 3416) using the memory cells, the voltage drivers and the current digitizers ([0139-0141]: VMM array 3401 is used with row/high-voltage/column decoders, bitline drivers, input circuit, output circuit, analog circuitry, and control engine), when the memory cells are programmed in the second mode (Fig.36; steps 3602-3608; [0157-0163]: VMM analog neural operation beginning at step 3602, enabling rows/columns, partial sum storage, and summation/activation/pooling to generate neural output).
Tran does not expressly disclose each of the memory cells is programmable in a second mode to store one bit of weight.
However, Roohparvar teaches each of the memory cells is programmable in a second mode to store one bit of weight ([0027]: SLC programming, i.e., single-bit-per-cell programming).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Tran with the teaching of Roohparvar such that each of the memory cells is programmable in a second mode to store one bit of weight, so as to provide reliable one-bit weight storage for analog computation while also allowing higher-density storage when memory cells are used for data storage.
As to claim 6, Tran in view of Roohparvar discloses the device of claim 1, wherein each respective memory cell in the memory cell array is configured to output, when programmed in the second mode and in response to a predetermined read voltage, a predetermined amount of current to represent a value of one stored in the respective memory cell (Roohparvar: [0027]: “Each cell can be programmed as a single bit per cell (i.e., single level cell--SLC) or multiple bits per cell (i.e., multiple level cell--MLC). Each cell's threshold voltage (V.sub.t) determines the data that is stored in the cell”).
As to claim 7, Tran in view of Roohparvar discloses the device of claim 6, wherein the respective memory cell in the memory cell array is configured to output, when programmed in the first mode and in response to a lower read voltage of a voltage region, a negligible amount of current and to output, when programmed in the first mode and in response to a higher read voltage of the voltage region, more than a threshold amount of current, to represent a value associated with the voltage region ([0027-0030]: determining the stored value by applying read voltages and sensing whether the cell conducts, thereby identifying the voltage region associated with the stored data value).
As to claim 8, Tran in view of Roohparvar discloses the device of claim 6, wherein the current digitizers are configured to convert currents, generated by memory cells programmed in the second mode and summed in bitlines, into column outputs representative of sums of bitwise multiplications ([0147]: the configurable output circuitry includes a current-to-voltage converter and ADC block that receives analog current outputs from columns of the hybrid memory array and generates digital output bits).
As to claim 10, Tran in view of Roohparvar discloses the device of claim 1, wherein the circuit comprises a plurality of parallel logic circuits (Fig.35A; [0145]: configurable output circuitry 3503 including ITV+ADC block 3506) each configured to evaluate an activation function of an artificial neuron (Fig.36; [0157-0163]: summation/activation/pooling operations).
Method claims 11 and 16-18 recite substantially similar subject matter as disclosed in claims 1 and 6-8, respectively; therefore, they are rejected for the same reasons.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran (US 2023/0053608 A1) in view of Roohparvar (US 2007/0133249 A1) as applied to claim 1 above, and further in view of Rom et al. (US 2020/0185027 A1).
As to claim 9, Tran in view of Roohparvar discloses the device of claim 1, but fails to disclose a portion of the memory cells is programmed in the first mode to store backup data usable to restore weight data programmed in the second mode into a second portion of the memory cells.
However, Rom et al. teaches a portion of the memory cells is programmed in the first mode to store backup data usable to restore weight data programmed in the second mode into a second portion of the memory cells (Fig.8 and 9; [0073]: reading synaptic weights stored in the first set of NAND elements into a latch, modifying or replacing the synaptic weights, and writing the synaptic weights into another set of NAND element, there the NAND elements may include SLC and MLC elements).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Tran and Roohparvar with the teaching of Rom et al. to incorporate a portion of the memory cells is programmed in the first mode to store backup data usable to restore weight data programmed in the second mode into a second portion of the memory cells, so as to improve the reliability of the neural-memory system by preserving recoverable weight data while still allowing the memory cells to be used for analog multiplication-and-accumulation operations.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiong et al. (US 2022/0116569 A1) in view of Tran (US 2023/0053608 A1) and Roohparvar (US 2007/0133249 A1).
As to claim 19, Xiong et al. discloses an apparatus (Figs.1-3: surveillance system), comprising:
a surveillance camera (Fig.1: camera 104), comprising:
a transceiver ([0059-0060]: transmitting image/video data from the surveillance system to a remote/cloud server and receiving a retrained neural network and weights back form the server);
a microprocessor configured to receive weight matrices ([0065]: the remote server transmits new weights back to the controller 308 and stores them in memory device 306)
Xiong et al. fails to disclose an integrated circuit device, having:
an array of memory cells, each of the memory cells programmable in a first mode to store more than one bit of data and programmable in a second mode to store one bit of weight usable in multiplication and accumulation operations performed at least in part in an analog form;
voltage drivers;
current digitizers; and
a circuit operable to perform the multiplication and accumulation operations using the memory cells, the voltage drivers and the current digitizers, when the memory cells are programmed in the second mode;
the micro processor configured to receive weight matrices for programming weight matrices in the second mode in a portion of the memory cells.
However, Tran teaches an integrated circuit device (Fig.34, 35A and 35B: VMM system 3400 and hybrid memory systems 3500/3550), having:
an array of memory cells (Fig.35A: hybrid array 3501), each of the memory cells programmable in a first mode to store more than one bit of data ([0146]: “In the first mode, hybrid array 3501 operates as a non-volatile memory storage to store or retrieve weight data in multi-bit digital form”) and programmable in a second mode ([0148]: “In the second mode, hybrid array 3501 operates as a VMM in an analog neural memory to store weight data in analog multi-level form, meaning each cell stores analog multilevels that has continuous analog values between levels”) 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer.”);
voltage drivers (Fig.4: row decoder 3402, high-voltage decoder 3403, column decoder 3404, bitline drivers 3405, input circuit 3406 bias generator 3409, and high-voltage generation block 3410);
current digitizers ([0140]: “The output circuit 3407 may include circuits such as a ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), APC (analog to pulse(s) converter, analog to time modulated pulse converter), or any other type of converters.”); and
a circuit operable to perform the multiplication and accumulation operations (Fig.34: analog circuitry 3415 and control engine 3416) using the memory cells, the voltage drivers and the current digitizers ([0139-0141]: VMM array 3401 is used with row/high-voltage/column decoders, bitline drivers, input circuit, output circuit, analog circuitry, and control engine), when the memory cells are programmed in the second mode (Fig.36; steps 3602-3608; [0157-0163]: VMM analog neural operation beginning at step 3602, enabling rows/columns, partial sum storage, and summation/activation/pooling to generate neural output);
the micro processor configured to receive weight matrices for programming weight matrices in the second mode in a portion of the memory cells ([0143-0148]: programming/storing weight data in memory cells of a hybrid memory array for analog neural/VMM operation).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Xiong et al. with the teaching of Tran to incorporate an integrated circuit device, having:
an array of memory cells, each of the memory cells programmable in a first mode to store more than one bit of data and programmable in a second mode to store one bit of weight usable in multiplication and accumulation operations performed at least in part in an analog form; voltage drivers; current digitizers; and a circuit operable to perform the multiplication and accumulation operations using the memory cells, the voltage drivers and the current digitizers, when the memory cells are programmed in the second mode; the micro processor configured to receive weight matrices for programming weight matrices in the second mode in a portion of the memory cells, so as to perform the local inference operations using the received weights.
The combination of Xiong et al. and Tran does not expressly disclose each of the memory cells is programmable in a second mode to store one bit of weight.
However, Roohparvar teaches each of the memory cells is programmable in a second mode to store one bit of weight ([0027]: SLC programming, i.e., single-bit-per-cell programming).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Xiong et al. and Tran with the teaching of Roohparvar such that each of the memory cells is programmable in a second mode to store one bit of weight, so as to provide reliable one-bit weight storage for analog computation while also allowing higher-density storage when memory cells are used for data storage.
Allowable Subject Matter
Claims 2-5, 12-15 and 20 would be allowable if the double patenting rejection set forth in this Office action is overcome, and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/ZHENZHEN WU/Examiner, Art Unit 2637
/SINH TRAN/Supervisory Patent Examiner, Art Unit 2637
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