DETAILED ACTION
The instant application having Application No. 19/071,558 has a total of 21 claims pending in the application, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made of applicant’s claim for foreign priority based on an application filed in REPUBLIC OF KOREA on 10/21/2024. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/5/2025 is being considered by the examiner.
Claim Language
Claims 14-21 recite limitations which, as claimed, are conditionally executed without accounting for the possibility of the condition failing to trigger.
The limitations in the claims following “when” are not positively recited in the claims, as the limitations, as claimed, are conditionally executed without accounting for the possibility of the condition failing to occur. The method may never be required to execute the conditions because “when” may be interpreted as a temporal conditional precedent that may never be reached within the scope of the claim under the broadest reasonable interpretation.
Additionally, for claims containing limitations recited to occur responsive to a condition, an occurrence of said condition is also required to be positively recited in the claims.
The examiner recommends amending instances of limitations reliant upon the language “when” to recite, for example, “in response to”, and to also provide recitations of occurrence of the conditions required for the relevant limitations.
See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding “The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim”); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 14, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Gim et al. (US 20220012181 A1) in view of Yoon et al. (US 20160062821 A1) in view of Han et al. (US 20220326873 A1) in view of Kato et al. (US 20130219244 A1).
As per claim 1,
1. A data storage apparatus comprising: a memory device; and a memory controller configured to control the memory device, wherein the memory controller includes an address mapping manager configured to: [Gim teaches a memory system including a memory device and a controller having a processor and address management module (para. 27-28; figs. 1-3 and associated paragraph)] access the memory device based on an address mapping table including a logical-virtual address table and a virtual-physical address table, and [On receiving a write request with a logical address, the logical address is used to generate a virtual address stored in a first table with the logical address (logical-virtual address table), the virtual address is used to generate a physical address stored in a second table with the virtual address (virtual-physical address table), and the physical address as generated and stored in the second table is used in a write operation (para. 60-63; figs. 4A-4C, 7 and associated paragraphs)]
Gim does not explicitly disclose, but Yoon discloses:
when an error occurs in a first page of the memory device: search for a virtual block address related to the first page with reference to the virtual-physical address table without accessing the logical-virtual address table, and [Gim as shown above teaches a physical addressed generated based on a virtual address and stored in the second table, the physical address having block number and page number (see above; Gim: para. 63); Gim does not explicitly disclose, but Yoon teaches, responsive to detecting an error, translating physical address related to the error to a virtual address and potentially decommissioning area related to the physical address (para. 36-38; fig. 3 and associated paragraphs)]
[Gim in view of Yoon as shown above teaches the second table mapping a virtual address to a physical address and translating a physical address to a virtual address responsive to an error, but it does not explicitly disclose using the second table to determine the virtual address based on the physical address; Han teaches performing a read operation using a physical address, and in association with an ECC failure, using a logical-to-physical mapping table to determine the logical address mapped to the physical address (para. 67, 73-74, 78; figs. 7-8 and associated paragraphs)]
Gim and Yoon are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim and Yoon, to modify the disclosures by Gim to include disclosures by Yoon since they both teach memory access and data storage, wherein Yoon is directed towards error correction mechanism for improved reliability, availability, and serviceability of electronic device including a memory (para. 40). Therefore, it would be applying a known technique (using a physical address of an error to determine the corresponding virtual address) to a known device (memory device comprising a table indicating mapping of a virtual address to a physical address) ready for improvement to yield predictable results (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined in order to provide for comprehensive determination of addresses affected by an error). MPEP 2143
Gim, Yoon, and Han are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon and Han, to modify the disclosures by Gim in view of Yoon to include disclosures by Han since they both teach memory access and data storage, wherein Han is directed towards address management and meta data recovery (para. 2, 7). Therefore, it would be applying a known technique (determining a logical address associated with a physical address by using a logical-to-physical translation table) to a known device (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined) ready for improvement to yield predictable results (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined using the table mapping virtual addresses to physical addresses in order to provide for reduced overhead from maintaining separate lookup tables). MPEP 2143
Gim in view of Yoon in view of Han does not explicitly disclose, but Kato teaches:
register a virtual address including a searched virtual block address in a reuse table. [Kato teaches an error block table for recording a block in which an ECC error has occurred, the error block table including a logical block address and physical block address (para. 44; fig. 4 and associated paragraphs; see para. 35 on the logical block address being defined by the memory controller)]
Gim, Yoon, Han, and Kato are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han and Kato, to modify the disclosures by Gim in view of Yoon in view of Han to include disclosures by Kato since they both teach memory access and data storage, wherein Kato is directed towards improved management of blocks having errors (para. 3-12). Therefore, it would be applying a known technique (error block table recording an internally defined logical address associated with an error block) to a known device (memory device for determining a virtual address associated with a physical address having an error) ready for improvement to yield predictable results (memory device for determining a virtual address associated with a physical address having an error and storing the virtual address in an error block table for greater efficiency in referencing addresses associated with errors). MPEP 2143
As per claim 14,
14. An operating method of a data storage apparatus including a memory device and a memory controller configured [Gim teaches a memory system including a memory device and a controller having a processor and address management module (para. 27-28; figs. 1-3 and associated paragraphs)] to access the memory device based on an address mapping table including a logical-virtual address table and a virtual-physical address table, [On receiving a write request with a logical address, the logical address is used to generate a virtual address stored in a first table with the logical address (logical-virtual address table), the virtual address is used to generate a physical address stored in a second table with the virtual address (virtual-physical address table), and the physical address as generated and stored in the second table is used in a write operation (para. 60-63; figs. 4A-4C, 7 and associated paragraphs)]
Gim does not explicitly disclose, but Yoon discloses:
the method comprising: the memory controller searching for, when an error occurs in a first page of the memory device, a virtual block address related to the first page with reference to the virtual-physical address table without accessing the logical-virtual address table; and [Gim as shown above teaches a physical addressed generated based on a virtual address and stored in the second table, the physical address having block number and page number (see above; Gim: para. 63); Gim does not explicitly disclose, but Yoon teaches, responsive to detecting an error, translating physical address related to the error to a virtual address and potentially decommissioning area related to the physical address (para. 36-38; fig. 3 and associated paragraphs)]
[Gim in view of Yoon as shown above teaches the second table mapping a virtual address to a physical address and translating a physical address to a virtual address responsive to an error, but it does not explicitly disclose using the second table to determine the virtual address based on the physical address; Han teaches performing a read operation using a physical address, and in association with an ECC failure, using a logical-to-physical mapping table to determine the logical address mapped to the physical address (para. 67, 73-74, 78; figs. 7-8 and associated paragraphs)]
Gim and Yoon are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim and Yoon, to modify the disclosures by Gim to include disclosures by Yoon since they both teach memory access and data storage, wherein Yoon is directed towards error correction mechanism for improved reliability, availability, and serviceability of electronic device including a memory (para. 40). Therefore, it would be applying a known technique (using a physical address of an error to determine the corresponding virtual address) to a known device (memory device comprising a table indicating mapping of a virtual address to a physical address) ready for improvement to yield predictable results (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined in order to provide for comprehensive determination of addresses affected by an error). MPEP 2143
Gim, Yoon, and Han are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon and Han, to modify the disclosures by Gim in view of Yoon to include disclosures by Han since they both teach memory access and data storage, wherein Han is directed towards address management and meta data recovery (para. 2, 7). Therefore, it would be applying a known technique (determining a logical address associated with a physical address by using a logical-to-physical translation table) to a known device (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined) ready for improvement to yield predictable results (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined using the table mapping virtual addresses to physical addresses in order to provide for reduced overhead from maintaining separate lookup tables). MPEP 2143
Gim in view of Yoon in view of Han does not explicitly disclose, but Kato teaches:
the memory controller registering a virtual address including a searched virtual block address in a reuse table. [Kato teaches an error block table for recording a block in which an ECC error has occurred, the error block table including a logical block address (para. 44; fig. 4 and associated paragraphs; see para. 35 on the logical block address being defined by the memory controller)]
Gim, Yoon, Han, and Kato are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han and Kato, to modify the disclosures by Gim in view of Yoon in view of Han to include disclosures by Kato since they both teach memory access and data storage, wherein Kato is directed towards improved management of blocks having errors (para. 3-12). Therefore, it would be applying a known technique (error block table recording an internally defined logical address associated with an error block) to a known device (memory device for determining a virtual address associated with a physical address having an error) ready for improvement to yield predictable results (memory device for determining a virtual address associated with a physical address having an error and storing the virtual address in an error block table for greater efficiency in referencing addresses associated with errors). MPEP 2143
As per claim 21, Gim in view of Yoon in view of Han in view of Kato teaches claim 14 as shown above and further teaches:
21. The method of claim 14, wherein when the virtual address related to the first page is registered in the reuse table, the memory controller does not register a logical address related to the first page in the reuse table. [Gim in view of Yoon in view of Han in view of Kato as shown above teaches storing a virtual address and physical address in the error block table (see claim 14 above; Yoon: para. 36-38; Kato: 35, 44)]
Gim, Yoon, Han, and Kato are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han and Kato, to modify the disclosures by Gim in view of Yoon in view of Han to include disclosures by Kato since they both teach memory access and data storage, wherein Kato is directed towards improved management of blocks having errors (para. 3-12). Therefore, it would be applying a known technique (error block table recording an internally defined logical address associated with an error block) to a known device (memory device for determining a virtual address associated with a physical address having an error) ready for improvement to yield predictable results (memory device for determining a virtual address associated with a physical address having an error and storing the virtual address in an error block table for greater efficiency in referencing addresses associated with errors). MPEP 2143
Claims 2-3, 8-9, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Gim et al. (US 20220012181 A1) in view of Yoon et al. (US 20160062821 A1) in view of Han et al. (US 20220326873 A1) in view of Kato et al. (US 20130219244 A1) in view of Yudanov (US 20210294746 A1).
As per claim 2, Gim in view of Yoon in view of Han in view of Kato teaches claim 1 as shown above and further teaches:
2. The data storage apparatus of claim 1, wherein the address mapping manager is configured to: generate a first virtual address corresponding to a first logical address of data to be written in the memory device, the first virtual address comprising a pair consisting of a first virtual block address and a first physical page address, store the first virtual address in the logical-virtual address table by allocating the first virtual address to the first logical address when a logical address is not allocated to the first virtual address, [Gim as shown above teaches converting a logical address to a virtual address comprising a virtual block number and offset and storing the logical address and the virtual address in the first table (para. 60), where the virtual block number and offset, necessarily associated with a virtual block, may correspond to a virtual block address, and where Gim does not require abstaining from storing the virtual address when a logical address is not allocated to the virtual address] and store the first virtual block address in the virtual-physical address table by mapping the first virtual block address to a first physical block address. [Gim teaches a second table having the virtual address mapped to a physical address comprising a physical block number and a page number (para. 63)]
Gim in view of Yoon in view of Han in view of Kato does not explicitly disclose, but Yudanov discloses:
and a first physical page address [Gim in view of Yoon in view of Han in view of Kato as shown above teaches a first table comprising a logical address and a virtual address comprising a virtual block number and an offset, and a second table comprising the virtual address and a physical address comprising a physical block number and page number; it does not explicitly disclose the first table also comprising a physical page address, but Yudanov provides for tables comprising virtual to logical address and further teaches that such tables may further associate a physical address as well (para. 12), where it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Gim in view of Yoon in view of Han in view of Kato, providing for a table comprising logical and virtual address translation with the virtual address being separately translated to a physical address, and disclosures by Yudanov, providing for tables having virtual to logical addressing further being associated with a physical address, to provide for a combination where the first table having logical and virtual address translation may further be updated to include the corresponding physical address in order to provide for greater flexibility in referencing translation information, where the physical address comprising physical block number and physical page number may correspond to a physical page address; where Gim in view of Yoon in view of Han in view of Kato as shown previously teaches accessing the second table for determining a virtual address based on a physical address (see claim 1 above; Han: para. 67, 73-74, 78), although the additional combination with Yudanov may result in two tables having virtual and physical addresses, it would further have been obvious for one of ordinary skill in the arts, in the event of having multiple tables with virtual-physical translations, to reference less than all the tables (i.e. one) in finding a virtual address based on a physical address to provide for faster translation latency.]
Gim, Yoon, Han, Kato, and Yudanov are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han in view of Kato and Yudanov, to modify the disclosures by Gim in view of Yoon in view of Han in view of Kato to include disclosures by Yudanov since they both teach memory access and data storage, wherein Yudanov is directed towards shared addressing and contexts (para. 1, 14). Therefore, it would be applying a known technique (tables configured to map virtual and logical addresses and further associable with physical addresses) to a known device (memory device performing logical to virtual to physical address translation and maintaining a logical to virtual addressing table) ready for improvement to yield predictable results (memory device performing logical to virtual to physical address translation and maintaining a logical to virtual addressing table, the logical to virtual addressing table configurable to also maintain corresponding physical address as well in order to provide for greater flexibility in referencing translation information). MPEP 2143
As per claim 3, Gim in view of Yoon in view of Han in view of Kato in view of Yudanov teaches claim 2 as shown above and further teaches:
3. The data storage apparatus of claim 2, wherein when the first virtual address is registered in the reuse table, the address mapping manager is configured to allocate the first virtual address to the first logical address, map the first virtual address and the first logical address, and store a mapping result in the reuse table. [Gim in view of Yoon in view of Han in view of Kato in view of Yudanov as shown above teaches, in writing data, mapping a logical address to a virtual address and physical address in a first table, the virtual address further being stored in a second table with the physical address (see claims 1-2 above; Gim: para. 60-63; Yudanov: para. 12); in storing a virtual address to the error block table, responsive to an error associated with accessing a physical address, a table, such as the second table, may be referenced to determining the corresponding virtual address (see claims 1-2 above; Gim: para. 60-63; Yoon: para. 36-38; Han: para. 67, 73-74, 78; Kato: para. 44)]
Gim and Yoon are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim and Yoon, to modify the disclosures by Gim to include disclosures by Yoon since they both teach memory access and data storage, wherein Yoon is directed towards error correction mechanism for improved reliability, availability, and serviceability of electronic device including a memory (para. 40). Therefore, it would be applying a known technique (using a physical address of an error to determine the corresponding virtual address) to a known device (memory device comprising a table indicating mapping of a virtual address to a physical address) ready for improvement to yield predictable results (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined in order to provide for comprehensive determination of addresses affected by an error). MPEP 2143
Gim, Yoon, and Han are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon and Han, to modify the disclosures by Gim in view of Yoon to include disclosures by Han since they both teach memory access and data storage, wherein Han is directed towards address management and meta data recovery (para. 2, 7). Therefore, it would be applying a known technique (determining a logical address associated with a physical address by using a logical-to-physical translation table) to a known device (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined) ready for improvement to yield predictable results (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined using the table mapping virtual addresses to physical addresses in order to provide for reduced overhead from maintaining separate lookup tables). MPEP 2143
Gim, Yoon, Han, and Kato are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han and Kato, to modify the disclosures by Gim in view of Yoon in view of Han to include disclosures by Kato since they both teach memory access and data storage, wherein Kato is directed towards improved management of blocks having errors (para. 3-12). Therefore, it would be applying a known technique (error block table recording an internally defined logical address associated with an error block) to a known device (memory device for determining a virtual address associated with a physical address having an error) ready for improvement to yield predictable results (memory device for determining a virtual address associated with a physical address having an error and storing the virtual address in an error block table for greater efficiency in referencing addresses associated with errors). MPEP 2143
As per claim 8,
A memory controller comprising: an address mapping table storage [Gim teaches a memory system including a memory device and a controller having a processor, address management module, and a memory for storing mapping tables (para. 27-28, 60; figs. 1-3 and associated paragraph)] including a logical-virtual address table, a virtual-physical address table, and a reuse table; an address conversion circuit configured to: generate a first virtual address corresponding to a first logical address of data to be written in a memory device, the first virtual address comprising a pair consisting of a first virtual block address and a first physical page address, store the first virtual address in the logical-virtual address table by mapping the first virtual address to the first logical address when a logical address is not allocated to the first virtual address, and store the first virtual block address in the virtual-physical address table by mapping the first virtual block address to a first physical block address; and [On receiving a write request with a logical address, the logical address is used to generate a virtual address, comprising a virtual block number and offset, stored in a first table with the logical address (logical-virtual address table), the virtual address is used to generate a physical address, comprising a physical block number and a page number, stored in a second table with the virtual address (virtual-physical address table), and the physical address as generated and stored in the second table is used in a write operation (para. 60-63; figs. 4A-4C, 7 and associated paragraphs), where the virtual block number and offset, necessarily associated with a virtual block, may correspond to a virtual block address, and where Gim does not require abstaining from storing the virtual address in the first table when a logical address is not allocated to the virtual address]
Gim does not explicitly disclose, but Yoon discloses:
a reuse circuit configured to: receive an error physical block address of the memory device, search for an error virtual block address mapped to the error physical block address with reference to the virtual-physical address table without accessing the logical-virtual address table, [Gim as shown above teaches a second table mapping a virtual address to a physical address, the physical address having block and page number (see above; Gim: para. 63); Gim does not explicitly disclose, but Yoon teaches, responsive to detecting an error, translating physical address related to the error to a virtual address and potentially decommissioning area related to the physical address (para. 36-38; fig. 3 and associated paragraphs; see para. 37 on an error handler receiving a physical address relating to the error)]
[Gim in view of Yoon as shown above teaches the second table mapping a virtual address to a physical address and translating a physical address to a virtual address, but it does not explicitly disclose using the second table to determine the virtual address based on the physical address; Han teaches performing a read operation using a physical address, and in association with an ECC failure, using a logical to physical mapping table to determine the logical address mapped to the physical address (para. 67, 73-74, 78; figs. 7-8 and associated paragraphs)]
Gim and Yoon are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim and Yoon, to modify the disclosures by Gim to include disclosures by Yoon since they both teach memory access and data storage, wherein Yoon is directed towards error correction mechanism for improved reliability, availability, and serviceability of electronic device including a memory (para. 40). Therefore, it would be applying a known technique (using a physical address of an error to determine the corresponding virtual address) to a known device (memory device comprising a table indicating mapping of a virtual address to a physical address) ready for improvement to yield predictable results (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined in order to provide for comprehensive determination of addresses affected by an error). MPEP 2143
Gim, Yoon, and Han are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon and Han, to modify the disclosures by Gim in view of Yoon to include disclosures by Han since they both teach memory access and data storage, wherein Han is directed towards address management and meta data recovery (para. 2, 7). Therefore, it would be applying a known technique (determining a logical address associated with a physical address by using a logical to physical translation table) to a known device (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined) ready for improvement to yield predictable results (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined using the table mapping virtual addresses to physical addresses in order to provide for reduced overhead from maintaining separate lookup tables). MPEP 2143
Gim in view of Yoon in view of Han does not explicitly disclose, but Kato teaches:
a reuse table; and register an error virtual address including a searched error virtual block address in the reuse table. [Kato teaches an error block table for recording a block in which an ECC error has occurred, the error block table including a logical block address (para. 44; fig. 4 and associated paragraphs; see para. 35 on the logical block address being defined by the memory controller)]
Gim, Yoon, Han, and Kato are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han and Kato, to modify the disclosures by Gim in view of Yoon in view of Han to include disclosures by Kato since they both teach memory access and data storage, wherein Kato is directed towards improved management of blocks having errors (para. 3-12). Therefore, it would be applying a known technique (error block table recording an internally defined logical address associated with an error block) to a known device (memory device for determining a virtual address associated with a physical address having an error) ready for improvement to yield predictable results (memory device for determining a virtual address associated with a physical address having an error and storing the virtual address in an error block table for greater efficiency in referencing addresses associated with errors). MPEP 2143
Gim in view of Yoon in view of Han in view of Kato does not explicitly disclose, but Yudanov discloses:
a first physical page address [Gim in view of Yoon in view of Han in view of Kato as shown above teaches a first table comprising a logical address and a virtual address comprising a virtual block number and an offset, and a second table comprising the virtual address and a physical address comprising a physical block number and page number; it does not explicitly disclose the first table also comprising a physical page address, but Yudanov provides for tables comprising virtual to logical address and further teaches that such tables may further associate a physical address as well (para. 12), where it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Gim in view of Yoon in view of Han in view of Kato, providing for a table comprising logical and virtual address translation with the virtual address being separately translated to a physical address, and disclosures by Yudanov, providing for tables having virtual to logical addressing further being associated with a physical address, to provide for a combination where the first table having logical and virtual address translation may further be updated to include the corresponding physical address in order to provide for greater flexibility in referencing translation information, where the physical address comprising physical block number and physical page number may correspond to a physical page address; where Gim in view of Yoon in view of Han in view of Kato as shown previously teaches accessing the second table for determining a virtual address based on a physical address (see above; Han: para. 67, 73-74, 78), although the additional combination with Yudanov may result in two tables having virtual and physical addresses, it would further have been obvious for one of ordinary skill in the arts, in the event of having multiple tables with virtual-physical translations, to reference less than all the tables (i.e. one) in finding a virtual address based on a physical address to provide for faster translation latency.]
Gim, Yoon, Han, Kato, and Yudanov are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han in view of Kato and Yudanov, to modify the disclosures by Gim in view of Yoon in view of Han in view of Kato to include disclosures by Yudanov since they both teach memory access and data storage, wherein Yudanov is directed towards shared addressing and contexts (para. 1, 14). Therefore, it would be applying a known technique (tables configured to map virtual and logical addresses and further associable with physical addresses) to a known device (memory device performing logical to virtual to physical address translation and maintaining a logical to virtual addressing table) ready for improvement to yield predictable results (memory device performing logical to virtual to physical address translation and maintaining a logical to virtual addressing table, the logical to virtual addressing table configurable to also maintain corresponding physical address as well in order to provide for greater flexibility in referencing translation information). MPEP 2143
As per claim 9, Gim in view of Yoon in view of Han in view of Kato in view of Yudanov teaches claim 8 as shown above and further teaches:
9. The memory controller of claim 8, wherein when the first virtual address is registered in the reuse table, the reuse circuit is configured to allocate the first virtual address to the first logical address, map the first virtual address and the first logical address, and store a mapping result in the reuse table. [Gim in view of Yoon in view of Han in view of Kato in view of Yudanov as shown above teaches, in writing data, mapping a logical address to a virtual address and physical address in a first table, the virtual address further being stored in a second table with the physical address (see claim 8 above; Gim: para. 60-63; Yudanov: para. 12); in storing a virtual address to the error block table, responsive to an error associated with accessing a physical address, a table, such as the second table, may be referenced to determining the corresponding virtual address (see claim 8 above; Gim: para. 60-63; Yoon: para. 36-38; Han: para. 67, 73-74, 78; Kato: para. 44)]
Gim and Yoon are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim and Yoon, to modify the disclosures by Gim to include disclosures by Yoon since they both teach memory access and data storage, wherein Yoon is directed towards error correction mechanism for improved reliability, availability, and serviceability of electronic device including a memory (para. 40). Therefore, it would be applying a known technique (using a physical address of an error to determine the corresponding virtual address) to a known device (memory device comprising a table indicating mapping of a virtual address to a physical address) ready for improvement to yield predictable results (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined in order to provide for comprehensive determination of addresses affected by an error). MPEP 2143
Gim, Yoon, and Han are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon and Han, to modify the disclosures by Gim in view of Yoon to include disclosures by Han since they both teach memory access and data storage, wherein Han is directed towards address management and meta data recovery (para. 2, 7). Therefore, it would be applying a known technique (determining a logical address associated with a physical address by using a logical-to-physical translation table) to a known device (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined) ready for improvement to yield predictable results (memory device having a table mapping virtual addresses to physical addresses, where, responsive to a determination of an error associated with a physical address, the corresponding virtual address may be determined using the table mapping virtual addresses to physical addresses in order to provide for reduced overhead from maintaining separate lookup tables). MPEP 2143
Gim, Yoon, Han, and Kato are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han and Kato, to modify the disclosures by Gim in view of Yoon in view of Han to include disclosures by Kato since they both teach memory access and data storage, wherein Kato is directed towards improved management of blocks having errors (para. 3-12). Therefore, it would be applying a known technique (error block table recording an internally defined logical address associated with an error block) to a known device (memory device for determining a virtual address associated with a physical address having an error) ready for improvement to yield predictable results (memory device for determining a virtual address associated with a physical address having an error and storing the virtual address in an error block table for greater efficiency in referencing addresses associated with errors). MPEP 2143
Claim 15 is rejected for reasons similar to claim 2.
Claim 16 is rejected for reasons similar to claim 3.
Claims 6-7 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gim et al. (US 20220012181 A1) in view of Yoon et al. (US 20160062821 A1) in view of Han et al. (US 20220326873 A1) in view of Kato et al. (US 20130219244 A1) in view of Rangan et al. (US 20210349639 A1).
As per claim 6, Gim in view of Yoon in view of Han in view of Kato teaches claim 1 as shown above and further teaches:
6. The data storage apparatus of claim 1, wherein when the virtual address is registered in the reuse table, the address mapping manager is configured to activate a reuse flag. [Gim in view of Yoon in view of Han in view of Kato teaches an error block table comprising virtual and physical addresses entered therein (see claim 1 above; Kato: para. 44); it does not explicitly disclose, but Rangan teaches a table comprising a flag for each entry, the flag indicating valid (being set) or invalid (being inactivated) to indicate whether an entry is empty or not (invalid being empty) (para. 54)]
Gim, Yoon, Han, Kato, and Rangan are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han in view of Kato and Rangan, to modify the disclosures by Gim in view of Yoon in view of Han in view of Kato to include disclosures by Rangan since they both teach memory access and data storage, wherein Rangan is directed towards more efficient memory access (abstract, para. 2-4). Therefore, it would be applying a known technique (flag used to indicate whether an entry of a table is valid or invalid (empty)) to a known device (memory device having an error block table for storing virtual addresses and physical addresses) ready for improvement to yield predictable results (memory device having an error block table for storing virtual addresses and physical addresses, where a flag may be used to indicate whether an entry is empty or contains virtual and physical addresses in order to provide for more efficient referencing of the error block table). MPEP 2143
As per claim 7, Gim in view of Yoon in view of Han in view of Kato in view of Rangan teaches claim 6 as shown above and further teaches:
7. The data storage apparatus of claim 6, wherein when all virtual addresses registered in the reuse table are deleted, the address mapping manager is configured to inactivate the reuse flag. [Gim in view of Yoon in view of Han in view of Kato in view of Rangan as shown above teaches an error block table comprising virtual and physical addresses entered therein (see claim 1, 6 above; Kato: para. 44) and a flag for each entry, the flag indicating valid (being set) or invalid (being inactivated) to indicate whether an entry is empty or not (invalid being empty) (Rangan: para. 54), where, when all the entries in the table are deleted, each of the flags would necessarily indicate invalid.]
Gim, Yoon, Han, Kato, and Rangan are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han in view of Kato and Rangan, to modify the disclosures by Gim in view of Yoon in view of Han in view of Kato to include disclosures by Rangan since they both teach memory access and data storage, wherein Rangan is directed towards more efficient memory access (abstract, para. 2-4). Therefore, it would be applying a known technique (flag used to indicate whether an entry of a table is valid or invalid (empty)) to a known device (memory device having an error block table for storing virtual addresses and physical addresses) ready for improvement to yield predictable results (memory device having an error block table for storing virtual addresses and physical addresses, where a flag may be used to indicate whether an entry is empty or contains virtual and physical addresses in order to provide for more efficient referencing of the error block table). MPEP 2143
Claim 19 is rejected for reasons similar to claim 6.
Claim 20 is rejected for reasons similar to claim 7.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Gim et al. (US 20220012181 A1) in view of Yoon et al. (US 20160062821 A1) in view of Han et al. (US 20220326873 A1) in view of Kato et al. (US 20130219244 A1) in view of Yudanov (US 20210294746 A1) in view of Rangan et al. (US 20210349639 A1).
As per claim 12, Gim in view of Yoon in view of Han in view of Kato in view of Yudanov teaches claim 8 as shown above and further teaches:
12. The memory controller of claim 8, wherein when the virtual address is registered in the reuse table, the reuse circuit is configured to activate a reuse flag. [Gim in view of Yoon in view of Han in view of Kato in view of Yudanov teaches an error block table comprising virtual and physical addresses entered therein (see claim 8 above; Kato: para. 44); it does not explicitly disclose, but Rangan teaches a table comprising a flag for each entry, the flag indicating valid (being set) or invalid (being inactivated) to indicate whether an entry is empty or not (invalid being empty) (para. 54)]
Gim, Yoon, Han, Kato, Yudanov, and Rangan are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han in view of Kato in view of Yudanov and Rangan, to modify the disclosures by Gim in view of Yoon in view of Han in view of Kato in view of Yudanov to include disclosures by Rangan since they both teach memory access and data storage, wherein Rangan is directed towards more efficient memory access (abstract, para. 2-4). Therefore, it would be applying a known technique (flag used to indicate whether an entry of a table is valid or invalid (empty)) to a known device (memory device having an error block table for storing virtual addresses and physical addresses) ready for improvement to yield predictable results (memory device having an error block table for storing virtual addresses and physical addresses, where a flag may be used to indicate whether an entry is empty or contains virtual and physical addresses in order to provide for more efficient referencing of the error block table). MPEP 2143
As per claim 13, Gim in view of Yoon in view of Han in view of Kato in view of Yudanov in view of Rangan teaches claim 12 as shown above and further teaches:
13. The memory controller of claim 12, wherein when all virtual addresses registered in the reuse table are deleted, the reuse circuit is configured to inactivate the reuse flag.
[Gim in view of Yoon in view of Han in view of Kato in view of Rangan as shown above teaches an error block table comprising virtual and physical addresses entered therein (see claim 8, 12 above; Kato: para. 44) and a flag for each entry, the flag indicating valid (being set) or invalid (being inactivated) to indicate whether an entry is empty or not (invalid being empty) (Rangan: para. 54), where, when all the entries in the table are deleted, each of the flags would necessarily indicate invalid.]
Gim, Yoon, Han, Kato, Yudanov, and Rangan are analogous to the claimed invention because they are in the same field of endeavor involving memory access and data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Gim in view of Yoon in view of Han in view of Kato in view of Yudanov and Rangan, to modify the disclosures by Gim in view of Yoon in view of Han in view of Kato in view of Yudanov to include disclosures by Rangan since they both teach memory access and data storage, wherein Rangan is directed towards more efficient memory access (abstract, para. 2-4). Therefore, it would be applying a known technique (flag used to indicate whether an entry of a table is valid or invalid (empty)) to a known device (memory device having an error block table for storing virtual addresses and physical addresses) ready for improvement to yield predictable results (memory device having an error block table for storing virtual addresses and physical addresses, where a flag may be used to indicate whether an entry is empty or contains virtual and physical addresses in order to provide for more efficient referencing of the error block table). MPEP 2143
Allowable Subject Matter
Claim 4-5, 10-11, and 17-18 are objected to as being dependent upon a rejected base claim. Claims 4-5 and 10-11 would be allowable if claims 4 and 10 were rewritten in independent form including all of the limitations of the base claim. Claims 17-18, in addition to the independent claim 14, recite temporal conditional precedent that may never be reached within the scope of the claim under the broadest reasonable interpretation, as indicated in Claim Language section above. For example, claim 17 recites ‘when a second virtual address corresponding to a second logical address of data to be read from the memory device is registered in the reuse table…’ as a condition for executing the rest of the limitations therein. Claim 18 similarly recites ‘when the third logical address coincides with the second logical address’ as a condition for executing the rest the claim. The limitations of claims 17-18 are therefore not positively recited in the claims, as the limitations, as claimed, are conditionally executed without accounting for the possibility of the condition failing to occur. However, if claims 14 and 17 were rewritten as suggested in the Claim Language section above and further rewritten to in an independent form including all of the limitations of claim 14 and 17, the claims would be allowable.
With respect to claim 4, “… wherein when a second virtual address corresponding to a second logical address of data to be read from the memory device is registered in the reuse table, the address mapping manager is configured to: read a third logical address mapped to the second virtual address from the reuse table, access the logical-virtual address table to release allocation of a virtual address allocated to the second logical address when the third logical address does not coincide with the second logical address, and delete the second virtual address and information related thereto from the reuse table.” in conjunction with the other limitations of the claim and the limitations of the base claim, are not disclosed by the prior art of record.
Gim et al. (US 20220012181 A1), Yoon et al. (US 20160062821 A1), Han et al. (US 20220326873 A1), Kato et al. (US 20130219244 A1), Baron (US 20120265920 A1), Byun (US 11263148 B2), Kang (US 12204445 B2), Guo et al (US 20170046073 A1), and Kim et al. (US 20240241646 A1).
Gim teaches mapping logical address into virtual and physical address, and an open block table used in determining mapping errors. Yoon teaches reverse mapping a physical address into a virtual address. Han teaches using a logical to physical table for translating a physical address into a logical address. Kato teaches maintaining an error block table. Byun teaches selecting a target address corresponding to a target logical address from a host from an extended candidate address table. Kang teaches generating virtual domains including respective page mapping table and block mapping table. Guo teaches remapping operation for mapping logical addresses in planes for a source band at an end on a die, that map to bad blocks, to different source bands on the same die so that the logical addresses in the band at the end are remapped to different bands on a different end. Kim teaches a bad block manager and a remapping engine configured to remap a first unrepairable address to a first physical address of a reserved region in response to a first host physical address from the at least one host matching the first unrepairable address in the unrepairable address information.
However, the prior arts of record, neither individually nor in combination, teaches, in association with system configured to store a virtual address associated with an errant physical page in a reuse table by searching a virtual-to-physical table without accessing a logical-to-virtual table, responsive to a second virtual address corresponding to a second logical address of data to be read from a memory device being registered in a reuse table, reading a third logical address mapped to the second virtual address from the reuse table, accessing the logical-to-virtual address table to release allocation of a virtual address as allocated to the second logical address when the third logical address does not coincide with the second logical address, and deleting the second virtual address and information related to the second virtual address from the reuse table.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the limitations of the base claim, the claim as a whole.
With respect to claim 10, “… wherein when a second virtual address corresponding to a second logical address of data to be read from the memory device is registered in the reuse table, the reuse circuit is configured to: read a third logical address mapped to the second virtual address from the reuse table, access the logical-virtual address table to release allocation of a virtual address allocated to the second logical address when the third logical address does not coincide with the second logical address, and delete the second virtual address and information related thereto from the reuse table.” in conjunction with the other limitations of the claim and the limitations of the base claim, are not disclosed by the prior art of record.
Gim et al. (US 20220012181 A1), Yoon et al. (US 20160062821 A1), Han et al. (US 20220326873 A1), Kato et al. (US 20130219244 A1), Baron (US 20120265920 A1), Byun (US 11263148 B2), Kang (US 12204445 B2), Guo et al (US 20170046073 A1), and Kim et al. (US 20240241646 A1).
Gim teaches mapping logical address into virtual and physical address, and an open block table used in determining mapping errors. Yoon teaches reverse mapping a physical address into a virtual address. Han teaches using a logical to physical table for translating a physical address into a logical address. Kato teaches maintaining an error block table. Byun teaches selecting a target address corresponding to a target logical address from a host from an extended candidate address table. Kang teaches generating virtual domains including respective page mapping table and block mapping table. Guo teaches remapping operation for mapping logical addresses in planes for a source band at an end on a die, that map to bad blocks, to different source bands on the same die so that the logical addresses in the band at the end are remapped to different bands on a different end. Kim teaches a bad block manager and a remapping engine configured to remap a first unrepairable address to a first physical address of a reserved region in response to a first host physical address from the at least one host matching the first unrepairable address in the unrepairable address information.
However, the prior arts of record, neither individually nor in combination, teaches, in association with system configured to store a virtual address associated with an errant physical block in a reuse table by searching a virtual-to-physical table without accessing a logical-to-virtual table, responsive to a second virtual address corresponding to a second logical address of data to be read from a memory device being registered in a reuse table, reading a third logical address mapped to the second virtual address from the reuse table, accessing the logical-to-virtual address table to release allocation of a virtual address as allocated to the second logical address when the third logical address does not coincide with the second logical address, and deleting the second virtual address and information related to the second virtual address from the reuse table.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the limitations of the base claim, the claim as a whole.
With respect to claim 17, “… when a second virtual address corresponding to a second logical address of data to be read from the memory device is registered in the reuse table,the memory controller reading a third logical address mapped to the second virtual address from the reuse table; the memory controller accessing the logical-virtual address table to release allocation of a virtual address allocated to the second logical address when the third logical address does not coincide with the second logical address; and the memory controller deleting the second virtual address and information related thereto from the reuse table.” in conjunction with the other limitations of the claim and the limitations of the base claim as interpreted by the examiner, are not disclosed by the prior art of record.
Gim et al. (US 20220012181 A1), Yoon et al. (US 20160062821 A1), Han et al. (US 20220326873 A1), Kato et al. (US 20130219244 A1), Baron (US 20120265920 A1), Byun (US 11263148 B2), Kang (US 12204445 B2), Guo et al (US 20170046073 A1), and Kim et al. (US 20240241646 A1).
Gim teaches mapping logical address into virtual and physical address, and an open block table used in determining mapping errors. Yoon teaches reverse mapping a physical address into a virtual address. Han teaches using a logical to physical table for translating a physical address into a logical address. Kato teaches maintaining an error block table. Byun teaches selecting a target address corresponding to a target logical address from a host from an extended candidate address table. Kang teaches generating virtual domains including respective page mapping table and block mapping table. Guo teaches remapping operation for mapping logical addresses in planes for a source band at an end on a die, that map to bad blocks, to different source bands on the same die so that the logical addresses in the band at the end are remapped to different bands on a different end. Kim teaches a bad block manager and a remapping engine configured to remap a first unrepairable address to a first physical address of a reserved region in response to a first host physical address from the at least one host matching the first unrepairable address in the unrepairable address information.
However, the prior arts of record, neither individually nor in combination, teaches, in association with system configured to store a virtual address associated with an errant physical block in a reuse table by searching a virtual-to-physical table without accessing a logical-to-virtual table, responsive to a second virtual address corresponding to a second logical address of data to be read from a memory device being registered in a reuse table, reading a third logical address mapped to the second virtual address from the reuse table, accessing the logical-to-virtual address table to release allocation of a virtual address as allocated to the second logical address when the third logical address does not coincide with the second logical address, and deleting the second virtual address and information related to the second virtual address from the reuse table.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the limitations of the base claim as interpreted by the examiner, the claim as a whole.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Quach et al. (US 20040221189 A1) teaches, responsive to detecting an error, using a physical address associated with the error for looking up, in a mapping table having virtual to physical translations, an associated virtual address (para. 18, 21, 25).
Conclusion
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/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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