DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
The term “close” in claim 2 is a relative term which renders the claim indefinite. The term “close” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
The term “close” is purely subjective.
Claim 19 recites the limitation “the electronic element.” There is insufficient antecedent basis for this limitation in the claim.
The claim contains no earlier recitation or limitation of an “electronic element.”
Any remaining claim(s) is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being dependent upon one or more rejected base claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-5, 10-12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al (US 2025/0081609 A1) in view of Ban et al (US 2023/0206874 A1).
Regarding claim 1, Xiao discloses an electronic device, comprising:
a substrate [e.g., Fig. 1: 100];
a gate driving line [e.g., Figs. 2-3: S1 for leftmost P3; Fig. 12B: leftmost DataT], disposed on the substrate;
a first switching element [e.g., Figs. 2-3: T3 for P2; Fig. 4: DTFT2], disposed on the substrate and having a first gate drain capacitance [e.g., Paragraph 365: 1st gate-drain capacitance Cgd for Figs. 2-4: T3/DTFT2 for P2];
a second switching element [e.g., Figs. 2-3: T3 for P1; Fig. 4: DTFT1], disposed on the substrate and having a second gate drain capacitance [e.g., Paragraph 365: 2nd gate-drain capacitance Cgd for for Figs. 2-4: T3/DTFT1 for P1],
wherein in a first direction [e.g., Fig. 4: right to left X direction], a distance [e.g., a short distance between Figs. 2-4: T3/DTFT2 for P2 and S1/DataT for leftmost P3] between the gate driving line and the first switching element is less than a distance [e.g., a longer distance between Figs. 2-4: T3/DTFT1 for P1 and S1/DataT for leftmost P3] between the gate driving line and the second switching element, and
the first gate drain capacitance is less than the second gate drain capacitance [e.g., Paragraph 365: gate-drain capacitance Cgd of the third/driving transistor will increase with the increase of the width-length ratio;
Paragraph 141: the width-length ratio (W/L) of the first drive transistor DTFT1 is greater than the width-length ratio of the second drive transistor DTFT2]; and
a plurality of electronic elements [e.g., Figs. 2-3: EL for P2, EL for P1], arranged in the first direction,
wherein one of the plurality of electronic elements [e.g., Figs. 2-3: EL for P2] is electrically connected to the first switching element and comprises at least one of a variable capacitor, a light emitting diode [e.g., Paragraph 119: light emitting diode EL] or a solar cell, and
another one of the plurality of electronic elements [e.g., Figs. 2-3: EL for P1] is electrically connected to the second switching element and comprises at least one of a variable capacitor, a light emitting diode [e.g., Paragraph 119: light emitting diode EL] or a solar cell (e.g., see Paragraphs 88-365).
Although Xiao discloses a gate driving line, Xiao doesn’t appear to expressly disclose a gate driving element, as instantly claimed.
However, Ban discloses a gate driving element [e.g., Fig. 1: 200b], disposed on the substrate [e.g., Paragraph 45: main substrate] (e.g., see Paragraphs 35-67).
Xiao and Ban are analogous art, because they are from the shared inventive field of display driving devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine Ban’s gate driving element with Xiao’s gate driving line, so as to accurately provide display images.
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Ban’s gate driving element with Xiao’s gate driving line as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Regarding claim 2, Xiao discloses a width [e.g., Fig. 5A: W1] of a boundary where a gate that is close to a drain overlaps with a semiconductor layer [e.g., Fig. 8B: AT3] in the second switching element is greater than a width [e.g., Fig. 5B: W2] of a boundary where a gate that is close to a drain overlaps a semiconductor layer [e.g., Fig. 8B: AT3] in the first switching element (e.g., see Paragraphs 147-189).
Regarding claim 4, Xiao discloses a fourth switching element [e.g., Figs. 2-3: T3 for P3; Fig. 4: DTFT3], disposed on the substrate and having a fourth gate drain capacitance [e.g., Paragraph 365: 4th gate-drain capacitance Cgd for Figs. 2-4: T3/DTFT3 for P3],
wherein the fourth switching element and the first switching element are arranged in a second direction [e.g., Figs. 2, 4: vertical, Y direction], and the fourth gate drain capacitance and the first gate drain capacitance are different [e.g., Paragraph 365: gate-drain capacitance Cgd of the third/driving transistor will increase with the increase of the width-length ratio;
Paragraph 141: the width-length ratio (W/L) of the first drive transistor DTFT1 may be greater than the width-length ratio of the second drive transistor DTFT3].
Regarding claim 5, Xiao discloses an area [e.g., Fig. 5B: overlapping area of W2, L2] where a gate [e.g., Fig. 5B: gate] of the first switching element overlaps with a drain [e.g., Fig. 5B: drain] of the first switching element and an area [e.g., Fig. 5A: area of W1, L1] where a gate [e.g., Fig. 5A: gate] of the second switching element overlaps with a drain [e.g., Fig. 5A: drain] of the second switching element are different (e.g., see Paragraphs 146-151).
Regarding claim 10, Xiao discloses a gate [e.g., Fig. 5B: gate] of the first switching element comprises a first overlapping part [e.g., Fig. 5B: part of overlapping area W2, L2] that overlaps with a drain [e.g., Fig. 5B: drain],
a gate [e.g., Fig. 5A: gate] of the second switching element comprises a second overlapping part [e.g., Fig. 5B: part of overlapping area W1, L1] that overlaps with a drain [e.g., Fig. 5A: drain], and
an area of the first overlapping part is less than an area of the second overlapping part (e.g., see Paragraphs 146-151).
Regarding claim 11, Xiao discloses a drain [e.g., Fig. 5B: drain] of the first switching element comprises a third overlapping part [e.g., Fig. 5B: part of overlapping area W2, L2] that overlaps with a gate [e.g., Fig. 5B: gate],
a drain [e.g., Fig. 5A: drain] of the second switching element comprises a fourth overlapping part [e.g., Fig. 5B: part of overlapping area W1, L1] that overlaps with a gate [e.g., Fig. 5A: gate], and
an area of the third overlapping part is less than an area of the fourth overlapping part (e.g., see Paragraphs 146-151).
Regarding claim 12, Xiao discloses a semiconductor layer [e.g., Fig. 8B: AT3] of the first switching element comprises a plurality of fifth overlapping parts [e.g., Fig. 8B: overlapping parts of AT3] that overlap with a gate [e.g., Fig. 5B: gate], and a semiconductor layer [e.g., Fig. 8B: AT3] of the second switching element comprises a plurality of sixth overlapping parts [e.g., Fig. 8B: overlapping parts of AT3] that overlap with a gate [e.g., Fig. 5A: gate] (e.g., see Paragraphs 146-189).
Regarding claim 16, Xiao discloses a first storage capacitor [e.g., Figs. 2-3: Cs for P1; Fig. 4: Cs1] and a second storage capacitor [e.g., Figs. 2-3: Cs for P2; Fig. 4: Cs2],
wherein the first switching element is electrically connected [e.g., via Fig. 2: VDD] to the first storage capacitor,
the second switching element is electrically connected [e.g., via Fig. 2: VDD] to the second storage capacitor, and
the first storage capacitor is greater than the second storage capacitor (e.g., see Paragraph 308-371).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al (US 2025/0081609 A1) in view of Ban et al (US 2023/0206874 A1) as applied to claim 1 above, and further in view of Hao et al (US 2023/0138001 A1).
Regarding claim 3, Xiao and Ban don’t appear to expressly disclose a third switching element having a third gate drain capacitance, as instantly claimed.
However, Hao discloses a third switching element [e.g., Fig. 2: Td for PX1011], disposed on the substrate and having a third gate drain capacitance [e.g., Fig. 3A: capacitance/width-to-length ratio of the second channel CNL1],
wherein the distance between the gate driving element [e.g., Fig. 2: leftmost DL] and the second switching element [e.g., Fig. 2: Td for PX1012] is less than a distance between the gate driving element and the third switching element, and
the second gate drain capacitance [e.g., Paragraph 64, Fig. 3A: capacitance/width-to-length ratio of the second channel CNL2 is less than capacitance/width-to-length ratio of the second channel CNL1] is less than the third gate drain capacitance (e.g., see Paragraphs 42-114).
Xiao, Ban and Hao are analogous art, because they are from the shared inventive field of display driving devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine Hao’s third switching element with Xiao’s and Ban’s device, so as to prevent poor display uniformity and short display lifespan.
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Hao’s third switching element with Xiao’s and Ban’s device as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al (US 2025/0081609 A1) in view of Ban et al (US 2023/0206874 A1) as applied to claim 1 above, and further in view of Liu et al (US 2024/0186454 A1).
Regarding claim 19, Xiao and Ban don’t appear to expressly disclose a conductive layer, as instantly claimed.
However, Liu discloses a conductive layer [e.g., Fig. 5A: 172], wherein the conductive layer is disposed between the electronic element [e.g., Fig. 5A: 130-132] and the substrate [e.g., Fig. 5A: 173] (e.g., see Paragraphs 61-89).
Xiao, Ban and Liu are analogous art, because they are from the shared inventive field of display driving devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine Liu’s conductive layer with Xiao’s and Ban’s device, so as to reduce the operating temperatures.
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Liu’s conductive layer with Xiao’s and Ban’s device as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Regarding claim 20, Liu discloses the conductive layer is a heat dissipation layer [e.g., Fig. 5A: 172], an electrostatic protection layer, an electromagnetic interference shielding layer or a combination thereof (e.g., see Paragraphs 83-85).
Election/Restrictions
Applicant’s election without traverse of Species 5, 13, 21, 29, 33, 37 and 44 in the reply filed on 26 December 2025 is acknowledged.
Claims 6-9, 13-15, 17 and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to at least a nonelected species/invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 26 December 2025.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The documents listed on the attached 'Notice of References Cited' are cited to further evidence the state of the art pertaining to electronic devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached on Monday - Friday (7:30AM - 4PM). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
9 January 2026