DETAILED ACTION
This Office Action is in response to Applicant’s Application filed on March 6, 2025. Claims 1-24 are pending and presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 6, 2025 has been considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: the status of the related application 18/389,995 in paragraph 0002 needs to be updated.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-24 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-26 of U.S. Patent No. 12,711,035. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in U.S. Pat. No. 12,711,035 and would be covered by any patent granted since the U.S. Pat. No. 12,711,035 and the instant application are claiming common subject matter.
Instant Application 19/072,114
1. A processor-implemented method for malicious code detection comprising: accessing a system-on-a-chip (SoC), wherein the SoC includes one or more processor cores, wherein each processor core within the one or more processor cores is coupled to one or more external profiling agents (EPAs) on the SoC; configuring, by an EPA within the one or more EPAs, a performance counter in a processor core within the one or more processor cores, wherein the configuring is based on an offset value; updating, by the processor core, the performance counter that was configured, wherein the updating is based on a processor core event; saving a program state to a performance counter storage area, wherein the saving is based on a performance counter event, wherein the program state that is saved corresponds to code being executed on the processor core; reading the program state, from the performance counter storage area, by the EPA; and interpreting, by the EPA, the program state that was read, wherein the interpreting identifies a malicious program running on the processor core.
2. The method of claim 1 wherein the performance counter comprises an activity counter.
3. The method of claim 2 wherein the activity counter identifies load changes within the processor core.
4. The method of claim 3 wherein the activity counter is used to detect malicious activity.
5. The method of claim 1 wherein the processor core event comprises a page fault.
6. The method of claim 1 further comprising resetting, by the EPA, the performance counter.
7. The method of claim 6 wherein the configuring, the updating, the saving, and the resetting are periodically repeated.
8. The method of claim 7 further comprising generating a code profile, based on the updating, the saving, the reading, and the resetting.
9. The method of claim 8 wherein the interpreting comprises comparing the code profile to a known profile of code being executed on the processor core.
10. The method of claim 9 wherein the comparing includes machine learning.
11. The method of claim 8 wherein the interpreting comprises comparing the code profile to a known profile of one or more malicious programs.
12. The method of claim 1 wherein the updating comprises incrementing, by the processor core, the performance counter, wherein the performance counter event is an overflow, and wherein the offset value comprises a distance from a performance counter overflow value.
13. The method of claim 1 wherein the updating comprises decrementing, by the processor core, the performance counter, wherein the performance counter event is an underflow, and wherein the offset value comprises a distance from a performance counter underflow value.
14. The method of claim 1 wherein the interpreting is based on machine learning.
15. The method of claim 1 wherein the program state includes execution identification values.
16. The method of claim 15 wherein the execution identification values include an address space identifier (ASID).
17. The method of claim 15 wherein the execution identification values include a virtual machine identifier (VMID).
18. The method of claim 1 wherein the configuring includes a performance counter control register.
19. The method of claim 18 wherein the performance counter control register includes settings for the processor core event, whether profiling is enabled, and what a sampling period comprises.
20. The method of claim 1 further comprising creating a known code profile.
21. The method of claim 20 wherein the known code profile is based on non-malicious code.
22. The method of claim 20 wherein the known code profile is based on malicious code.
23. A computer program product embodied in a non-transitory computer readable medium for malicious code detection, the computer program product comprising code which causes one or more processors to generate semiconductor logic for: accessing a system-on-a-chip (SoC), wherein the SoC includes one or more processor cores, wherein each processor core within the one or more processor cores is coupled to one or more external profiling agents (EPAs) on the SoC; configuring, by an EPA within the one or more EPAs, a performance counter in a processor core within the one or more processor cores, wherein the configuring is based on an offset value; updating, by the processor core, the performance counter that was configured, wherein the updating is based on a processor core event; saving a program state to a performance counter storage area, wherein the saving is based on a performance counter event, wherein the program state that is saved corresponds to code being executed on the processor core; reading the program state, from the performance counter storage area, by the EPA; and interpreting, by the EPA, the program state that was read, wherein the interpreting identifies a malicious program running on the processor core.
24. A computer system for malicious code detection comprising: a memory which stores instructions; one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to: access a system-on-a-chip (SoC), wherein the SoC includes one or more processor cores, wherein each processor core within the one or more processor cores is coupled to one or more external profiling agents (EPAs) on the SoC; configure, by an EPA within the one or more EPAs, a performance counter in a processor core within the one or more processor cores, wherein the configuring is based on an offset value; update, by the processor core, the performance counter that was configured, wherein the updating is based on a processor core event; save a program state to a performance counter storage area, wherein the saving is based on a performance counter event, wherein the program state that is saved corresponds to code being executed on the processor core; read the program state, from the performance counter storage area, by the EPA; and interpret, by the EPA, the program state that was read, wherein the interpreting identifies a malicious program running on the processor core.
U.S. Pat. No. 12,711,035
1. A processor-implemented method for performance profiling comprising: accessing a processor core, wherein the processor core includes a performance counter, a performance counter storage area, and a performance counter control register, and wherein the processor core includes a performance monitoring interface; assigning the performance counter, the performance counter storage area, and the performance counter control register to an external profiling agent; loading the performance counter and the performance counter control register by the external profiling agent; saving a program state to the storage area, based on a counter event in the performance counter and an enable bit in the performance counter control register being set, wherein the program state that is saved corresponds to code being executed on the processor core; and reading the program state, from the storage area, by the external profiling agent.
2. The method of claim 1 wherein the loading by the external profiling agent is based on a particular event in the processor core.
3. The method of claim 2 wherein the particular event includes particular code running on the processor core.
4. The method of claim 2 wherein the particular event includes human direction.
5. The method of claim 2 wherein the external profiling agent loads the performance counter and the performance counter control register, based on the particular event.
6. The method of claim 1 wherein the counter event includes incrementing the performance counter by a value N.
7. The method of claim 6 wherein the performance counter is incremented to a value M.
8. The method of claim 1 wherein the counter event includes decrementing the performance counter by a value N.
9. The method of claim 8 wherein the performance counter is decremented to a value M.
10. The method of claim 1 wherein the saving a program state is periodically repeated, based on the external profiling agent.
11. The method of claim 10 further comprising generating a performance profile, based on the saving of repeated program states.
12. The method of claim 11 wherein the performance profile is generated by the external profiling agent.
13. The method of claim 12 further comprising augmenting the performance profile using context information from the processor core.
14. The method of claim 12 further comprising delivering the performance profile to a system administrator or system users.
15. The method of claim 12 further comprising delivering the performance profile to a networked storage area.
16. The method of claim 11 wherein the saving of repeated program states occurs on a regular basis.
17. The method of claim 16 wherein the regular basis is every 100 ms.
18. The method of claim 16 further comprising freeing the storage area for additional program states, based on completion of the saving.
19. The method of claim 11 wherein the performance profile enables malicious code execution detection.
20. The method of claim 19 wherein the malicious code execution detection includes performance anomaly detection.
21. The method of claim 1 wherein the performance counter control register includes settings for which event the performance counter is counting, whether profiling is enabled, and what a sampling period comprises.
22. The method of claim 1 wherein the performance counter, the performance counter storage area, and the performance counter control register use logic associated with the performance counter to control the saving.
23. The method of claim 1 wherein the program state includes program execution identification values.
24. The method of claim 23 wherein the program execution identification values include an address space identifier (ASID) and/or a virtual machine identifier (VMID).
25. A computer program product embodied in a non-transitory computer readable medium for performance profiling, the computer program product comprising code which causes one or more processors to generate semiconductor logic for: accessing a processor core, wherein the processor core includes a performance counter, a performance counter storage area, and a performance counter control register, and wherein the processor core includes a performance monitoring interface; assigning the performance counter, the performance counter storage area, and the performance counter control register to an external profiling agent; loading the performance counter and the performance counter control register by the external profiling agent; saving a program state to the storage area, based on a counter event in the performance counter and an enable bit in the performance counter control register being set, wherein the program state that is saved corresponds to code being executed on the processor core; and reading the program state, from the storage area, by the external profiling agent.
26. An apparatus for performance profiling comprising: a processor core comprising a performance counter, a performance counter storage area, and a performance counter control register, wherein the processor core and the performance counter are used to perform operations comprising: accessing the processor core wherein the processor core includes a performance monitoring interface; assigning the performance counter, the performance counter storage area, and the performance counter control register to an external profiling agent; loading the performance counter and the performance counter control register by the external profiling agent; saving a program state to the storage area, based on a counter event in the performance counter and an enable bit in the performance counter control register being set, wherein the program state that is saved corresponds to code being executed on the processor core; and reading the program state, from the storage area, by the external profiling agent.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dalton et al (U.S. Pub. No. 2016/0078226) discloses detecting a security event in a computing device. The software-based security solutions run on a host processor of the computing device, the software-based security solutions are vulnerable to the same security events that can harm the host processor. They can also slow down the performance of processes already running on the host processor. The present disclosure describes a system-on-chip (SOC) or an application-specific integrated circuit (ASIC) with one or more processing cores sharing a memory space. The SOC or ASIC will also include a discrete secure core with its own memory. The secure core can inspect the shared memory space to detect and remedy security events of the processing cores. With its own dedicated memory, the secure core can monitor activities of the processing cores without being vulnerable to attacks.
Jayaraman et al (U.S. Pub. No. 2016/0294396) discloses A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LASHONDA T JACOBS-BURTON whose telephone number is (571)272-4004. The examiner can normally be reached M-F 8:30 am - 5:00 pm.
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/LASHONDA JACOBS-BURTON/Primary Examiner, Art Unit 2457
ljb
August 20, 2026
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