DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements were submitted on 04/17/2025 & 12/08/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Claim Rejections - 35 USC § 112
112(b):
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 31-40 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 31 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 31 recites “a fourth processor”. This renders the claim unclear as there is no previous limitations reciting first, second, third processor. For examination purposes, a fourth processor will be read as a first processor.
This same rejection applies to Claims 34, 36, 37, 40.
Claim 32 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 32 recites “a fifth processor”. This renders the claim unclear as there is no previous limitations reciting first, second, third processor. For examination purposes, a fifth processor will be read as a second processor.
This same rejection applies to Claims 34, 38, 40.
All dependents are also rejected as having the same deficiencies as the claims from which they depend.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-23, 28, 30-31, 35-37 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0183591 A1 (HE).
Regarding Claim 21:
HE teaches A method, applied to a computing device (Fig 3, System 200, Host 201), wherein the computing device comprises a first network interface card, (Fig 3, Forwarding and Processing Device 202, comprising network ports 2024, 2025) and the method comprises:
detecting, by the first network interface card, an access instruction, wherein the access instruction (ie. command) is for accessing a target storage in a storage device; ([0042] and Fig 1, step 100, “A host 201 generates a first packet that complies with the NVMe protocol, and sends the first packet to a forwarding and processing device 202, where the first packet includes an input/output command 100 or a management command, and the input/output command or the management command complies with the NVMe protocol and includes an identity of a target hard disk that needs to be accessed.)
performing, by the first network interface card, fault detection; ([0031]-[0038] Optionally, the processor may select, according to a preset selection policy and from the network ports that can reach the target non-volatile memory, the network port for forwarding the second packet. The selection policy includes but is not limited to an active/standby selection policy, a load sharing policy, a priority policy, and a quality of service (QoS) policy. The processor is further configured to: manage non-volatile memory discovery, link establishment, link disconnection, and the like in the target storage device, and provide an in-band or out-of-band management function interface and the like.)
determining a first network link from a plurality of network links existing between the first network interface card and the target storage, the first network link being network-fault- free; ([0031]-[0038][0048], Optionally, the processor may select, according to a preset selection policy and from the network ports that can reach the target non-volatile memory, the network port for forwarding the second packet. [0115] In FIG. 1, the host 101 and the target storage device 105 are connected by using two paths. When one of the paths fails, the host 101 and the target storage device 105 may communicate with each other by using the other path.)
and accessing, by the first network interface card, the target storage over the first network link. ([0043][0048]-[0049] generate a second packet according to the input/output command or the management command that complies with the NVMe protocol, … encapsulate the second packet into a packet that meets an NVMe over Fabric forwarding requirement; and send the encapsulated second packet by using the selected network port. [0052] The management command includes but is not limited to: reading device information of the target non-volatile memory, adding or deleting the target non-volatile memory, and the like.)
Regarding Claim 31:
HE teaches A network interface card (Fig 3, Forwarding and Processing device 202), comprising: a bus interface, configured to be connected to a computing device; (Fig 3, Forwarding and Processing device 202 comprising bus port 2022 connected to CPU 2011.)
a network interface, configured to be connected to a remote storage device via a network; and a first processor, (Fig 3, Forwarding and Processing device 202 comprising network ports 2024, 2025 connected over a network via switches to target storage 205, 206.) configured to perform:
performing fault detection when receiving an access instruction that is sent by the computing device and that is for accessing a target storage in the remote storage device, ([0042] and Fig 1, step 100, “A host 201 generates a first packet that complies with the NVMe protocol, and sends the first packet to a forwarding and processing device 202, where the first packet includes an input/output command 100 or a management command, and the input/output command or the management command complies with the NVMe protocol and includes an identity of a target hard disk that needs to be accessed. Fault detection: [0031]-[0037] Optionally, the processor may select, according to a preset selection policy and from the network ports that can reach the target non-volatile memory, the network port for forwarding the second packet. The selection policy includes but is not limited to an active/standby selection policy, a load sharing policy, a priority policy, and a quality of service (QoS) policy. [0038] Optionally, the processor is further configured to: manage non-volatile memory discovery, link establishment, link disconnection, and the like in the target storage device, and provide an in-band or out-of-band management function interface and the like.)
determining a first network link from a plurality of network links existing between the network interface card and the remote storage device, the first network link being network-fault- free, ([0031]-[0038][0048], Optionally, the processor may select, according to a preset selection policy and from the network ports that can reach the target non-volatile memory, the network port for forwarding the second packet. [0115] In FIG. 1, the host 101 and the target storage device 105 are connected by using two paths. When one of the paths fails, the host 101 and the target storage device 105 may communicate with each other by using the other path.)
and accessing the target storage over the first network link. ([0043][0048]-[0049] generate a second packet according to the input/output command or the management command that complies with the NVMe protocol, … encapsulate the second packet into a packet that meets an NVMe over Fabric forwarding requirement; and send the encapsulated second packet by using the selected network port. [0052] The management command includes but is not limited to: reading device information of the target non-volatile memory, adding or deleting the target non-volatile memory, and the like.)
Regarding Claim 36:
HE teaches An electronic device (Fig 3, System 200, Host 201), wherein the electronic device comprises a network interface card, (Fig 3, Forwarding and Processing device 202) the network interface card including: a bus interface, configured to be connected to a computing device; (Fig 3, Forwarding and Processing device 202 comprising bus port 2022 connected to CPU 2011.)
a network interface, configured to be connected to a remote storage device via a network; and a first processor, (Fig 3, Forwarding and Processing device 202 comprising network ports 2024, 2025 connected over a network via switches to target storage 205, 206.) configured to perform:
performing fault detection when receiving an instruction that is sent by the computing device and that is for accessing a target storage in the remote storage device, ([0042] and Fig 1, step 100, “A host 201 generates a first packet that complies with the NVMe protocol, and sends the first packet to a forwarding and processing device 202, where the first packet includes an input/output command 100 or a management command, and the input/output command or the management command complies with the NVMe protocol and includes an identity of a target hard disk that needs to be accessed. Fault detection: [0031]-[0038] Optionally, the processor may select, according to a preset selection policy and from the network ports that can reach the target non-volatile memory, the network port for forwarding the second packet. The selection policy includes but is not limited to an active/standby selection policy, a load sharing policy, a priority policy, and a quality of service (QoS) policy. The processor is further configured to: manage non-volatile memory discovery, link establishment, link disconnection, and the like in the target storage device, and provide an in-band or out-of-band management function interface and the like.)
determining a first network link from a plurality of network links existing between the network interface card and the remote storage device, the first network link being network-fault- free, ([0031]-[0038][0048], Optionally, the processor may select, according to a preset selection policy and from the network ports that can reach the target non-volatile memory, the network port for forwarding the second packet. [0115] In FIG. 1, the host 101 and the target storage device 105 are connected by using two paths. When one of the paths fails, the host 101 and the target storage device 105 may communicate with each other by using the other path.)
and accessing the target storage over the first network link. ([0043][0048]-[0049] generate a second packet according to the input/output command or the management command that complies with the NVMe protocol, … encapsulate the second packet into a packet that meets an NVMe over Fabric forwarding requirement; and send the encapsulated second packet by using the selected network port. [0052] The management command includes but is not limited to: reading device information of the target non-volatile memory, adding or deleting the target non-volatile memory, and the like.)
Regarding Claim 37:
HE teaches An electronic device, (Fig 3, System 200, Host 201) comprising:
a computing device, configured to send an access instruction for accessing a target storage in a remote storage device; ([0042] and Fig 1, step 100, “A host 201 generates a first packet that complies with the NVMe protocol, and sends the first packet to a forwarding and processing device 202, where the first packet includes an input/output command 100 or a management command, and the input/output command or the management command complies with the NVMe protocol and includes an identity of a target hard disk that needs to be accessed.)
a network interface card, comprising: a bus interface, configured to be connected to the computing device; (Fig 3, Forwarding and Processing device 202 comprising bus port 2022 connected to CPU 2011.)
a network interface, configured to be connected to the remote storage device via a network; and a first processor, (Fig 3, Forwarding and Processing device 202 comprising network ports 2024, 2025 connected over a network via switches to target storage 205, 206.) configured to perform:
performing fault detection when receiving the access instruction, [0031]-[0038] Optionally, the processor may select, according to a preset selection policy and from the network ports that can reach the target non-volatile memory, the network port for forwarding the second packet. The selection policy includes but is not limited to an active/standby selection policy, a load sharing policy, a priority policy, and a quality of service (QoS) policy. The processor is further configured to: manage non-volatile memory discovery, link establishment, link disconnection, and the like in the target storage device, and provide an in-band or out-of-band management function interface and the like.)
determining a first network link from a plurality of network links existing between the network interface card and the remote storage device, the first network link being network-fault- free, ([0031]-[0038][0048], Optionally, the processor may select, according to a preset selection policy and from the network ports that can reach the target non-volatile memory, the network port for forwarding the second packet. [0115] In FIG. 1, the host 101 and the target storage device 105 are connected by using two paths. When one of the paths fails, the host 101 and the target storage device 105 may communicate with each other by using the other path.)
and accessing the target storage over the first network link. ([0043][0048]-[0049] generate a second packet according to the input/output command or the management command that complies with the NVMe protocol, … encapsulate the second packet into a packet that meets an NVMe over Fabric forwarding requirement; and send the encapsulated second packet by using the selected network port. [0052] The management command includes but is not limited to: reading device information of the target non-volatile memory, adding or deleting the target non-volatile memory, and the like.)
Regarding Claim 22:
HE teaches on the invention of Claim 21 as described.
HE teaches wherein the first network interface card accesses the target storage over the first network link according to a non-volatile memory (NVMe) over fabric (NoF) protocol and a remote direct memory access (RDMA) protocol. ([0012]-[0020] encapsulate the second packet into a packet that meets an NVMe over Fabric forwarding requirement, and send the encapsulated second packet by using the selected network port. [0025] Optionally, the data that needs to be stored and that is obtained by the processor from the control device may be transmitted by means of remote direct memory access (RDMA) or direct memory access (DMA). )
Regarding Claim 23:
HE teaches on the invention of Claim 22 as described.
HE teaches wherein the first network interface card is connected to a mainboard of the computing device through a bus interface, the computing device further comprises a first processor disposed on the mainboard, and the access instruction is generated by the first processor. ([0042] and Fig 1, step 100, “A host 201 generates a first packet that complies with the NVMe protocol, and sends the first packet to a forwarding and processing device 202, where the first packet includes an input/output command 100 or a management command, and the input/output command or the management command complies with the NVMe protocol and includes an identity of a target hard disk that needs to be accessed. Fig 3, Forwarding and Processing device 202 comprising bus port 2022, processor 2021, network ports 2024, 2025 and connected to CPU 2011 (on Host 201) via bus port 2022.)
Regarding Claim 28:
HE teaches on the invention of Claim 21 as described.
HE teaches wherein the determining the first network link from the plurality of network links existing between the first network interface card and the target storage comprises: based on receiving, from the storage device, no information indicating that the first network link is faulty, determining, by the first network interface card, that the first network link that is network-fault-free between the first network interface card and the target storage exists. ([0031]-[0038][0048], The processor may select, according to a preset selection policy and from the network ports that can reach the target non-volatile memory, the network port for forwarding the second packet.)
Regarding Claims 30, 35:
HE teaches on the inventions of Claims 21, 31 as described.
HE teaches wherein the access instruction is an NVMe instruction. ([0127] After receiving the first packet, the bus port 2022 obtains the input/output command or the management command that complies with the NVMe protocol and that is included in the first packet, and sends, to a processor 2021, the obtained input/output command or the management command that complies with the NVMe protocol.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 24-26, 29, 32-34, 38-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0183591 A1 (HE) in view of US 2022/0091754 Al (Raman).
Regarding Claim 24:
HE teaches on the invention of Claim 23 as described.
HE teaches wherein the first network interface card comprises a ([0012]-[0020] encapsulate the second packet into a packet that meets an NVMe over Fabric forwarding requirement, and send the encapsulated second packet by using the selected network port. [0025] Optionally, the data that needs to be stored and that is obtained by the processor from the control device may be transmitted by means of remote direct memory access (RDMA) or direct memory access (DMA).)
HE teaches on a processor in a NIC card and a second processor on the Host 201 (Fig 3). However, HE is silent on multiple processors on the NIC card.
Raman teaches, in the same field of endeavor, on load balancing of NVMe targets based on real time metrics, Abstract.
Raman also teaches on multiple processors on the NIC card. ([0055] FIG. 4 is a high-level diagram of a network interface card (NIC) 401. The NIC can also include … CPU cores 407, service processing offloads 408, packet buffer 409, and ethernet ports 410. [0060] The CPU cores may be used to implement discrete packet processing operations such … storage volume management (e.g., NVMe volume setup and/or management. [0088] RDMA.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, to modify HE per Raman to include multiple processors on the NIC card. This would have been advantageous as discussed above, as it would allow the modified system to provide not only load balancing amongst the ports/links, but also to provide multiple processors to load balance processing as this would provide resiliency and efficiency.
Regarding Claim 25:
HE (as modified by Raman) teaches on the invention of Claim 24 as described.
HE teaches that based on that the access instruction is for writing first data into the target storage, obtaining, or based on that the access instruction is for reading second data from the target storage, obtaining, ([0016] Optionally, the input/output command is used to write data to the target non-volatile memory or read data from the target non-volatile memory. The management command includes but is not limited to: reading device information of the target non-volatile memory, adding or deleting the target non-volatile memory, and the like.)
HE teaches on a processor in a NIC card and a second processor on the Host 201 (Fig 3). However, HE is silent on multiple processors on the NIC card.
Raman teaches on multiple processors on the NIC card. ([0055] FIG. 4 is a high-level diagram of a network interface card (NIC) 401. The NIC can also include … CPU cores 407, service processing offloads 408, packet buffer 409, and ethernet ports 410. [0060] The CPU cores may be used to implement discrete packet processing operations such … storage volume management (e.g., NVMe volume setup and/or management. [0088] RDMA.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, to modify HE per Raman to include multiple processors on the NIC card. This would have been advantageous as discussed above, as it would allow the modified system to provide not only load balancing amongst the ports/links, but also to provide multiple processors to load balance processing as this would provide further resiliency and efficiency.
Regarding Claim 26:
HE (as modified by Raman) teaches on the invention of Claim 24 as described.
HE teaches wherein the first network interface card further comprises a ([0012]-[0020] encapsulate the second packet into a packet that meets an NVMe over Fabric forwarding requirement, and send the encapsulated second packet by using the selected network port. [0025] Optionally, the data that needs to be stored and that is obtained by the processor from the control device may be transmitted by means of remote direct memory access (RDMA) or direct memory access (DMA).)
HE teaches on a processor in a NIC card and a second processor on the Host 201 (Fig 3). However, HE is silent on multiple processors on the NIC card.
Raman teaches on multiple processors on the NIC card. ([0055] FIG. 4 is a high-level diagram of a network interface card (NIC) 401. The NIC can also include … CPU cores 407, service processing offloads 408, packet buffer 409, and ethernet ports 410. [0060] The CPU cores may be used to implement discrete packet processing operations such … storage volume management (e.g., NVMe volume setup and/or management. [0088] RDMA.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, to modify HE per Raman to include multiple processors on the NIC card. This would have been advantageous as discussed above, as it would allow the modified system to provide not only load balancing amongst the ports/links, but also to provide multiple processors to load balance processing as this would provide further resiliency and efficiency.
Regarding Claim 29:
HE (as modified by Raman) teaches on the invention of Claim 26 as described.
HE teaches wherein the ([0119] The bus port 2022 is connected, by using a PCIe bus, to a CPU of a host that is in NVMe over Fabric and that serves as a control device, and receives a packet sent by the CPU of the host, or sends, to the CPU of the host, a packet sent by the forwarding and processing device to the host.)
HE teaches on a processor in a NIC card and a second processor on the Host 201 (Fig 3). However, HE is silent on multiple processors on the NIC card.
Raman teaches on multiple processors on the NIC card. ([0055] FIG. 4 is a high-level diagram of a network interface card (NIC) 401. The NIC can also include … CPU cores 407, service processing offloads 408, packet buffer 409, and ethernet ports 410. [0060] The CPU cores may be used to implement discrete packet processing operations such … storage volume management (e.g., NVMe volume setup and/or management. [0088] RDMA.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, to modify HE per Raman to include multiple processors on the NIC card. This would have been advantageous as discussed above, as it would allow the modified system to provide not only load balancing amongst the ports/links, but also to provide multiple processors to load balance processing as this would provide further resiliency and efficiency.
Regarding Claim 32:
HE teaches on the invention of Claim 31 as described.
HE teaches wherein the network interface card further comprises a processor, wherein the processor is configured to: when the network interface card is started, establish a non-volatile memory (NVMe) over fabric (NoF) connection and a remote direct memory access (RDMA) connection that are between the network interface card and the remote storage device, and the accessing the target storage over the first network link comprises: accessing the target storage according to an NoF protocol and an RDMA protocol by using the NoF connection and the RDMA connection. ([0012]-[0020] encapsulate the second packet into a packet that meets an NVMe over Fabric forwarding requirement, and send the encapsulated second packet by using the selected network port. [0025] Optionally, the data that needs to be stored and that is obtained by the processor from the control device may be transmitted by means of remote direct memory access (RDMA) or direct memory access (DMA). )
HE teaches on a processor in a NIC card and a second processor on the Host 201 (Fig 3). However, HE is silent on multiple processors on the NIC card.
Raman teaches on multiple processors on the NIC card. ([0055] FIG. 4 is a high-level diagram of a network interface card (NIC) 401. The NIC can also include … CPU cores 407, service processing offloads 408, packet buffer 409, and ethernet ports 410. [0060] The CPU cores may be used to implement discrete packet processing operations such … storage volume management (e.g., NVMe volume setup and/or management. [0088] RDMA.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, to modify HE per Raman to include multiple processors on the NIC card. This would have been advantageous as discussed above, as it would allow the modified system to provide not only load balancing amongst the ports/links, but also to provide multiple processors to load balance processing as this would provide further resiliency and efficiency.
Regarding Claim 33:
HE teaches (as modified by Raman) on the invention of Claim 32 as described.
HE teaches wherein the accessing the target storage over the first network link comprises at least one of: based on that the access instruction is for writing first data into the target storage, obtaining the first data from the computing device, and writing the first data into the target storage over the first network link according to the NoF protocol and the RDMA protocol; or based on that the access instruction is for reading second data from the target storage, obtaining the second data from the target storage according to the NoF protocol and the RDMA protocol, and sending the second data to the computing device. ([0012]-[0020] encapsulate the second packet into a packet that meets an NVMe over Fabric forwarding requirement, and send the encapsulated second packet by using the selected network port. [0025] Optionally, the data that needs to be stored and that is obtained by the processor from the control device may be transmitted by means of remote direct memory access (RDMA) or direct memory access (DMA).)
Regarding Claim 34:
HE (as modified by Raman) teaches on the invention of Claim 32 as described.
HE teaches wherein the first processor is at least one of: a field programmable logic gate array, a complex programmable logic device, a domain-specific architecture, a network processor, a digital signal processing circuit, a microcontroller, or a programmable controller. ([0119] The bus port 2022 is connected, by using a PCIe bus, to a CPU of a host that is in NVMe over Fabric and that serves as a control device, and receives a packet sent by the CPU of the host, or sends, to the CPU of the host, a packet sent by the forwarding and processing device to the host.)
Regarding Claim 38:
HE teaches on the invention of Claim 37 as described.
HE teaches wherein the network interface card further comprises a processor, wherein the processor is configured to: when the network interface card is started, establish a non-volatile memory (NVMe) over fabric (NoF) connection and a remote direct memory access (RDMA) connection that are between the network interface card and the remote storage device, and accessing the target storage over the first network link comprises: accessing the target storage according to an NoF protocol and an RDMA protocol by using the NoF connection and the RDMA connection. ([0012]-[0020] encapsulate the second packet into a packet that meets an NVMe over Fabric forwarding requirement, and send the encapsulated second packet by using the selected network port. [0025] Optionally, the data that needs to be stored and that is obtained by the processor from the control device may be transmitted by means of remote direct memory access (RDMA) or direct memory access (DMA).)
HE teaches on a processor in a NIC card and a second processor on the Host 201 (Fig 3). However, HE is silent on multiple processors on the NIC card.
Raman teaches on multiple processors on the NIC card. ([0055] FIG. 4 is a high-level diagram of a network interface card (NIC) 401. The NIC can also include … CPU cores 407, service processing offloads 408, packet buffer 409, and ethernet ports 410. [0060] The CPU cores may be used to implement discrete packet processing operations such … storage volume management (e.g., NVMe volume setup and/or management. [0088] RDMA.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, to modify HE per Raman to include multiple processors on the NIC card. This would have been advantageous as discussed above, as it would allow the modified system to provide not only load balancing amongst the ports/links, but also to provide multiple processors to load balance processing as this would provide further resiliency and efficiency.
Regarding Claim 39:
HE (as modified by Raman) teaches on the invention of Claim 38 as described.
HE teaches wherein the accessing the target storage over the first network link comprises at least one of: based on that the access instruction is for writing first data into the target storage, obtaining the first data from the computing device, and writing the first data into the target storage over the first network link according to the NoF protocol and the RDMA protocol; or based on that the access instruction is for reading second data from the target storage, obtaining the second data from the target storage according to the NoF protocol and the RDMA protocol, and sending the second data to the computing device. ([0016] Optionally, the input/output command is used to write data to the target non-volatile memory or read data from the target non-volatile memory. The management command includes but is not limited to: reading device information of the target non-volatile memory, adding or deleting the target non-volatile memory, and the like.)
Regarding Claim 40:
HE (as modified by Raman) teaches on the invention of Claim 38 as described.
HE teaches wherein the first processor is at least one of: a field programmable logic gate array, a complex programmable logic device, a domain-specific architecture, a network processor, a digital signal processing circuit, a microcontroller, or a programmable controller. ([0119] The bus port 2022 is connected, by using a PCIe bus, to a CPU of a host that is in NVMe over Fabric and that serves as a control device, and receives a packet sent by the CPU of the host, or sends, to the CPU of the host, a packet sent by the forwarding and processing device to the host.)
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0183591 A1 (HE) in view of US 2022/0094590 Al (LAL).
Regarding Claim 27:
HE teaches on the invention of Claim 21 as described.
HE teaches on a processor in a NIC card and a second processor on the Host 201 (Fig 3). However, HE is silent on multiple NIC cards.
LAL teaches, in the same field of endeavor, on a central Resource Manager is used to monitors the health of the Infrastructure Processing Units (IPUs) in the data center and in the event of in IPU failure, locates another IPU and assigns it to take over the failed IPU's functions, Abstract.
LAL also teaches wherein the computing device (Fig 5, System 500) further comprises a second network interface card (ie. IPU2 NIC 236), and the method further comprises: based on that the first network interface card (ie. IPU1 NIC 234), determines that no first network link exists between the first network interface card (ie. IPU2 NIC 236) and the target storage (ie. XPU 212-216), accessing, by the second network interface card (ie. IPU2 NIC 236), the target storage (ie. XPU 212-216) over a second network link between the second network interface card and the target storage (ie. XPU status links 250), the second network link being network-fault-free. (See Figs 5a-c, System 500 in various embodiments, comprises to IPU1 and IPU2 with respective NICs. [0067] FIG. 5a shows a healthy system 500a with an alternative implementation under which XPUs 212, 214, and 216 includes respective embedded fNICs 502,504, and 506. [0068] FIG. 5b shows a reconfigured system 500b under which IPU 204 has failed and its IPU operations for XPUs 212, 214, and 216 have been migrated to IPU 206.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, to modify HE per LAL to include wherein the computing device further comprises a second network interface card, and the method further comprises: based on that the first network interface card determines that no first network link exists between the first network interface card and the target storage, accessing, by the second network interface card, the target storage over a second network link between the second network interface card and the target storage, the second network link being network-fault-free. This would have been advantageous as discussed above, as it would allow the modified system to provide not only load balancing amongst the ports/links, but to also incorporate multiple NICs to load balance packet forwarding/processing as this would provide further resiliency and efficiency.
Conclusion & Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RACHEL J HACKENBERG whose telephone number is (571)272-5417. The examiner can normally be reached 9am-5pm M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Glenton B Burgess can be reached at (571)272-3949. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RACHEL J HACKENBERG/Primary Examiner, Art Unit 2454
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