DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The disclosure is objected to because of the following informalities:
In para. [0006], “FIG. 4 illustrates a manufacturing method of a multilayer ceramic capacitor;;” should read “FIG. 4 illustrates a manufacturing method of a multilayer ceramic capacitor;”.
In para. [0006], “FIG. 6 illustrates a side view of a multilayer section2s of an example of a polishing process” should read “FIG. 6 illustrates a side view of a multilayer section of an example of a polishing process”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, and 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. US 2019/0304697 A1.
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Figure 1: Examiner annotated fig. 8 of Nakamura ‘697.
Regarding claim 1, Nakamura ‘697 discloses
A multilayer ceramic electronic device comprising: a multilayer section (11 – fig. 1; para. [0042]) that has a substantially rectangular parallelepiped shape (fig. 1) and includes each of a plurality of internal electrode layers (12, 13 – fig. 3; para. [0048]) and each of a plurality of dielectric layers (ceramic between 12 and 13 – fig. 3) which are alternately stacked (para. [0048]), and a cover layer (20 – fig. 6; para. [0048]) provided outside in a stacking direction of the plurality of internal electrode layers and the plurality of dielectric layers (fig, 6); a side margin section (17 – fig. 4; para. [0047]) that is provided on a side surface facing in a first direction orthogonal to the stacking direction among six surfaces of the multilayer section (fig. 4); and an external electrode (14 and/or 15 – fig. 3; para. [0043]) that is provided on an end surface facing in a second direction (left and/or right, X – fig. 3) orthogonal to the first direction and the stacking direction among the six surfaces of the multilayer section and is connected to at least one of the plurality of internal electrode layers (fig. 3 and para. [0050]), wherein, when viewing a cross section of the multilayer section along the stacking direction and the first direction (fig. 4), at least at one corner of the multilayer section, a first end (first end of margin section – present office action figure 1, hereafter called POA1) of the side margin section in the stacking direction contacts a second end (second end of cover portion – POA1) of the cover layer in the first direction from the stacking direction (figs. 4 and/or 7-8), and wherein a ratio of a distance in the first direction between a tip of the first end of the side margin section and the side surface to a thickness of the cover layer in the stacking direction is 2.8 or less (See figs. 4 and/or 7-8. As the margin portion is disposed on a flat surface, the ratio is zero, meeting the claimed limitation of 2.8 or less).
Regarding claim 2, Nakamura ‘697 discloses
The multilayer ceramic electronic device as claimed in claim 1, wherein the at least one corner has a curved surface that is convex outward (POA1 clearly shows a corner that is convex outward), and wherein the first end is in contact with the curved surface provided at the second end in the stacking direction (After polishing, the first end of the side margin is in contact (even if it doesn’t overlap) with an edge of the curved surface at the second end. See POA1).
Regarding claim 5, Nakamura ‘697 discloses
The multilayer ceramic electronic device as claimed in claim 1,
wherein the ratio of the distance in the first direction between the tip of the first end of the
side margin section and the side surface to the thickness of the cover layer in the stacking direction
is 1.0 or less (See figs. 4 and/or 7-8. As the margin portion is disposed on a flat surface, the ratio is zero, meeting the claimed limitation of 1.0 or less).
Regarding claim 9, Nakamura ‘697 discloses
A manufacturing method of a multilayer ceramic electronic device comprising: polishing a multilayer section (fig. 9 and 111 – figs. 17-18; paras. [0114-0116]) that has a substantially rectangular parallelepiped shape (111 – fig. 17) and includes each of a plurality of internal electrode layers (112 – fig. 17) and each of a plurality of dielectric layers (ceramic between internal electrodes – fig. 17) which are alternately stacked, and a cover layer (top and/or bottom ceramic layer – fig. 17) provided outside in a stacking direction (Z) of the plurality of internal electrode layers and the plurality of dielectric layers; forming a side margin section (117 – figs. 15-16; para. [0102]) that is provided on a side surface facing in a first direction (Y) orthogonal to the stacking direction among six surfaces of the multilayer section; and forming an external electrode (14 and/or 15 – fig. 1; paras. [0120-0121]) that is provided on an end surface facing in a second direction (X) orthogonal to the first direction and the stacking direction among the six surfaces of the multilayer section and is connected to at least one of the plurality of internal electrode layers (para. [0050]), wherein, in the forming of the side margin section (Note that polishing is part of the side margin forming process), the side margin section is formed so that, when viewing a cross section of the multilayer section along the stacking direction and the first direction, at least at one corner of the multilayer section, a first end (first end of margin section –POA1) of the side margin section in the stacking direction contacts a second end (second end of cover portion – POA1) of the cover layer in the first direction from the stacking direction, and a ratio of a distance in the first direction between a tip of the first end of the side margin section and the side surface to a thickness of the cover layer in the stacking direction is 2.8 or less (See figs. 4 and/or 7-8. As the margin portion is disposed on a flat surface, the ratio is zero, meeting the claimed limitation of 2.8 or less).
Regarding claim 10, Nakamura ‘697 discloses
The method as claimed in claim 9 ,wherein, in the polishing of the multilayer section, a curved surface that is convex outward is formed at the at least one corner (POA1 clearly shows a corner that is convex outward), and wherein, in the forming of the side margin section, the side margin section is formed so that the first end is in contact with the curved surface provided at the second end in the stacking direction (After polishing, the first end of the side margin is in contact (even if it doesn’t overlap) with an edge of the curved surface at the second end. See POA1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita JP 2020004815 A in view of Ikeda US 2016/0163453 A1.
Regarding claim 1, Fujita ‘815 discloses
A multilayer ceramic electronic device comprising: a multilayer section (24 – fig. 1; para. [0035]) that has a substantially rectangular parallelepiped shape (see fig. 1) and includes each of a plurality of internal electrode layers (26 and/or 27 – fig. 3; para. [0036]) and each of a plurality of dielectric layers (25 – fig. 3; para. [0036]) which are alternately stacked, and a cover layer (top and/or bottom ceramic – fig. 12) provided outside in a stacking direction (T) of the plurality of internal electrode layers and the plurality of dielectric layers (See fig. 2); a side margin section (22 and/or 23 – fig. 12; para. [0035]) that is provided on a side surface (20 and/or 21 – fig. 3; para. [0035]) facing in a first direction (W) orthogonal to the stacking direction among six surfaces of the multilayer section; and an external electrode (28 and/or 29 – fig. 1; para. [0040]) that is provided on an end surface (36 and/or 37 – fig. 3; para. [0063]) facing in a second direction (L) orthogonal to the first direction and the stacking direction among the six surfaces of the multilayer section and is connected to at least one of the plurality of internal electrode layers (para. [0040]), wherein, when viewing a cross section of the multilayer section along the stacking direction and the first direction, at least at one corner of the multilayer section, a first end of the side margin section in the stacking direction contacts a second end of the cover layer in the first direction from the stacking direction (See any corner of fig. 12), and wherein a distance in the first direction between a tip of the first end of the side margin section and the side surface is less than 15 μm (X2 – fig. 12; para. [0131]). Fujita ‘815 fails to explicitly disclose wherein a ratio of a distance in the first direction between a tip of the first end of the side margin section and the side surface to a thickness of the cover layer in the stacking direction is 2.8 or less.
Ikeda ‘453 discloses wherein a thickness of the cover layer in the stacking direction is 15 to 25 μm (Para. [0022] and Table I). After modifying the cover layer of Fujita ‘815 to be 15 to 25 μm, a ratio of a distance in the first direction between a tip of the first end of the side margin section and the side surface to a thickness of the cover layer in the stacking direction is less than 1 μm, meeting the claimed range.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the cover layer of Fujita ‘815 to have a thickness to 15 to 25 μm as taught by Ikeda ‘453 in order to manufacture a multilayer ceramic component which suppresses moisture intrusion without sacrificing volumetric efficiency (Paras. [0022-0024] of Ikeda ‘453).
Regarding claim 2, modified Fujita ‘815 discloses
The multilayer ceramic electronic device as claimed in claim 1, wherein the at least one corner has a curved surface that is convex outward (See any corner of fig. 12 of Fujita ‘815), and wherein the first end is in contact with the curved surface provided at the second end in the stacking direction (See any corner of fig. 12 and para. [0129] of Fujita ‘815).
Regarding claim 3, modified Fujita ‘815 discloses
The multilayer ceramic electronic device as claimed in claim 1 but fails to explicitly disclose wherein the ratio of the distance in the first direction between the tip of the first end of the side margin section and the side surface to the thickness of the cover layer in the stacking direction is 0.2 or more.
However, Fujita ‘815 teaches that the distance in the first direction between the tip of the first end of the side margin section and the side surface is a result effective variable for improving impact resistance (para. [0129] of Fujita ‘815).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to adjust the distance in the first direction between the tip of the first end of the side margin section and the side surface in Fujita ‘815 to be 5 μm or more and less than 15 μm to achieve a multilayer component with improved impact resistance and moisture resistance (Paras. [0129] and [0131] of Fujita ‘815). Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. After this modification, the ratio of the distance in the first direction between the tip of the first end of the side margin section and the side surface to the thickness of the cover layer in the stacking direction is 0.2 μm or greater and less than 1 μm, meeting the claimed range.
Regarding claim 4, modified Fujita ‘815 discloses
The multilayer ceramic electronic device as claimed in claim 1 but fails to explicitly disclose wherein the ratio of the distance in the first direction between the tip of the first end of the side margin section and the side surface to the thickness of the cover layer in the stacking direction is 0.5 or more.
However, Fujita ‘815 teaches the distance in the first direction between the tip of the first end of the side margin section and the side surface is a result effective variable for improving impact resistance (para. [0129] of Fujita ‘815).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to adjust the distance in the first direction between the tip of the first end of the side margin section and the side surface in Fujita ‘815 to be 12.5 μm or more and less than 15 μm to achieve a multilayer component with improved impact resistance and moisture resistance (Paras. [0129] and [0131] of Fujita ‘815). Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. After this modification, the ratio of the distance in the first direction between the tip of the first end of the side margin section and the side surface to the thickness of the cover layer in the stacking direction is 0.5 μm or greater and less than 1 μm, meeting the claimed range.
Regarding claim 5, modified Fujita ‘815 discloses
The multilayer ceramic electronic device as claimed in claim 1, wherein the ratio of the distance in the first direction between the tip of the first end of the side margin section and the side surface to the thickness of the cover layer in the stacking direction is 1.0 or less (After modification of Fujita ‘815 with Ikeda ‘453 in claim 1, the ratio is 1.0 or less).
Regarding claim 6, modified Fujita ‘815 discloses
The multilayer ceramic electronic device as claimed in claim 1, wherein the distance in the first direction between the tip of the first end and the side surface is less than 15 μm (Para. [0131] of Fujita ‘815), and wherein the thickness of the cover layer in the stacking direction is 11.2 to 85.2 μm (Para. [0022] and Table 1 of Ikeda ‘453 discloses 15 to 25 μm which is completely within the claimed range). Fujita ‘815 fails to explicitly disclose wherein the distance in the first direction between the tip of the first end and the side surface is 2.1 to 240.2 μm.
However, Fujita ‘815 teaches the distance in the first direction between the tip of the first end of the side margin section and the side surface is a result effective variable for improving impact resistance (para. [0129] of Fujita ‘815).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to adjust the distance in the first direction between the tip of the first end of the side margin section and the side surface in Fujita ‘815 to be 2.1 μm or more and less than 15 μm (completely within the claimed range) to achieve a multilayer component with improved impact resistance and moisture resistance (Paras. [0129] and [0131] of Fujita ‘815). Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 7, modified Fujita ‘815 discloses
The multilayer ceramic electronic device as claimed in claim 1, wherein the distance in the first direction between the tip of the first end and the side surface is less than 15 μm (Para. [0131] of Fujita ‘815), and wherein the thickness of the cover layer in the stacking direction is 10 to 90 μm (Para. [0022] and Table 1 of Ikeda ‘453 discloses 15 to 25 μm, which is completely within the claimed range). Fujita ‘815 fails to explicitly disclose wherein the distance in the first direction between the tip of the first end and the side surface is 5.0 to 200.0 μm.
However, Fujita ‘815 teaches the distance in the first direction between the tip of the first end of the side margin section and the side surface is a result effective variable for improving impact resistance (para. [0129] of Fujita ‘815).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to adjust the distance in the first direction between the tip of the first end of the side margin section and the side surface in Fujita ‘815 to be 5.0 μm or more and less than 15 μm (completely within the claimed range) to achieve a multilayer component with improved impact resistance and moisture resistance (Paras. [0129] and [0131] of Fujita ‘815). Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 8, modified Fujita ‘815 discloses
The multilayer ceramic electronic device as claimed in claim 1, wherein the distance in the first direction between the tip of the first end and the side surface is less than 15 μm (Para. [0131] of Fujita ‘815), and wherein the thickness of the cover layer in the stacking direction is 20 to 55 μm (Para. [0022] of Ikeda ‘453 discloses 15 to 25 μm. Furthermore, Table I of Ikeda ‘453 shows examples of 20 μm and 25 μm (overlapping with the claimed range) for a highly reliable and small sized capacitor with water resistance.). Fujita ‘815 fails to explicitly disclose wherein the distance in the first direction between the tip of the first end and the side surface is 10.0 to 90.0 μm.
However, Fujita ‘815 teaches the distance in the first direction between the tip of the first end of the side margin section and the side surface is a result effective variable for improving impact resistance (para. [0129] of Fujita ‘815).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to adjust the distance in the first direction between the tip of the first end of the side margin section and the side surface in Fujita ‘815 to be 10.0 μm or more and less than 15 μm (completely within the claimed range) to achieve a multilayer component with improved impact resistance and moisture resistance (Paras. [0129] and [0131] of Fujita ‘815). Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 9, Fujita ‘815 discloses
A manufacturing method of a multilayer ceramic electronic device comprising: polishing a multilayer section (19 – fig. 9; para. [0076]) that has a substantially rectangular parallelepiped shape (19 – fig. 3) and includes each of a plurality of internal electrode layers (26 and/or 27 – fig. 3; para. [0032]) and each of a plurality of dielectric layers (25 – fig. 3; para. [0036]) which are alternately stacked, and a cover layer (top and/or bottom ceramic – fig. 3) provided outside in a stacking direction (T) of the plurality of internal electrode layers and the plurality of dielectric layers; forming a side margin section (fig. 11 and para. [0089]) that is provided on a side surface (20 and/or 21 – fig. 3; para. [0035]) facing in a first direction (W) orthogonal to the stacking direction among six surfaces of the multilayer section; and forming an external electrode (28 and/or 29 – fig. 1; paras. [0040-0041]) that is provided on an end surface (36 and/or 37 – fig. 3; para. [0063]) facing in a second direction (L) orthogonal to the first direction and the stacking direction among the six surfaces of the multilayer section and is connected to at least one of the plurality of internal electrode layers (Para. [0040]), wherein, in the forming of the side margin section, the side margin section is formed so that, when viewing a cross section of the multilayer section along the stacking direction and the first direction, at least at one corner of the multilayer section, a first end of the side margin section in the stacking direction contacts a second end of the cover layer in the first direction from the stacking direction (See any corner of fig. 12), and wherein a distance in the first direction between a tip of the first end of the side margin section and the side surface is less than 15 μm (X2 – fig. 12; para. [0131]). Fujita ‘815 fails to explicitly disclose wherein a ratio of a distance in the first direction between a tip of the first end of the side margin section and the side surface to a thickness of the cover layer in the stacking direction is 2.8 or less.
Ikeda ‘453 discloses wherein a thickness of the cover layer in the stacking direction is 15 to 25 μm (Para. [0022] and Table I). After modifying the cover layer of Fujita ‘815 to be 15 to 25 μm, a ratio of a distance in the first direction between a tip of the first end of the side margin section and the side surface to a thickness of the cover layer in the stacking direction is less than 1 μm, meeting the claimed range.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the cover layer of Fujita ‘815 to have a thickness to 15 to 25 μm as taught by Ikeda ‘453 in order to manufacture a multilayer ceramic component which suppresses moisture intrusion without sacrificing volumetric efficiency (Paras. [0022-0024] of Ikeda ‘453).
Regarding claim 10, modified Fujita ‘815 discloses
The method as claimed in claim 1, wherein, in the polishing of the multilayer section, a curved surface that is convex outward is formed at the at least one corner (Para. [0126] and fig. 12 of Fujita ‘815), and wherein, in the forming of the side margin section, the side margin section is formed so that the first end is in contact with the curved surface provided at the second end in the stacking direction (See any corner of fig. 12 of Fujita ‘815).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20170287643 A1: fig. 3
US 20180166217 A1: fig. 13
US 20200312567 A1: figs. 5 and 6
US 11626251 B2: fig. 3
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/T.J.T./Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
