Prosecution Insights
Last updated: October 25, 2026
Application No. 19/072,417

UTILIZING CAPACITORS ON A CHIP OF A CAPACITIVE SENSING DEVICE

Non-Final OA §102§103
Filed
Mar 06, 2025
Priority
Mar 07, 2024 — provisional 63/562,509 +1 more
Examiner
MCKINNEY, ANGELICA M
Art Unit
2694
Tech Center
2600 — Communications
Assignee
Invensense Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
441 granted / 517 resolved
+23.3% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
17 currently pending
Career history
543
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
52.8%
+12.8% vs TC avg
§102
26.1%
-13.9% vs TC avg
§112
16.4%
-23.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 517 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Allowable Subject Matter Claims 1-26 are allowed. The following is a statement of reasons for the indication of allowable subject matter: the closest prior art (Seeger US-PG-PUB No. 2023/0192479) discloses a MEMS device comprises a sense element circuit comprising a bias resistance, a charge-pump, and a capacitive sense element comprising an electrode and a sense capacitance. The charge-pump generates, at a bias resistor electrically coupled to the electrode, a bias voltage that is inversely proportional to a capacitance value comprising a value of the sense capacitance to facilitate maintenance of a nominally constant charge on the electrode. The closest prior art fails to teach that the first sense element node is electrically connected to a first bond pad of the MEMS chip and is biased via a defined bias voltage that is externally applied to the first bond pad, wherein the first sense element node is electrically connected to a first node of the capacitor, wherein a second node of the capacitor is electrically connected to a second bond pad of the MEMS chip, and wherein the second sense element node is electrically connected to a third bond pad of the MEMS chip; and a semiconductor chip comprising an amplifier that is electrically connected, via the second bond pad, to the second node of the capacitor, as recited in claim 1. Regarding claim 15, it recites that the first sense element node is electrically connected to a first bond pad of the MEMS chip and is biased via a defined bias voltage that is externally applied to the first bond pad, wherein the first sense element node is electrically connected to a first node of the first capacitor, wherein the second sense element node is electrically connected to a first node of the second capacitor and a second bond pad of the MEMS chip, and wherein a second node of the first capacitor and a second node of the second capacitor are electrically connected to a third bond pad of the MEMS chip; and a semiconductor chip comprising a ground pad that is electrically connected to the third bond pad of the MEMS chip. Therefore, the prior art does not meet the requirements of the claimed invention as recited in the broadest claim respectively since there is no suggestion to render obviousness in combination or individually to teach the limitations as claimed. For the above reason, independent claims 1 and 15 are allowed. Regarding claims 29-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 102 5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 7. Claim 27 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Deas et al. (Hereinafter Deas) US-PG-PUB No. 2016/0167946. Regarding claim 27, Deas teaches A micro-electro-mechanical system (MEMS) sensor (Fig. 2 shows a MEMS transducer die 200….Para. [0042], Lines 1-5), comprising: a substrate layer (Fig. 2 shows a substrate 105) comprising an acoustic port (Fig. 2 shows a cavity 123); a capacitive sense element (Fig. 2 shows a transducer structure 101….Para. [0060], Lines 6-11) comprising a backplate layer (Fig. 2 shows backplate layers 116, 117 and 118) and a diaphragm layer (Fig. 2 shows a membrane layers 114 and 115), wherein the capacitive sense element (i.e. transducer structure 101) converts an external pressure that has been applied to the diaphragm layer via the acoustic port 1008 into an electrical signal (capacitive transducers for detecting and/or generating pressure/sound waves or transducers for detecting acceleration. MEMS capacitive microphones typically comprise a first electrode, which is moveable with respect to a second fixed electrode in response to incident acoustic waves….Para. [0003], Lines 1-11), and wherein the backplate layer (i.e. backplate layers 116, 117 and 118) and the diaphragm layer (i.e. membrane layers 114 and 115) are disposed over the substrate layer (Fig. 2 shows a substrate 105) as shown in Fig. 2; and a capacitor comprising a dielectric layer (Fig. 2 shows a dielectric 108) that is disposed between a portion of the substrate layer (i.e. substrate 105) and the diaphragm layer (i.e. membrane layers 114 and 115) as shown in Fig. 2. Claim Rejections - 35 USC § 103 8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 10. Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Deas in view of Yang et al. (Hereinafter Yang) US-PG-PUB No. 2014/0072152. Regarding claim 28, Deas teaches all the features with respect to claim 27 as outlined above. Deas does not explicitly teach that the diaphragm layer comprises at least one of polysilicon, epi-silicon, or silicon-germanium. Yang teaches that the diaphragm layer comprises at least one of polysilicon (Para. [0025], Line 4). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the diaphragm layer, as taught by Deas with the polysilicon diaphragm layer, as taught by Yang. The motivation that by combining both teachings the diaphragm layer would be able to have high stiffness and low density, which allow diaphragm layer to maintain uniform excursion and avoid break‑up. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGELICA M MCKINNEY whose telephone number is (571)270-3321. The examiner can normally be reached 7AM-3PM EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Vivian Chin can be reached at 571-272-7848. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANGELICA M MCKINNEY/Primary Examiner, Art Unit 2694
Read full office action

Prosecution Timeline

Mar 06, 2025
Application Filed
Sep 30, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+13.8%)
2y 2m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 517 resolved cases by this examiner. Grant probability derived from career allowance rate.

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