DETAILED ACTION
Notice to Applicant
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-5, 8-11, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuperman et al. (US 2001/0003424 – hereinafter “Kuperman”).
Per claim 1, Kuperman teaches a capacitive voltage sensor arrangement, comprising:
a first input terminal (An upper terminal connected to a condenser C1 (Fig. 1; ¶21));
a second input terminal (A ground terminal connected to a condenser C2 (Fig. 1; ¶21-22);
a first sensor output terminal (A first terminal connected to a cable 2 (Fig. 1));
a second sensor output terminal (A second terminal connected to the cable 2 (Fig. 1));
a capacitive voltage divider (Combination of condensers C1 and C2 (Fig. 1; ¶21)) including a primary capacitor (Fig. 1; condenser C1; ¶21) arranged between the first input terminal and a first node (Common potential point of condensers C1 and C2 (Fig. 1; ¶22)), and a secondary capacitor (Fig. 1; condenser C2; ¶21) arranged between the first node and the second input terminal and electrically connected in series to the primary capacitor; and
a tuning circuit (Combination of resistors R1 and R3 and condensers C3 and C4 (Fig. 1; ¶22-23 and 49)) arranged between the first node, a second node (A node connected to an end of the resistor R3 (Fig. 1; ¶49)), a third node (A node connected to the ground terminal (Fig. 1; ¶22)), and a fourth node (A node connected between the ground terminal and the second terminal connected to the cable 2 (Fig. 1)), the second node is connected with the first sensor output terminal, the third node is connected with the second input terminal, and the fourth node is connected with the second sensor output terminal, the tuning circuit has only one or more passive components.
Per claim 2, Kuperman teaches the capacitive voltage sensor arrangement of claim 1, wherein the tuning circuit has a first resistor (Fig. 1; resistor R1; ¶23) arranged between the first node and the second node.
Per claim 3, Kuperman teaches the capacitive voltage sensor arrangement of claim 2, wherein the third node of the tuning circuit is directly connected with the fourth node (The third node is directly connected to the fourth node (Fig. 1)).
Per claim 4, Kuperman teaches the capacitive voltage sensor arrangement of claim 3, wherein the tuning circuit includes a first capacitor (Fig. 1; condenser C3; ¶22) arranged in parallel to the first resistor between the first node and the second node.
Per claim 5, Kuperman teaches the capacitive voltage sensor arrangement of claim 4, wherein the tuning circuit includes a second capacitor (Fig. 1; condenser C4; ¶22) arranged between the second node and the third node.
Per claim 8, Kuperman teaches the capacitive voltage sensor arrangement of claim 1, wherein the primary capacitor is formed by an electrode arrangement and a dielectric material or is formed by at least one discrete capacitor (The condenser C1 is a discrete capacitor (Fig. 1)).
Per claim 9, Kuperman teaches the capacitive voltage sensor arrangement of claim 1, wherein the secondary capacitor is formed by an electrode arrangement and a dielectric material or is formed by at least one discrete capacitor (The condenser C2 is a discrete capacitor (Fig. 1)).
Per claim 10, Kuperman teaches the capacitive voltage sensor arrangement of claim 1, wherein the primary capacitor has a capacitance of 10 pF-30 pF (¶37) and/or the secondary capacitor has a capacitance of 30 nF-300 nF.
Per claim 11, Kuperman teaches the capacitive voltage sensor arrangement of claim 2, wherein at least one of the first resistor has a resistance of 500 kΩ-2 MΩ, the primary capacitor has a capacitance of 1 pF-50 pF (¶37), and the secondary capacitor has a capacitance of 1 pF-500 pF.
Per claim 13, Kuperman teaches the capacitive voltage sensor arrangement of claim 1, wherein the second input terminal is connected to ground (¶22).
6. Claims 1, 6-9, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tziouvaras (US 2013/0234731).
Per claim 1, Tziouvaras teaches a capacitive voltage sensor arrangement, comprising:
a first input terminal (Fig. 1; terminal 111; ¶32);
a second input terminal (Fig. 1; terminal 140; ¶34);
a first sensor output terminal (Fig. 1; output 161; ¶34);
a second sensor output terminal (Fig. 1; output 162; ¶34);
a capacitive voltage divider (Combination of capacitive assemblies C1 and C2 (Fig. 1; ¶33)) including a primary capacitor (Fig. 1; capacitive assembly C1; ¶33) arranged between the first input terminal and a first node (A node between the capacitive assemblies C1 and C2 (Fig. 1)), and a secondary capacitor (Fig. 1; capacitive assembly C2; ¶33) arranged between the first node and the second input terminal and electrically connected in series to the primary capacitor; and
a tuning circuit (Circuitry including inductor L1 (Fig. 1; ¶33)) arranged between the first node, a second node (A node connected to an end of the inductor L1 (Fig. 1)), a third node (A node connected to the terminal 140 (Fig. 1)), and a fourth node (A node connected between the terminal 140 and a primary winding 155 (Fig. 1)), the second node is connected with the first sensor output terminal, the third node is connected with the second input terminal, and the fourth node is connected with the second sensor output terminal, the tuning circuit has only one or more passive components.
Per claim 6, Tziouvaras teaches the capacitive voltage sensor arrangement of claim 1, wherein the tuning circuit includes an inductor (Fig. 1; inductor L1; ¶33) arranged between the first node and the second node.
Per claim 7, Tziouvaras teaches the capacitive voltage sensor arrangement of claim 6, wherein the third node of the tuning circuit is directly connected with the fourth node (The third node is directly connected to the fourth node (Fig. 1)).
Per claim 8, Tziouvaras teaches the capacitive voltage sensor arrangement of claim 1, wherein the primary capacitor is formed by an electrode arrangement and a dielectric material or is formed by at least one discrete capacitor (The capacitor C1 is a discrete capacitor (Fig. 1)).
Per claim 9, Tziouvaras teaches the capacitive voltage sensor arrangement of claim 1, wherein the secondary capacitor is formed by an electrode arrangement and a dielectric material or is formed by at least one discrete capacitor (The capacitor C2 is a discrete capacitor (Fig. 1)).
Per claim 13, Tziouvaras teaches the capacitive voltage sensor arrangement of claim 1, wherein the second input terminal is connected to ground (¶34).
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim 12 is rejected under 35 U.S.C. 103 as being obvious over Tziouvaras in view of Tanabe et al. (US 2013/0285669 – hereinafter “Tanabe”).
Per claim 12, Tziouvaras does not teach the capacitive voltage sensor arrangement of claim 6, wherein the inductor has an inductance of 0.1 H - 5 H. In contrast, Tanabe teaches a ground fault detection circuit comprising a resonance circuit 21 having an inductor LE1 that has an inductance value of 3 H (Fig. 9; ¶53).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the arrangement of Tziouvaras such that the inductor L1 has an inductance of 0.1 H – 5 H. One of ordinary skill would make such a modification for the purpose of providing a suitable inductance between an AC source and a load (Tanabe; ¶53).
9. Claims 14 and 19-20 are rejected under 35 U.S.C. 103 as being obvious over Kuperman in view of Johnson et al. (US 2020/0158759 – hereinafter “Johnson”).
Per claim 14, Kuperman teaches a voltage sensor system, comprising:
a capacitive voltage sensor arrangement including a first input terminal (An upper terminal connected to a condenser C1 (Fig. 1; ¶21)), a second input terminal (A ground terminal connected to a condenser C2 (Fig. 1; ¶21-22), a first sensor output terminal (A first terminal connected to a cable 2 (Fig. 1)), a second sensor output terminal (A second terminal connected to the cable 2 (Fig. 1)), a capacitive voltage divider (Combination of condensers C1 and C2 (Fig. 1; ¶21)), and a tuning circuit (Combination of resistors R1 and R3 and condensers C3 and C4 (Fig. 1; ¶22-23 and 49)),
the capacitive voltage divider has a primary capacitor (Fig. 1; condenser C1; ¶21) arranged between the first input terminal and a first node (Common potential point of condensers C1 and C2 (Fig. 1; ¶22)), and a secondary capacitor (Fig. 1; condenser C2; ¶21) arranged between the first node and the second input terminal and electrically connected in series to the primary capacitor, and
the tuning circuit is arranged between the first node, a second node (A node connected to an end of the resistor R3 (Fig. 1; ¶49)), a third node (A node connected to the ground terminal (Fig. 1; ¶22)), and a fourth node (A node connected between the ground terminal and the second terminal connected to the cable 2 (Fig. 1)), the second node is connected with the first sensor output terminal, the third node is connected with the second input terminal, and the fourth node is connected with the second sensor output terminal, the tuning circuit has only one or more passive components.
However, Kuperman does not teach the system comprising: a first measurement output terminal and a second measurement output terminal, wherein the first sensor output terminal is connected to the first measurement output terminal and the second sensor output terminal is connected to the second measurement output terminal; and a measurement device including a burden capacitance arranged between the first measurement output terminal and the second measurement output terminal and a burden resistance arranged in parallel to the burden capacitance.
In contrast, Johnson teaches a voltage sensing system comprising a meter having output nodes A and B wherein an effective input resistance Rm and capacitance Cm of the meter are arranged in parallel between the output nodes A and B (Fig. 1; ¶153).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kuperman such that the first and second terminals of the cable 2 are connected, respectively, to first and second measurement output terminals wherein a measurement device is provided that includes a burden capacitance arranged between the first measurement output terminal and the second measurement output terminal and a burden resistance arranged in parallel to the burden capacitance. One of ordinary skill would make such a modification for the purpose of using a meter to sense a voltage across a capacitor (Johnson; ¶153).
Per claim 19, Kuperman in view of Johnson teaches the voltage sensor system of claim 14, wherein the burden capacitance is in a range of 1 pF-5000 pF (Johnson; ¶153) and/or the burden resistance is in a range of 2 kΩ-10 MΩ.
Per claim 20, Kuperman in view of Johnson teaches the voltage sensor system of claim 14, wherein the tuning circuit compensates (Kuperman; ¶49) an impedance of the burden caused by the measurement device arranged at the first measurement output terminal and the second measurement output terminal.
10. Claims 15-18 are rejected under 35 U.S.C. 103 as being obvious over Kuperman in view of Johnson, in further view of Ogle (US 5,107,201).
Per claim 15, Kuperman in view of Johnson does not explicitly teach the voltage sensor system of claim 14, further comprising a signal cable having a signal cable capacitance arranged between the first measurement output terminal and the second measurement output terminal.
In contrast, Ogle teaches a high voltage probe comprising capacitors 11-18 that are arranged in series and electrically connected to a coaxial cable 28 having a capacitance of 0.3 nfd (Fig. 1; col. 2, lines 36-38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kuperman in view of Johnson such that the cable 2 has a signal cable capacitance arranged between the first measurement output terminal and the second measurement output terminal. One of ordinary skill would make such a modification for the purpose of using a coaxial cable (Ogle; col. 2, lines 36-38).
Per claim 16, Kuperman in view of Johnson does not explicitly teach the voltage sensor system of claim 14, further comprising a signal cable having a signal cable capacitance arranged between the first node and the third node.
In contrast, Ogle teaches a high voltage probe comprising capacitors 11-18 that are arranged in series and electrically connected to a coaxial cable 28 having a capacitance of 0.3 nfd (Fig. 1; col. 2, lines 36-38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kuperman in view of Johnson such that the cable 2 has a signal cable capacitance arranged between the first node and the third node. One of ordinary skill would make such a modification for the purpose of using a coaxial cable (Ogle; col. 2, lines 36-38).
Per claim 17, Kuperman in view of Johnson in further view of Ogle teaches the voltage sensor system of claim 15, wherein the signal cable capacitance is in a range of 2 pF-1600 pF (Ogle; col. 2, lines 36-38).
Per claim 18, Kuperman in view of Johnson in further view of Ogle teaches the voltage sensor system of claim 16, wherein the signal cable capacitance is in a range of 2 pF-1600 pF (Ogle; col. 2, lines 36-38).
11. Claims 14 and 19-20 are rejected under 35 U.S.C. 103 as being obvious over Tziouvaras in view of Johnson.
Per claim 14, Tziouvaras teaches a voltage sensor system, comprising:
a capacitive voltage sensor arrangement including a first input terminal (Fig. 1; terminal 111; ¶32), a second input terminal (Fig. 1; terminal 140; ¶34), a first sensor output terminal (Fig. 1; output 161; ¶34), a second sensor output terminal (Fig. 1; output 162; ¶34), a capacitive voltage divider (Combination of capacitive assemblies C1 and C2 (Fig. 1; ¶33)), and a tuning circuit (Circuitry including inductor L1 (Fig. 1; ¶33)),
the capacitive voltage divider has a primary capacitor (Fig. 1; capacitive assembly C1; ¶33) arranged between the first input terminal and a first node (A node between the capacitive assemblies C1 and C2 (Fig. 1)), and a secondary capacitor (Fig. 1; capacitive assembly C2; ¶33) arranged between the first node and the second input terminal and electrically connected in series to the primary capacitor, and
the tuning circuit is arranged between the first node, a second node (A node connected to an end of the inductor L1 (Fig. 1)), a third node (A node connected to the terminal 140 (Fig. 1)), and a fourth node (A node connected between the terminal 140 and a primary winding 155 (Fig. 1)), the second node is connected with the first sensor output terminal, the third node is connected with the second input terminal, and the fourth node is connected with the second sensor output terminal, the tuning circuit has only one or more passive components.
However, Tziouvaras does not teach the system comprising: a first measurement output terminal and a second measurement output terminal, wherein the first sensor output terminal is connected to the first measurement output terminal and the second sensor output terminal is connected to the second measurement output terminal; and a measurement device including a burden capacitance arranged between the first measurement output terminal and the second measurement output terminal and a burden resistance arranged in parallel to the burden capacitance.
In contrast, Johnson teaches a voltage sensing system comprising a meter having output nodes A and B wherein an effective input resistance Rm and capacitance Cm of the meter are arranged in parallel between the output nodes A and B (Fig. 1; ¶153).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Tziouvaras such that the outputs 161 and 162 are connected, respectively, to first and second measurement output terminals wherein a measurement device is provided that includes a burden capacitance arranged between the first measurement output terminal and the second measurement output terminal and a burden resistance arranged in parallel to the burden capacitance. One of ordinary skill would make such a modification for the purpose of using a meter to sense a voltage across a capacitor (Johnson; ¶153).
Per claim 19, Tziouvaras in view of Johnson teaches the voltage sensor system of claim 14, wherein the burden capacitance is in a range of 1 pF-5000 pF (Johnson; ¶153) and/or the burden resistance is in a range of 2 kΩ-10 MΩ.
Per claim 20, Tziouvaras in view of Johnson teaches the voltage sensor system of claim 14, wherein the tuning circuit compensates (Tziouvaras; ¶33) an impedance of the burden caused by the measurement device arranged at the first measurement output terminal and the second measurement output terminal.
12. Claims 15-18 are rejected under 35 U.S.C. 103 as being obvious over Tziouvaras in view of Johnson, in further view of Ogle.
Per claim 15, Tziouvaras in view of Johnson does not explicitly teach the voltage sensor system of claim 14, further comprising a signal cable having a signal cable capacitance arranged between the first measurement output terminal and the second measurement output terminal.
In contrast, Ogle teaches a high voltage probe comprising capacitors 11-18 that are arranged in series and electrically connected to a coaxial cable 28 having a capacitance of 0.3 nfd (Fig. 1; col. 2, lines 36-38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Tziouvaras in view of Johnson such that a cable is provided having a signal cable capacitance arranged between the first measurement output terminal and the second measurement output terminal. One of ordinary skill would make such a modification for the purpose of using a coaxial cable (Ogle; col. 2, lines 36-38).
Per claim 16, Tziouvaras in view of Johnson does not explicitly teach the voltage sensor system of claim 14, further comprising a signal cable having a signal cable capacitance arranged between the first node and the third node.
In contrast, Ogle teaches a high voltage probe comprising capacitors 11-18 that are arranged in series and electrically connected to a coaxial cable 28 having a capacitance of 0.3 nfd (Fig. 1; col. 2, lines 36-38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Tziouvaras in view of Johnson such that a cable is provided having a signal cable capacitance arranged between the first node and the third node. One of ordinary skill would make such a modification for the purpose of using a coaxial cable (Ogle; col. 2, lines 36-38).
Per claim 17, Tziouvaras in view of Johnson in further view of Ogle teaches the voltage sensor system of claim 15, wherein the signal cable capacitance is in a range of 2 pF-1600 pF (Ogle; col. 2, lines 36-38).
Per claim 18, Tziouvaras in view of Johnson in further view of Ogle teaches the voltage sensor system of claim 16, wherein the signal cable capacitance is in a range of 2 pF-1600 pF (Ogle; col. 2, lines 36-38).
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAS A. SANGHERA whose telephone number is (571)272-4787. The examiner can normally be reached M-Th, alt. Fri, 8-5 EST.
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/JAS A SANGHERA/Primary Examiner, Art Unit 2852
