Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independence: 1 and 17.
b. Claims 1-20 are pending on the application.
Preliminary Amendment
2. Acknowledgment is made of applicant’s Preliminary Amendment, filed 03/06/2025. The changes and remarks disclosed therein were considered.
Claims 3, 4, 5, 6, 7, 9, 10, 11, 12,13, 14, 16 and 20 have been amended. Therefore, claims 1-20 are pending in the application.
Drawings
3. The drawings were received on 03/06/2025. These drawings are reviewed and accepted by examiners.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pathak et al. (US No.: 10,650,874 B2; “Pathak et al”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation, and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Pathak et al in Figures 1-13 directly discloses a spintronic adaptive approximate memory (SAAM) (a memory device, Figures 1-4) comprising:
a magnetic tunnel junction (MTJ) (a magnetic element 10, Figs. 1-4) having a critical current switching level (a switch transistor 20, Figs. 1-4); and
a write circuit (a write circuit 100, Figs. 1-4) having a write current adaptability to provide a variable write current (the write circuit 100 provides a write current to the magnetic element 10 in a write operation, column 2, 61-62) to selectively provide deterministic or probabilistic switching of said MTJ (the magnetic element 10, for example, the write circuit 100 provide the write current between the write line 33 and the source line 32 during a write operation, where is the magnetic element 10 coupled to the write line 33 and other coupled the source line 32 through to the switch transistor 20, see at least in Figures 1-4, column 2, lines 43 to column 5, lines 14 and the related disclosures).
Regarding dependent claim 2, Pathak et al in Figures 1-13 directly discloses a spintronic adaptive approximate memory (SAAM) (a memory device, Figures 1-4), further comprising a plurality of MTJs (a magnetic element 10) each storing a single bit (the magnetic element 10 use as stored data bit in memory).
Regarding dependent claim 3, Pathak et al in Figures 1-13 directly discloses a spintronic adaptive approximate memory (SAAM) (a memory device, Figures 1-4), wherein the write current varies the write current (the write circuit 100 provide the write current, column 2, lines 61-62).
Regarding dependent claim 4, Pathak et al in Figures 1-13 directly discloses a spintronic adaptive approximate memory (SAAM) (a memory device, Figures 1-4), the MTJ (the magnetic element 10) having an adjustable switching current level configured to provide adjustable approximation in a critical current regime (the write circuit 100 provides a write current to the magnetic element 10 in a write operation. The write current includes a first/second current in the form of a pulse having first/second peak; respectively, column 2, lines 61-67).
Allowable Subject Matter
5. Claims 5-16, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respect to dependent claim 5, the prior art fails to teach or suggest the claimed limitations, namely, the MTJ having an input value and lower significance bits, and adaptive approximation applied to the lower significance bits based on the input value.
With respect to dependent claim 6, the prior art fails to teach or suggest the claimed limitations, namely, the MTJ having adaptive approximation based on quality of the application execution feedback.
With respect to dependent claims 7-9, the prior art fails to teach or suggest the claimed limitations, namely, further comprising a circuit having one or more transistors, said one or more transistors having a size that provides an MTJ switching current below a critical current for said one or more transistors, wherein said one or more transistors are small but can be integrated to act as bigger transistors, wherein the small transistors are adaptively integrated at run time.
With respect to dependent claim 10, the prior art fails to teach or suggest the claimed limitations, namely, further comprising smaller transistors and larger transistors, wherein said MTJ having bit-wise approximation performed at a transistor level using the smaller transistors.
With respect to dependent claim 11, the prior art fails to teach or suggest the claimed limitations, namely, wherein MTJ switching current below a critical current reduces probability of MTJ switching.
With respect to dependent claim 12, the prior art fails to teach or suggest the claimed limitations, namely, where approximation is applied only to lower bits in any approximate memories besides spintronic.
With respect to dependent claim 13, the prior art fails to teach or suggest the claimed limitations, namely, further comprising an input-aware write circuit to use appropriate level approximation based on the input value or quality of the application execution feedback.
With respect to dependent claims 14-15, the prior art fails to teach or suggest the claimed limitations, namely, further comprising a smart write circuit that compares input data with stored data to avoid writing duplicate using a comparator circuit to compare the input data against the data already saved in the cell. wherein said smart write circuit can assist any other type of memories besides spintronic where write operations are energy inefficient, by avoiding the writing of duplicate values.
With respect to dependent claim 16, the prior art fails to teach or suggest the claimed limitations, namely, the SAAM having a write operation as a part of the precharge phase, and an evaluation phase having a read operation.
6. Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 17: there is no teaching, suggestion, or motivation for combination in the prior art to “a magnetic tunnel junction (MTJ) having critical current switching level at which the MTJ switches between a low-resistance state and a high-resistance state, wherein a sub-critical current level below the critical current switching level has a lower probability of switching the MTJ between the low-resistance state and the high-resistance state” in a spintronic adaptive approximate memory (SAAM) as claimed in the independent claim 17. Claims 18-20 are also allowed because of their dependency on claim 17.
Conclusion
Examiner's note: Examiner has cited columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested by the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al (US. 2014/0347918 A1) discloses mram write pulse to dissipated intermediate state domains.
Lin et al (US. 2024/0071451 A1) discloses three-state spintronic device memory cell, memory array and read-write circuit.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights