Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MINNEN et al. (USPGPUB 2021/0356330).
Regarding claims 1, 8, Minnen et al. disclose a data compression system for compressing data and method (figs. 1 – 6; paragraph 0058) , the data compression system comprising: a parallel processing device, wherein the parallel processing device is configured to divide compression target data into a plurality of pieces of partial data , execute compression processing on the partial data in parallel (paragraph 0103), calculate an appearance probability for each predetermined data unit of the partial data by using a neural network in the compression processing (paragraph 0056), and output a coded bit string which is a bit string subjected to entropy coding for each data unit based on the data unit and the appearance probability (paragraphs 0053, 0054, 0062, 0069; fig. 5), and processing for implementing the neural network includes first conversion processing of executing matrix multiplication processing, and second conversion processing of inputting a processing result of the first conversion processing and converting each element of a matrix resulting from the processing result into an integer of 1 bit, subsequent to the first conversion processing (paragraphs 0039, 00041, 0044, 0063, 0064; figs. 2, 6).
Regarding claim 7, Minnen et al. disclose a data compression program causing a computer to execute processing of compressing data, wherein the computer includes a parallel processing device (figs. 1 – 6; paragraph 0058), the parallel processing device is configured to divide compression target data into a plurality of pieces of partial data (paragraph 0103), execute compression processing on the partial data in parallel, calculate an appearance probability for each predetermined data unit of the partial data by using a neural network in the compression processing (paragraph 0056) , and output a coded bit string which is a bit string subjected to entropy coding to the data unit based on the data unit and the appearance probability (paragraphs 0053, 0054, 0062, 0069; fig. 5), and processing of implementing the neural network includes first conversion processing of executing matrix multiplication processing, and second conversion processing of inputting a processing result of the first conversion processing and converting each element of a matrix resulting from the processing result into an integer of 1 bit, subsequent to the first conversion processing (paragraphs 0039, 00041, 0044, 0063, 0064; fig. 2).
Regarding claim 2 , Minnen et al. disclose a data compression system (figs. 1 – 6) wherein the parallel processing device includes one or more calculation processors provided with a plurality of matrix calculation cores and a plurality of integer calculation cores, and the parallel processing device is configured to execute the first conversion processing using the matrix calculation cores, and execute the second conversion processing using the integer calculation cores (paragraphs 0039, 00041, 0044, 0063, 0064; fig. 2).
Regarding claim 3 , Minnen et al. disclose a data compression system (figs. 1 – 6), wherein the calculation processor further includes a first memory connected to the matrix calculation cores and the integer calculation cores, and the parallel processing device is configured to store the processing result of the first conversion processing in the first memory, and input the processing result of the first conversion processing stored in the first memory to the second conversion processing, and store a processing result of the second conversion processing in the first memory (figs. 1 – 6; paragraphs 0039, 00041, 0044, 0063, 0062, 0064, 0069; fig. 2).
Regarding claim 4 , Minnen et al. disclose a data compression system (figs. 1 – 6), wherein the parallel processing device rearranges a calculation result stored in the first memory into a layout in the first memory that matches a layout of input data input to the first conversion processing (figs. 1, 2) .
Regarding claim 4 , Minnen et al. disclose a data compression system (figs. 1 – 6), wherein the parallel processing device stores, in a second memory having a larger capacity and a lower speed than the first memory, a calculation result obtained by rearranging the layout in the first memory (figs. 1, 2).
Regarding claim 6 , Minnen et al. disclose a data compression system (figs. 1 – 6), wherein the first memory stores an input matrix in which each element is 1 bit and a calculation matrix in which each element is a plurality of bits and matrix multiplication is executed with the input matrix, the matrix calculation core executes calculation between matrices in which each element is 1 bit, the matrix calculation core executes calculation between the input matrix and a virtual matrix in which, for each element having multiple bits in the calculation matrix, each order of the element is assumed to be an element of 1 bit, and stores a matrix of a calculation result in the first memory, and the integer calculation core multiplies each element of the matrix of the calculation result by a coefficient corresponding to each element of the calculation matrix, generates a summed matrix in which a value obtained by summing values of a plurality of elements based on the same element of the calculation matrix serves as each element of a matrix obtained by the multiplication, and outputs a matrix obtained by converting each element of the summed matrix into 1 bit as the processing result of the second conversion processing (paragraphs 0039, 00041, 0044, 0063, 0064; fig. 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM.
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845
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