DETAILED ACTION
Reissue
The present reissue application is directed to US 8,664,113 B2 (“113 Patent”). 113 Patent issued on March 4, 2014 with claims 1-12 from application 13/096,898 filed on April 28, 2011, which does not claim priority to any previous application.
This application was filed on March 6, 2025. Since this date is after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions. Furthermore, the present application is being examined under the pre-AIA first to invent provisions.
This application is a continuation reissue of reissue application 17/542,158 (now US RE50,384 E).
Broadened claims are not permitted in this reissue application. Applicant did not demonstrate an intent to broaden within two years of the issue date of 113 Patent.
The most recent amendment was filed on March 6, 2025. The status of the claims is:
Claims 1 and 7-12: Amended
Claims 2-6: Original
Claims 13-29: New
This is a first, non-final action.
References and Documents Cited in this Action
113 Patent (US 8,664,113 B2)
Zhang (US 2010/0044869 A1)
Chang (US 2006/0113675 A1)
US RE50,384 E
Summary of Rejections and Objections in this Action
Examiner objects to the drawings.
Claims 1-29 are rejected as being based upon a defective reissue declaration under 35 U.S.C. 251.
Claims 1-12 are rejected under 35 U.S.C. 251 because the reissue application is not correcting an error in the original patent.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite
Claims 1-4 and 6-8 are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Zhang.
Claims 5 and 9 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Zhang in view of Chang.
Claims 10 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 20 of U.S. Patent No. US RE50,384 E.
Summary of the Claims
113 Patent is directed to a method for forming a multilayer interconnection structure. Claim 20 is representative:
20. A method for forming a multi-layer interconnection comprising a lower conductor
disposed in a first dielectric, an interlayer dielectric disposed on the first dielectric, first and second upper conductors disposed in the interlayer dielectric, and a self-aligned via conductor in electrical contact with and interconnecting the lower conductor and the first upper conductor, wherein the lower conductor comprises copper, the method comprising:
forming the self-aligned via conductor, the first upper conductor, and the second upper conductor comprising:
providing a substrate having thereon the first dielectric and the lower conductor disposed in the first dielectric, wherein the lower conductor is elongated in a first horizontal direction and has a width in a second horizontal direction orthogonal to the first horizontal direction, and an upper surface of the lower conductor is located in a recess below an upper surface of the first dielectric, wherein a depth of the recess is between 10 nm and 100 nm;
depositing the interlayer dielectric on the first dielectric and the lower conductor;
etching, in desired locations of the first and second upper conductors, respective first and second upper cavities in the interlayer dielectric wherein etching a lower portion of the first upper cavity comprises selectively etching the interlayer dielectric with respect to the first dielectric and the selective etching exposes the upper surface of the lower conductor and a portion of the first dielectric;
filling the first and second upper cavities with an electrical conductor; and
removing an excess of electrical conductor overlying the interlayer dielectric to electrically separate the first upper conductor and the second upper conductor,
wherein an upper portion of the self-aligned via conductor is self-aligned to the first upper conductor and a lower portion of the self-aligned via conductor is self-aligned to the lower conductor.
Claims 1, 10, and 20 are the independent claims. Claim 10 recites similar steps and limitations as claim 20, except a depth of the recess is approximately equal to a thickness of a topmost layer of the first dielectric.
Drawings
Figures 1 and 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Corrected drawing sheets in compliance with 37 CFR 1.173(b)(3) are required in reply to the Office action to avoid abandonment of the application. Applicant must submit a replacement sheet for each sheet of drawings containing a Figure to be revised. Any replacement sheet must comply with 37 CFR 1.84 and include all of the figures appearing on the original version of the sheet, even if only one figure is being amended. Each figure that is amended must be identified by placing the word “Amended” at the bottom of that figure. Any added figure must be identified as “New.” In the event that a figure is canceled, the figure must be identified as “Canceled” and also surrounded by brackets. All changes to the figure(s) must be explained, in detail, beginning on a separate sheet which accompanies the papers including the amendment to the drawings. See MPEP 1413 for further information.
Oath/Declaration
The reissue oath/declaration filed with this application is defective (see 37 CFR 1.175 and MPEP § 1414) because of the following:
The declaration is a copy of the one filed in prior reissue US RE50,384 E. The statement of error in this declaration describes an error in 113 Patent that was already corrected by US RE50,384 E. The declaration in the present reissue application must identify a new error; or if the same error corrected in the parent is also being corrected in the continuation reissue application, but the error is being corrected in a different way, a statement is needed to explain compliance with 37 CFR 1.175(f)(2) for a reissue application filed on or after September 16, 2012. For example, Applicant should explain how a same error is being corrected in a different way in this reissue application.
Applicant must file a new declaration (rather than merely correct the error statement in remarks) as no proper declaration has been yet entered in this application.
Claim Rejections - 35 USC § 251
Claims 1-29 are rejected as being based upon a defective reissue declaration under 35 U.S.C. 251 as set forth above. See 37 CFR 1.175.
The nature of the defect(s) in the declaration is set forth in the discussion above in this Office action.
Claims 1-12 are also rejected under 35 U.S.C. 251 because the reissue application is not correcting an error in the original patent. Claims 1-12 of 113 Patent have been superseded by the previous reissue US RE50,384 E. Once a claim in the patent has been reissued, it does not exist in the original patent; thus, it cannot be reissued from the original patent in another reissue application. Applicant should cancel claims 1-12. The subject matter recited in claims 1-12 may be presented as additional new claims (and the dependencies of new claims such as claims 13-19 that currently depend on claim 10 should be amended accordingly). See MPEP 1451 I for further details (the discussion therein of numbering claims in a divisional reissue application applies also to this continuation reissue).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
First, claims 1-19 are indefinite because the inventions of claims 1-19 are not particularly pointed out and distinctly claimed. Claims 1-12 present one coverage in previous reissue US RE50,384 E and another in the present reissue application. This is inconsistent. Once a claim in the patent has been reissued, it does not exist in the original patent; thus, it cannot be reissued from the original patent in another reissue application. See MPEP 1451 I for further details (the discussion therein of numbering claims in a divisional reissue application applies also to this continuing reissue). New claims 13-19 depend on claim 10 and are also indefinite for the same reason as parent claim 10.
Second, claims 1-9 are also indefinite because of language in independent claim 1. Claim 1 recites “determining whether or not a desired multilevel interconnection stack having Q total interconnection levels is complete” and “repeating providing, etching, filling, determining, and removing for any or all desired successive interconnection level N up to N=Q-1.” Claim 1 is indefinite because there is insufficient antecedent basis for “multilevel interconnection stack” and “interconnection level.” The claim does not relate any previously recited elements to a “multilevel interconnection stack” or an “interconnection level.” The step of determining whether a multilevel interconnection stack is “complete” is unclear because it is unclear what is “a desired multilevel interconnection stack having Q total interconnection levels.” The step of “repeating providing, etching, filling, determining, and removing for any or all desired successive interconnection level N up to N=Q-1” is unclear because it is unclear what is a “successive interconnection level N” and also because it is unclear whether “any or all” includes none (i.e., for no level), whereby the repetition of steps would not occur at all. Claims 2-9 depend on claim 1 and are also indefinite for the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claims 1-4 and 6-8 are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Zhang.
Regarding independent claim 1, as well as the claim may be understood with respect to 35 U.S.C. 112 as discussed above, Zhang discloses a method for forming an integrated circuit (IC) 100 having a multilayer interconnect structure (Figures 1-3), comprising:
supplying a substrate 105 having thereon an Nth dielectric 130 (paragraph [0016]), in or on which it is desired to form a multi-layer interconnection having lower conductor 150, upper conductor 260 and interconnecting via 263;
forming the lower conductor 150 on the substrate with an upper surface of the lower conductor 150 recessed below an upper surface of the Nth dielectric (Figure 2; see also Figure 3b and paragraphs [0031]-[0034]);
providing an (N+1)th dielectric 275 above the Nth dielectric 130 and the upper surface of the lower conductor 150 (Figure 2);
etching an (N+1)th cavity through the (N+1)th dielectric from a desired location of the upper conductor 260 and exposing the upper surface of the lower conductor MN 150;
filling the (N+1)th cavity with an electrical conductor adapted to form the upper conductor 260 and the interconnecting via 263, and make electrical contact with the upper surface of the lower conductor MN (Figure 2; paragraphs [0023]-[0024]); and
determining whether or not a desired multilevel interconnection stack having Q total interconnection levels is complete, and if not: optionally removing conductor material in the (N+1)th cavity to lower an upper surface of the upper conductor MN+1 below an upper surface of the (N+1)th dielectric; and then incrementing N by one and repeating providing, etching, filling, determining, and removing for any or all desired successive interconnection level N up to N=Q-1 (i.e., as well as the claim may be understood, Zhang discloses that a same process is repeated for “additional interconnect levels”; paragraphs [0023]-[0025]).
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Regarding claim 2, Zhang discloses after N=Q-1, incrementing N by one and repeating at least providing, etching, and filling for interconnection level N=Q (i.e., as well as the claim may be understood, Zhang discloses that a same process is repeated for “additional interconnect levels”; paragraphs [0023]-[0025]).
Regarding claim 3, Zhang discloses that removing conductor material in the (N+1)th cavity to lower an upper surface of the upper conductor 260 below an upper surface of the (N+1)th dielectric 275 is accomplished by chemical-mechanical-polishing (CMP) (paragraph [0034]).
Regarding claim 4, Zhang discloses that removing conductor material in the (N+1)th cavity to lower an upper surface of the upper conductor 260 below an upper surface of the (N+1)th dielectric 275 is accomplished by etching an exposed surface of the upper conductor 260 (paragraph [0034]).
Regarding claim 6, Zhang discloses that forming the lower conductor 150 comprises: forming at least an Nth dielectric 130 on the substrate; etching an Nth cavity at least through the Nth dielectric 130, corresponding to the desired location of the lower conductor 150; filling the Nth cavity with electrically conductive material adapted to serve as the lower conductor 150; and removing conductive material in the Nth cavity to lower an upper surface of the lower conductor 150 below an upper surface of the Nth dielectric 130 within a recess portion of the Nth dielectric 130 around the Nth cavity (Figures 2 and 3b; paragraphs [0033]-[0034]).
Regarding claim 7, Zhang discloses that removing conductive material in the Nth cavity to lower an upper surface of the lower conductor 150 below an upper surface of the Nth dielectric 130 within a recess portion of the Nth dielectric 130 around the Nth cavity is accomplished by chemical-mechanical-polishing (CMP) (paragraph [0034]).
Regarding claim 8, Zhang discloses that removing conductive material in the Nth cavity to lower an upper surface of the lower conductor MN below an upper surface of the Nth dielectric within a recess portion of the Nth dielectric around the Nth cavity is accomplished by etching an exposed surface of the lower conductor MN (paragraph [0034]).
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 9 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Zhang in view of Chang.
Regarding claims 5 and 9, Zhang discloses a method as discussed above with regard to claims 1 and 6 respectively, including removing conductor material in the (N+1)th cavity to lower an upper surface of the upper conductor 260 below an upper surface of the (N+1)th dielectric 275 and removing conductive material in the Nth cavity to lower an upper surface of the lower conductor 150 below an upper surface of the Nth dielectric 130 (Zhang, Figures 2 and 3b; paragraphs [0033]-[0034]). Zhang discloses various ways to accomplish these steps (paragraph [0034]) but does not specifically disclose converting conductive material near an exposed upper surface of the upper or lower conductor to an oxide of the conductive material and then removing the oxide by etching.
However, Chang teaches a method that is related to the one disclosed by Zhang, including removing conductive material 120 in a cavity 106 to lower an upper surface 121/122 below an upper surface of a dielectric 112 (Chang; Figure 4; paragraphs [0031], [0034], [0050]). Chang further teaches converting conductive material near an exposed upper surface of the conductor to an oxide of the conductive material and then removing the oxide by etching (Chang, paragraph [0050]). Regarding claims 5 and 9, it would have been obvious to a person of ordinary skill in the art to converting conductive material near an exposed upper surface of the conductor to an oxide of the conductive material and then removing the oxide by etching as taught by Chang in the method disclosed by Zhang as an engineering design choice of another known technique to effectively perform the removing step with predictable results (again, the removing step is already disclosed by Zhang with different known techniques).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 10 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 20 of U.S. Patent No. US RE50,384 E. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding independent reissue claims 10 and 20, although the recited elements are not identical to the elements of claim 20 of US RE50,384 E, they are not patentably distinct from each other because they are of the same scope of invention with claim 20 of US RE50,384 E anticipating the instant claims. Reissue claims 10 and 20 and claim 20 of US RE50,384 E are directed to a method for forming a multi-layer interconnection comprising a lower conductor, an interlayer, first and second conductors, and a self-aligned via conductor, the method comprising steps of forming the self-aligned via conductor, providing a substrate, depositing the interlayer dielectric, etching and filling first and second upper cavities, and removing an excess of electrical conductor with identical details. Reissue claims 10 and 20 differ from claim 20 of US RE50,384 E only in that the reissue claims further recite a depth of the recess. Given claim 20 of US RE50,384 E, it would have been obvious to create reissue claims 10 and 20 by slightly changing the wording of limitations and/or removing limitations and merely further specifying a depth of the recess.
Allowable Subject Matter
Claims 10-19 may contain allowable subject matter if Applicant overcomes the 35 U.S.C. 112, 35 U.S.C. 251, and double patenting rejections set forth above in this action. Claims 20-29 may contain allowable subject matter if Applicant overcomes the 35 U.S.C. 251 and double patenting rejections set forth above in this action.
The prior art does not specifically disclose or fairly suggest a method including the combination of all of the elements, steps, and limitations recited in claims 10-29 (including all of the limitations of any respective parent claims and as well as claims may be understood with respect to 35 U.S.C. 112(b) as discussed above), particularly including
a self-aligned via conductor in electrical contact with and interconnecting the lower conductor and the first upper conductor, wherein the lower conductor comprises copper; and
forming the self-aligned via conductor, the first upper conductor, and the second upper
conductor comprising:
providing a substrate having thereon the first dielectric and the lower conductor disposed in the first dielectric, wherein the lower conductor is elongated in a first horizontal direction and has a width in a second horizontal direction orthogonal to the first horizontal direction, and an upper surface of the lower conductor is located in a recess below an upper surface of the first dielectric,
wherein a depth of the recess is approximately equal to a thickness of a topmost layer of the first dielectric or wherein a depth of the recess is between 10 nm and 100 nm; and
depositing the interlayer dielectric on the first dielectric and the lower conductor;
etching, in desired locations of the first and second upper conductors, respective first and second upper cavities in the interlayer dielectric wherein etching a lower portion of the first upper cavity comprises selectively etching the interlayer dielectric with respect to the first dielectric and the selective etching exposes the upper surface of the lower conductor and a portion of the first dielectric;
filling the first and second upper cavities with an electrical conductor; and
removing an excess of electrical conductor overlying the interlayer dielectric to electrically separate the first upper conductor and the second upper conductor,
wherein an upper portion of the self-aligned via conductor is self-aligned to the first upper conductor and a lower portion of the self-aligned via conductor is self-aligned to the lower
conductor.
Conclusion
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which this reissue application is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application. These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Applicant is notified that any subsequent amendment to the specification and/or claims must comply with 37 CFR 1.173(b).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patents/laws/interview-practice.
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Any inquiry concerning this communication or earlier communications from the examiner, or as to the status of this proceeding, should be directed to Examiner Christina Leung at telephone number (571) 272-3023; the Examiner’s supervisor, SPE Patricia Engle at (571) 272-6660; or the Central Reexamination Unit at (571) 272-7705.
/CHRISTINA Y. LEUNG/Primary Examiner, Art Unit 3991
Conferees:
/Patricia L Engle/SPRS, Art Unit 3991
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