Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 14 is objected to because of the following informalities: Claim 14 includes the language “configured to obtain generate an”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-21 and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Srinivasan et al. (US 11799460 B1 and Srinivasan hereinafter.) in view of Nakamura et al. (US 20220337230 A1 and Nakamura hereinafter.).
Regarding claim 1, Srinivasan discloses a method for synchronizing digital reference clock signals for Digital-to-analog converter (DAC) serializers and Analog-to-Digital converter (ADC) deserializers [col 1 lines 34-51], the method comprising: activating a phase locked loop (PLL) of a communication system to generate an ADC/DAC reference signal [PLL_CLK shown in fig. 3]; obtaining a DAC Enable (DACEN) signal at a DAC [signal RST, col 10 lines 4-7]. Srinivasan discloses further generating, at a first digital reference clock generator [104C of 120 shown in fig. 1B] associated with the DAC [130], based on the ADC/DAC reference signal [col 9 lines 30-38], a serializer digital reference clock [DCLK/SYSREF] for a serializer coupled to the DAC [col 5 lines 59-63]; and generating, at a second digital reference clock generator [104D of 120 shown in fig. 1B] associated with an ADC [140], based on the ADC/DAC reference signal [receiving clock information from 120 shown in fig. 1B, with 120 shown in fig. 3],], a deserializer digital reference clock [DCLK/SYSREF] for a deserializer coupled to the ADC [col 5 lines 59-63], wherein: the serializer digital reference clock and the deserializer digital reference clock are each respectively generated by frequency division of the ADC/DAC reference signal [col 6 lines 51-56].
Srinivasan does not explicitly disclose the method for synchronizing digital reference clock signals for Digital-to-analog converter (DAC) serializers and Analog-to-Digital converter (ADC) in a radio frequency (RF) communication system.
However, Srinivasan discloses [pg. 2] “For JESD204B/C communications, reference clock PLLCLK may be of relatively high frequency, such as on the order of several GHz.“. It would have obvious to one of ordinary skill in the art before the effective filing date to use the invention described by Swinivasan within an RF communication system because the operational frequency of an RF communication system reaches several GHz.
Srinivasan does not explicitly disclose generating, based on the DACEN signal, a SET signal, wherein the SET signal is aligned with a phase of the ADC/DAC reference signal; the deserializer digital reference clock based on the SET signal and the serializer digital reference clock and the deserializer digital reference clock are synchronized to a known phase based on the SET signal.
However, Nakamura discloses [fig. 2] generating, based on the DACEN signal [RST signal], a SET signal [RSTB_SYNC signal], wherein the SET signal is aligned with a phase of the ADC reference signal [RSTB_SYNC signal phase aligned with CLK as shown in fig. 6 for use in an ADC circuit 102 shown in fig. 10]. Nakamura discloses further
Regarding claim 2, Srinivasan in view of Nakamura discloses further in a receive mode, deserializing, by the deserializer, a portion of a serial digital output of the ADC [Srinivasan, col 5 lines 59-63], wherein the deserializer is clocked by the deserializer digital reference clock [Srinivasan, col 6 lines 51-56]; and in a transmit mode, serializing, by the serializer, a serial digital input to the DAC [Srinivasan, col 5 line 59-63], wherein the serializer is clocked by the serializer digital reference clock [Srinivasan, col 6 lines 51-56].
Regarding claim 3, Srinivasan in view of Nakamura does not explicitly disclose wherein the ADC/DAC reference signal has a bandwidth of at least twice that of a signal being converted at the ADC or a signal being converted at the DAC.
However, the requirement that a digitized signal must have a bandwidth twice that of the sampling frequency, otherwise known as the Nyquist frequency, is well known to someone trained in the art before the effective filing date. since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 4, Srinivasan in view of Nakamura does not explicitly disclose wherein the ADC/DAC reference signal is a differential signal and wherein the ADC/DAC reference signal is converted within the RF communication system to a single ended internal ADC/DAC reference signal.
However, Srinivasan discloses [col 1 lines 46-59] the use of High-speed serial interface standards such as the low voltage differential signaling (LVDS) standard. It would have been a simple practice to one trained in the art before the effective filing date to adapt an external PLL signal being a differential signal and convert this signal to single ended as an internal reference signal. Since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 5, Srinivasan in view of Nakamura discloses further wherein a voltage of the SET signal changes to a high voltage after a rising edge of the single ended internal ADC/DAC reference signal [Nakamura, fig. 6, RSTB_SYNC high at T14 after a rising edge of CLK] following activation of the DAC_EN signal is identified [Nakamura, fig. 6, system reset at T11].
Regarding claim 6, Srinivasan in view of Nakamura discloses further wherein the DACEN signal is synchronized to a synchronization signal of the RF communication system [Nakamura, para. 26].
Regarding claim 7, Srinivasan in view of Nakamura discloses further wherein the DACEN signal is coupled to an active low reset port of a frequency divider of the RF communication system [Nakamura, fig. 2, output of INV1 on reset terminals RB of flip flops 11-13], wherein the frequency divider is configured to generate the serializer digital reference clock [circuit 10 shown in fig. 2 of Nakamura part of circuit 310 shown in fig. 3 of Srinivasan, with DIVOUT of Srinivasan used to generate DCLK/SYSREF].
Regarding claim 8, Srinivasan in view of Nakamura discloses further wherein the SET signal is generated by a SET signal generator [Nakamura, fig. 2, circuit 10].
Regarding claim 10, Srinivasan in view of Nakamura discloses further wherein a frequency of the ADC/DAC reference signal is divided by two (2) or four (4) to generate the serializer digital reference clock and the deserializer digital reference clock [Srinivasan, DIV_VAL allowing for a division value of 2 or 4].
Regarding claim 11, Srinivasan in view of Nakamura does not explicitly disclose wherein a frequency of the ADC/DAC reference signal is divided using one or more flip-flops to generate the serializer digital reference clock and the deserializer digital reference clock.
However, the use of flip-flops to divide down the frequency of a clocking signal is well known in the art. It would have been a simple practice for someone trained in the art before the effective filing date to use flip flops within synchronous counter 312 of Srinivasan to have a frequency of the ADC/DAC reference signal is divided using one or more flip-flops to generate the serializer digital reference clock and the deserializer digital reference clock.
Regarding claim 12, Srinivasan in view of Nakamura discloses further wherein: a plurality of deserializer reference clocks comprises the deserializer digital reference clock [Srinivasan, fig. 4A, a plurality of possible deserializer reference clocks via step 400 and 410]; and each deserializer reference clock of the plurality of deserializer reference clocks has a respective different phase [Srinivasan, fig. 4A, step 408].
Regarding claim 13, Srinivasan in view of Nakamura discloses further wherein the plurality of deserializer reference clocks comprises four deserializer reference clocks [Srinivasan, fig. 4a, steps 400 and 410 with a possible 4 differing DIV_VAL values of deserializer reference clock], wherein the respective different phases for the four deserializer reference clocks comprise ninety degree phase increments [Srinivasan, fig. 4a, step 408 allowing for phase shift of clock output].
Regarding claim 14, Srinivasan discloses an apparatus for synchronizing digital reference signals for DAC serializers and ADC deserializers [col 1 lines 34-51], the apparatus comprising: a PLL [PLL_CLK shown in fig. 3] configured to obtain generate an ADC/DAC reference signal [PLL_CLK]. Srinivasan discloses further a first digital reference clock generator [104C of 120 shown in fig. 1B] associated with the DAC [130] and configured to generate a serializer digital reference clock [DCLK/SYSREF] based on the ADC/DAC reference signal [col 9 lines 30-38] by frequency dividing the ADC/DAC reference signal [DIVOUT shown in fig. 3 associated with 104C shown in fig. 1B]; and a second digital reference clock generator [104D of 120 shown in fig. 1B] associated with an ADC [140] and configured to generate a deserializer digital reference clock [DCLK/SYSREF] based on the ADC/DAC reference signal [col 9 lines 30-38] by frequency dividing the ADC/DAC reference signal [DIVOUT shown in fig. 3 associated with 104D].
Srinivasan does not explicitly disclose a SET signal generator included within a DAC and configured to obtain a DAC_EN signal and to generate a SET signal based on an activation of the DAC_EN signal. Wherein the SET signal is aligned with a phase of the ADC/DAC reference signal. Wherein the serializer digital reference clock and the deserializer digital reference clock are synchronized to a known phase based on the SET signal.
However, Nakamura discloses [fig. 2] a SET signal generator [10] within a digital/analog domain conversion circuit [fig. 10 showing ADC circuit 102, para. 89 and fig. 2, para. 25 regarding reset synchronization unit 10] configured to obtain an enable signal [RST] and generate a SET signal [RSTB_SYNC signal] based on the enable signal [RST]. Wherein the SET signal is aligned with a phase of the ADC reference signal [RSTB_SYNC signal phase aligned with CLK as shown in fig. 6 for use with an ADC shown in fig. 10]. Wherein the serializer digital reference clock [clock provided to serializer 107 shown in fig. 10 are synchronized to a known phase based on the SET signal [para. 26-27]. It would have been obvious to someone trained in the art before the effective filing date to include the reset synchronization unit 10 of Nakamura within the integer divider 310 of Srinivasan to have with the integer divider 310 providing settable/restable synchronized clocks to the serializer 136 and deserializer 142 of Srinivasan to have a SET signal generator included within a DAC and configured to obtain a DAC_EN signal and to generate a SET signal based on an activation of the DAC_EN signal. Wherein the SET signal is aligned with a phase of the ADC/DAC reference signal. Wherein the serializer digital reference clock and the deserializer digital reference clock are synchronized to a known phase based on the SET signal thereby reducing the likelihood of a malfunction within a signal conversion circuit, thereby improving high-speed operation of the circuit.
Regarding claim 15, Srinivasan in view of Nakamura discloses further comprising: a deserializer configured to, in a receive mode, deserialize a portion of a serial digital output of the ADC [Srinivasan, col 5 lines 59-63], wherein the deserializer is clocked by the deserializer digital reference clock [Srinivasan, col 6 lines 51-56]; and a serializer configured to, in a transmit mode, serialize a serial digital output of the ADC [Srinivasan, col 5 lines 59-63], wherein the serializer is clocked by the serializer digital reference clock [Srinivasan, col 6 lines 51-56].
Regarding claim 16, Srinivasan in view of Nakamura does not explicitly disclose wherein the ADC/DAC reference signal has a bandwidth to be at least twice that of a signal being converted at ADC or the DAC.
However, the requirement that a digitized signal must have a bandwidth twice that of the sampling frequency, otherwise known as the Nyquist frequency, is well known to someone trained in the art before the effective filing date. since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 17, Srinivasan in view of Nakamura does not explicitly disclose wherein the ADC/DAC reference signal is a differential signal and wherein the ADC/DAC reference signal is converted to a single ended internal ADC/DAC reference signal by a differential to single-ended converter.
However, Srinivasan discloses [col 1 lines 46-59] the use of High-speed serial interface standards such as the low voltage differential signaling (LVDS) standard. It would have been a simple practice to one trained in the art before the effective filing date to adapt an external PLL signal being a differential signal and convert this signal to single ended as an internal reference signal. Since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 18, Srinivasan in view of Nakamura discloses further wherein a voltage of the SET signal changes to a high voltage signal after a rising edge of the single ended internal ADC/DAC reference signal [Nakamura, fig. 6, RSTB_SYNC high at T14 after a rising edge of CLK] following activation of the DAC_EN signal is identified [Nakamura, fig. 6, system reset at T11].
Regarding claim 19, Srinivasan in view of Nakamura does not explicitly disclose wherein the DAC_EN signal is synchronized to a synchronization signal of a phased array antenna system.
However, Nakamura discloses [para. 26] “The reset synchronization unit 10 … is a circuit that generates and outputs a reset synchronization signal RSTB_SYNC … by synchronizing a reset signal RST … input from the outside with a clock signal.”. Furthering this Srinivasan discloses [col 4 line 14-16] “For JESD204B/C communications, reference clock PLLCLK may be of relatively high frequency, such as on the order of several GHz.“. it would have obvious to one trained in the art before the effective filing date to utilize the invention described by Srinivasan in view of Nakamura to have the DAC_EN signal is synchronized to a synchronization signal of a phased array antenna system.
Regarding claim 20, Srinivasan in view of Nakamura discloses further wherein the DAC_EN signal is coupled to an active low reset port of a frequency divider [Nakamura, fig. 2, output of INV1 on reset terminals RB of flip flops 11-13], wherein the frequency divider is configured to generate the serializer digital reference clock [circuit 10 shown in fig. 2 of Nakamura part of circuit 310 shown in fig. 3 of Srinivasan, with DIVOUT of Srinivasan used to generate DCLK/SYSREF].
Regarding claim 21, Srinivasan in view of Nakamura discloses further wherein the SET signal is generated at a SET signal generator [Nakamura, fig. 2, circuit 10].
Regarding claim 23, Srinivasan in view of Nakamura discloses further wherein a frequency of the ADC/DAC reference signal is divided by two (2) or four (4) to generate the serializer digital reference clock and the deserializer digital reference clock [Srinivasan, DIV_VAL allowing for a division value of 2 or 4].
Regarding claim 24, Srinivasan in view of Nakamura does not explicitly disclose wherein a frequency of the ADC/DAC reference signal is divided using one or more flip-flops to generate the serializer digital reference clock and the deserializer digital reference clock.
However, the use of flip-flops to divide down the frequency of a clocking signal is well known in the art. It would have been a simple practice for someone trained in the art before the effective filing date to use flip flops within synchronous counter 312 of Srinivasan to have a frequency of the ADC/DAC reference signal is divided using one or more flip-flops to generate the serializer digital reference clock and the deserializer digital reference clock
Regarding claim 25, Srinivasan in view of Nakamura discloses further wherein: a plurality of deserializer reference clocks comprises the deserializer digital reference clock [Srinivasan, fig. 4A, a plurality of possible deserializer reference clocks via step 400 and 410]; and each deserializer reference clock of the plurality of deserializer reference clocks has a respective different phase [Srinivasan, fig. 4A, step 408].
Regarding claim 26, Srinivasan in view of Nakamura discloses further wherein: the plurality of deserializer reference clocks comprises four deserializer reference clocks [Srinivasan, fig. 4a, steps 400 and 410 with a possible 4 differing DIV_VAL values of deserializer reference clock]; and the respective different phases for the four deserializer reference clocks comprise ninety degree phase increments [Srinivasan, fig. 4a, step 408 allowing for phase shift of clock output].
Claims 9 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Srinivasan in view of Nakamura further in view of “78902” (JP 3078902 B2 and “78902” hereinafter).
Regarding claim 9, Srinivasan in view of Nakamura discloses all the features of claim 1 as indicated above. Srinivasan in view of Nakamura does not explicitly disclose wherein the SET signal includes a delay provided by one or more buffers.
However, “8902” disclose [fig. 26] wherein the SET signal [output of flip flop 25a-25e] includes a delay [pg. 28] provided by one or more buffers [buffers 26a-26e]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the invention as described by Srinivasan in view of Nakamura to include the delay buffers of “8902” within the synchronization circuit 10 of Nakamura to improve synchronization accuracy of a SET/RESET circuit.
Regarding claim 22, Srinivasan in view of Nakamura discloses all the features of claim 14 as indicated above. Srinivasan in view of Nakamura does not explicitly disclose wherein the SET signal includes a delay provided by one or more buffers.
However, “8902” disclose [fig. 26] wherein the SET signal [output of flip flop 25a-25e] includes a delay [pg. 28] provided by one or more buffers [buffers 26a-26e]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the invention as described by Srinivasan in view of Nakamura to include the delay buffers of “8902” within the synchronization circuit 10 of Nakamura to improve synchronization accuracy of a SET/RESET circuit.
Conclusion
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/JAMES G YEAMAN/Examiner, Art Unit 2836
/TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
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