Detailed Action
Response to Amendment
The amendment filed on 2/3/2026 has been entered and considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (PGPUB 2020/0380911 A1) in view of Lim et al (PGPUB 2019/0156730 A1).
As to claim 1, Park (Fig. 4) teaches, a display device (display device, Fig. 1) comprising:
a display panel (display unit 100) including a display area (i.e. area of display unit 100) where at least one pixel (pixel PX) is arranged and a non-display area (i.e. areas of scan driver 210, data driver 220) adjacent to the display area (¶ 39, 40); and
a gate driver (scan driver 210) disposed in the non-display area and including a scan signal generator (stage ST) configured to output at least one scan signal (scan signal SC)(¶ 40, 42) and an emission signal generator (emission driver) configured to output an emission signal (light emission control signal)(¶ 50), wherein at least one pixel includes:
a light emitting diode (light emitting element LED)(¶ 53),
a driving transistor (driving transistor M1) configured to drive the light emitting diode (¶ 52), and
at least one switching transistor (switching transistor M2) configured to drive the driving transistor (¶ 53), and
wherein the at least one scan signal is applied to different pixel rows (Figs. 1, 3: i.e. scan signals SC are applied to different scan lines),
wherein the scan signal generator includes:
a switch circuit (first drive controller 110, second driver controller 120, third drive controller 130, fourth drive controller 140) including a common node (first node N1), and an inverting node (second node N2) configured to operate opposite to the common node (¶ 83), and
an output circuit (output buffers 150B and 150A) configured to output a signal (scan signal SC(2) and scan signal SC(1) respectively) in response voltages of the common node and the inverting node of the switch circuit (¶ 62), and
wherein the switch circuit includes at least one stabilization transistor (transistor T12) having a first electrode (i.e. left terminal as shown in Fig. 4) connected to the common node and a gate electrode connected to a turn-on voltage (display on signal DIS_ON has gate on voltage)(¶ 159).
Park does not specifically teach a gate electrode connected to receive a turn-on voltage during all periods.
Lim (Fig. 3) teaches, a gate electrode (i.e. gate electrode of transistor Ts3) connected to receive a turn-on voltage (VGH) during all periods (i.e. VGH is a constant voltage).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lim’s method of driving the shift register into Park’s shift register, so as to reduce the area occupied by the shift register (¶ 10).
As to claim 2, Park (Fig. 4) teaches, wherein the scan signal generator includes:
a first scan signal generator (output buffer 150B) configured to generate a first scan signal (scan signal SC(2) or SCi+1)(¶ 62), and
a second scan signal generator (output buffer 150A) configured to generate a second scan signal (scan signal SC(1) or SCi)(¶ 62).
As to claim 4, Park (Fig. 5) teaches, wherein the second scan signal is applied as an on voltage before the first scan signal (Fig. 5: i.e. SC(i) is applied before SC(i+1)).
As to claim 10, Park (Fig. 4) teaches, wherein the output circuit includes at least one pull-up transistor (transistor T27 and T1) and at least one pull-down transistor (transistor T28 and T2)(¶ 125, 126m 131, 132.
As to claim 11, Park (Fig. 4) teaches, wherein the output circuit includes a first capacitor (capacitor C7) having a first electrode (i.e. upper electrode as shown in Fig. 4) connected to a gate electrode of the pull-down transistor and a second electrode (i.e. lower terminal as shown in Fig. 4) connected to an output terminal (i.e. output terminal of scan signal SC(i+1))(Fig. 4).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park and Lim as applied to claim 1 above, and further in view of Cho et al (PGPUB 2021/0043134 A1).
As to claim 3, Park and Lim teach the display device of claim 2, but do not specifically teach, wherein the first scan signal generator or the second scan signal generator is adjacent to the display area than the emission signal generator.
Cho (Figs. 2 and 3) teaches, wherein the first scan signal generator or the second scan signal generator (i.e. different stages of scan driver) is adjacent to the display area than the emission signal generator (Figs. 2 and 3: i.e. scan driver is adjacent to the pixel area as shown in Figs. 2 and 3).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Cho’s display structure regarding emission control driver and scan driver into Park’s display device as modified with the teaching of Lim, so as to reduce dead space at corners (¶ 56).
Claim(s) 5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park and Lim as applied to claim 1 above, and further in view of Kim et al (PGPUB 2019/0035322 A1).
As to claim 5, Park and Lim teach the display device of claim 1, but not specifically teach wherein the driving transistor is selected as p-type.
Kim (Fig. 2A) teaches, wherein the driving transistor is selected as p-type (Fig. 2A: i.e. driving transistor DT is a p-type transistor).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Kim’s pixel structure shift register structure into Park’s shift register as modified with the teaching of Lim, so as to reduce power consumption (¶ 64) and enhance the reliability of the connecting transistors (¶ 153).
As to claim 12, Park and Lim teach the display device of claim 10 but do not specifically teach wherein the output circuit includes a second capacitor having a first electrode connected to a gate high voltage line and a second electrode connected to the inverting node.
Kim (Fig. 5) teaches, wherein the output circuit includes a second capacitor (capacitor C2) having a first electrode (i.e. lower terminal as shown in Fig. 5) connected to a gate high voltage line (gate high voltage VGH) and a second electrode (i.e. upper terminal) connected to the inverting node (node QB).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Kim’s shift register structure into Park’s shift register with the teaching of Lim, so as to enhance the reliability of the connecting transistors (¶ 153).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park and Lim as applied to claim 1 above, and further in view of Li et al (PGPUB 2020/0243151 A1).
As to claim 6, Park and Lim teach the display device of claim 1, but do not specifically teach double-gate transistor.
Li (Fig. 7) teaches, wherein the at least one switching transistor is a double-gate transistor (¶ 89).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Li’s circuit structures into Park’s display device as modified with the teaching of Lim, so as to avoid leakage current loss and improve image display effect (¶ 69).
Claim(s) 8, 13, 14 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park and Lim as applied to claim 1 above, and further in view of Lee (PGPUB 2015/0187313 A1).
As to claim 8, Park and Lim teach the display device of claim 1, but do not specifically teach wherein the inverting node is charged with a low voltage applied by a turn-on operation of the switching transistor, which is turned on according to a clock signal.
Lee (Fig. 5) teaches, wherein the inverting node (node QB) is charged with a low voltage (gate-low voltage VGL) applied by a turn-on operation of the switching transistor, which is turned on according to a clock signal (shift clock CLK3)(Fig. 5, ¶ 59: i.e. T4 turns on in response to CLK3 to apply VGL to node QB).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lee’s shift register structure into Park’s shift register as modified with the teaching of Lim, so as to improve the reliability of initialization (¶ 50, 52).
As to claim 13, Park and Lim teach the display device of claim 1, but do not specifically teach the switch circuit includes a first to third transistors.
Lee (Fig. 5) teaches, wherein the switch circuit includes:
a first transistor (switch TFT T1) having a gate electrode connected to a start signal line (start pulse VST) and a first electrode (i.e. upper terminal) connected to the gate low voltage line (low-potential voltage VGL)(¶ 59),
a second transistor (switch TFT T2) having a gate electrode connected to a common node clock signal line (CLK4), a first electrode (i.e. upper electrode as shown in Fig. 5) connected to a second electrode (i.e. lower terminal of T1) of the first transistor, and a second electrode (i.e. lower terminal of T2) connected to the common node (Fig. 5: i.e. connects to node Q)(¶ 61), and
a third transistor (switch TFT T3) having a gate electrode connected to the inverting node (i.e. T3 connects to QB via gate electrode), a first electrode (i.e. lower terminal as shown in Fig. 5) connected to a gate high voltage line (high-potential voltage VGH), and a second electrode (i.e. upper terminal as shown in Fig. 5) connected to the common node (¶ 59).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lee’s shift register structure into Park’s shift register as modified with the teaching of Lim, so as to improve the reliability of initialization (¶ 50, 52).
As to claim 14, Park and Lim teach the display device of claim 16, but do not specifically teach the switch circuit includes a fourth, fifth, eighth and ninth transistors.
Lee (Fig. 5) teaches, wherein the switch circuit includes:
a fourth transistor (switch TFT T4) having a gate electrode connected to an inverting node clock signal line (shift clock CLK3), a first electrode (i.e. upper terminal of T4) connected to the gate low voltage line, and a second electrode (i.e. lower terminal of T4) connected to the inverting node (Fig. 5)(¶ 59),
a fifth transistor (switch TFT T5) having a gate electrode connected to the start signal line (i.e. connects to Vst), a first electrode (i.e. lower terminal of T5 as shown in Fig. 5) connected to the gate high voltage line, and a second electrode (i.e. upper terminal) connected to the inverting node (Fig. 5)(¶ 61),
an eighth transistor (switch TFT T8) having a gate electrode connected to the common node, a first electrode (i.e. lower terminal as shown in fig. 5) connected to the gate high voltage line, and a second electrode (i.e. upper terminal) connected to the common node (Fig. 5)(¶ 61), and
a ninth transistor (switch TFT Tqrst) having a gate electrode connected to a reset signal line (initialization pulse QRST), a first electrode (i.e. lower terminal as shown in Fig. 5) connected to the gate high voltage line, and a second electrode (i.e. upper terminal) connected to the common node (Fig. 5)(¶ 35, 59).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lee’s shift register structure into Park’s shift register as modified with the teaching of Lim, so as to improve the reliability of initialization (¶ 50, 52).
As to claim 19, Park (Fig. 5) teaches, wherein a period in which a (1-1)th scan signal maintains a low voltage and a period in which a (2-1)th scan signal maintains a low voltage do not overlap (carry signals CR(i) and CR(i+2) do not have low voltage overlap during T3 and T4), and a period in which a (1-2)th scan signal maintains a low voltage and a period in which a (2-2)th scan signal maintains a low voltage partially overlap (i.e. scan signals SC(i) and SC(i+1) partially overlap during T2).
Allowable Subject Matter
Claims 7, 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant’s claimed invention regards the shift register structure in a display device. Applicant’s invention in Fig. 22 teaches four sets of output units (transistors T6_1/T7_1, T6_2/T7_2, T6_3/T7_3 and T6_4/T7_4). Each of the transistors in each of the output unit comprises a pull-up transistor and a pull-down transistor. Each of the pull-up transistor is controlled by a corresponding stabilization transistor TBV1-TBV4. Regarding this, Applicant claims in claim 7 that “the switch circuit includes a first stabilization transistor, a second stabilization transistor, a third stabilization transistor, and a fourth stabilization transistor having first electrodes connected to the common node, and gate electrodes connected to a gate low voltage line”, which was previously indicated as allowable subject matter. Examiner conducted a search to find this limitation but could not find it. There are prior arts that teach multiple output unit per one shift register stage. However, none of the prior arts specifically teach having four different stabilization transistor for four output units as required by claim.
For claim 15, similar reason applies as claim 15 recites first to four stabilization transistors connected to corresponding nodes.
Followings are the relevant prior arts that regard shift register structure without four stabilization transistors.
Kim et al (PGPUB 2019/0035322 A1) – Kim teaches a shift register as shown in Fig. 5 without the four stabilization transistors.
Bai et al (PGPUB 2015/0170592 A1) – Bai teaches a shift register with three output unit as shown in Fig. 5 without the four stabilization transistors.
Chou et al (PGPUB 2014/0198022 A1) – Chou teaches a shift register with four output unit as shown in Fig. 1B without the four stabilization transistors.
Du (PGPUB 2018/0233098 A1) – Du teaches a shift register with output unit as shown in Fig. 4 without the four stabilization transistors.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8, 10-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623
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