Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 1/27/2026 has been entered and considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 8-11, 15 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al (PGPUB 2020/0380911 A1).
As to claim 1, Park (Figs. 2, 4) teaches, a display device (display device) comprising:
a display panel (display unit 100) including a display area (i.e. area of display unit 100) where a plurality of pixels (pixel PX) are arranged and a non-display area (i.e. areas of scan driver 210, data driver 220) surrounding the display area (¶ 39, 40); and
a gate driver (scan driver 210) disposed in the non-display area and including a scan signal generator (stage ST) configured to generate at least one scan signal (scan signals SC), wherein the plurality of pixels includes:
a light emitting diode (light emitting element LED)(¶ 53),
a driving transistor (driving transistor M1) configured to drive the light emitting diode (¶ 52), and
at least one switching transistor (switching transistor M2) configured to drive the driving transistor (¶ 53), and
wherein the scan signal generator includes:
a switch circuit (first driver controller 110, second drive controller 120, third drive controller 130, fourth drive controller 140) including a common node (first node N1), and an inverting node (second node N2) configured to operate opposite to the common node (¶ 83), and
an output circuit (output buffers 150B and 150A) configured to output a first scan signal (scan signal SC(2) or SCi+1) and a second scan signal (scan signal SC(1) or SCi) in response to the switch circuit (¶ 62), and, wherein the output circuit includes:
a first output transistor (transistors T27) and a second output transistor (transistor T28) configured to output the first scan signal in response to the common node and the inverting node (¶ 131, 167: i.e. in response to node N1, QN1 and T12), and a third output transistor (transistor T1) and a fourth output transistor (transistor T2) configured to output the second scan signal in response to the common node and the inverting node (¶ 125: i.e. in response to node N1, QN1 and T12),
wherein a voltage (i.e. voltage potential at N1) at the common node is input to a gate electrode (i.e. gate of transistor T27) of the first output transistor and a gate electrode (i.e. gate of transistor T1) of the third output transistor, and wherein a voltage at the inverting node is input to a gate electrode (i.e. gate of transistor T28) of the second output transistor and a gate electrode (i.e. gate of transistor T2) of the fourth output transistor (Fig. 4, ¶ 121, 122: i.e. when DIS_ON is applied, T12 and T13 turn on and connect to share the same signals from nodes N1 and N2 to nodes QN1 and QN2 respectively).
As to claim 2, Park (Fig. 4) teaches, wherein the first scan signal is output based on a first clock signal (scan control clock signal CLK4_SC)(¶ 76, 131).
As to claim 3, Park (Fig. 4) teaches, wherein the second scan signal is output based on a second clock signal (third scan clock signal CLK3-SC, ¶ 125).
As to claim 5, Park (Fig. 4) teaches, wherein the scan signal generator is configured to operate based on at least one reset signal (¶ 162: i.e. reset period RP, Fig. 5: i.e. RP is reset period at t12, ¶ 171: i.e. t12 / reset period RP is operated by signal SEN_ON).
As to claim 8, Park (Fig. 4) teaches, wherein the output circuit includes:
a first capacitor (capacitor C7) having a first electrode (i.e. upper terminal as shown in Fig. 4) connected to a gate electrode of the first output transistor and a second electrode (i.e. lower terminal as shown in Fig. 4) connected to a first output terminal (second output terminal OUT2 or SC(i+1)),
a second capacitor (capacitor C5) having a first electrode (i.e. upper terminal as shown in Fig. 4) connected to a gate electrode of the third output transistor and a second electrode (i.e. lower terminal as shown in Fig. 4) connected to a second output terminal (first output terminal SC(i)).
As to claim 9, Park (Fig. 4) teaches, wherein the scan signal generator includes:
a first scan signal generator (STI and output buffer with T27 and T28) configured to generate the first scan signal (Fig. 7), and
a second scan signal generator (STI and output buffer with T1 and T2) configured to generate the second scan signal (Fig. 7).
As to claim 10, Park (Fig. 1) teaches, wherein the first scan signal generator or the second scan signal generator is adjacent to the display area (Fig. 1: i.e. SCi+1, or SC2, is adjacent to SC1 as shown in the figure).
As to claim 11, Park (Fig. 5) teaches, wherein the second scan signal is applied as an on voltage before the first scan signal (Fig. 5: i.e. SC(i) is turned on before SC(i+1) as shown in the figure).
As to claim 15, Park (Fig. 4) teaches, wherein the switch circuit includes at least one stabilization transistor (transistor T12) having a first electrode (i.e. left terminal as shown in Fig. 4) connected to the common node and a gate electrode (i.e. gate of T12 in Fig. 4) connected to a second gate voltage line (i.e. connected to DIS_ON, which has gate off voltage in the sensing period)(¶ 118).
As to claim 18, Park (Fig. 4) teaches,
wherein the first output transistor has the gate electrode connected to the common node, a first electrode (i.e. upper terminal of T27) connected to a first clock signal line (CLK4_SC), and a second electrode (i.e. lower terminal of T27 as shown in Fig. 4) connected to the first output terminal (Fig. 4),
the second output transistor has the gate electrode connected to the inverting node (i.e. gate of T28 connected to N2 via T13), a first electrode (i.e. lower terminal of T28 as shown in Fig. 4) connected to a second gate voltage line (VGL2), and a second electrode (i.e. upper terminal as shown in Fig. 4) connected to the first output terminal (Fig. 4),
the third output transistor has the gate electrode (i.e. gate electrode of transistor T1) connected to the common node, a first electrode (i.e. upper terminal) connected to a second clock signal line (CLK3_SC), and a second electrode (i.e. lower terminal as shown in Fig. 4) connected to the second output terminal (Fig. 4), and
the fourth output transistor has the gate electrode (i.e. gate of T2 is connected to N2 via T13) connected to the inverting node, a first electrode (i.e. lower terminal of T2) connected to the second gate voltage line, and a second electrode (i.e. upper terminal of T2) connected to the second output terminal (Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Chung (PGPUB 2011/0227884 A1).
As to claim 4, Park teaches the display device of claim 1, but does not specifically teach wherein the scan signal generator is configured to operate based on at least six phases clock signals with different phases.
Chung (Fig. 3) teaches, wherein the scan signal generator is configured to operate based on at least six phases clock signals (six phase clock) with different phases (Fig. 3, ¶ 36).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Chung’s clock signal into Park’s shift register, so as to reduce generation of abnormal scan signal and provide a regular image (¶ 9).
Claim(s) 6, 7, 14, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Lee (PGPUB 2015/0187313 A1).
As to claim 6, Park teaches the display device of claim 1, but does not specifically teach, wherein the switch circuit includes a transistor disposed between the common node and a first gate voltage line and having a gate electrode connected to the inverting node.
Lee (Fig. 5) teaches, wherein the switch circuit includes a transistor (switch TFT T3) disposed between the common node (i.e. upper terminal as shown in Fig. 5) and a first gate voltage line (gate-high voltage VGH) and having a gate electrode (i.e. gate connects to QB) connected to the inverting node (Fig. 5).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lee’s shift register structure into Park’s shift register, so as to improve the reliability of initialization (¶ 50, 52).
As to claim 7, Park teaches the display device of claim 1, but does not specifically teach, wherein the switch circuit includes a transistor disposed between the inverting node and a first gate voltage line and having a gate electrode connected to a start signal line.
Lee (Fig. 5) teaches, wherein the switch circuit includes a transistor (switch TFT T5) disposed between the inverting node (i.e. via upper termina as shown in Fig. 5) and a first gate voltage line (gate-high voltage VGH) and having a gate electrode connected to a start signal line (start pulse Vst)(Fig. 5).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lee’s shift register structure into Park’s shift register, so as to improve the reliability of initialization (¶ 50, 52).
As to claim 14, Park teaches the display device but does not specifically teach, wherein the inverting node is charged with a low voltage applied by a turn-on operation of the switching transistor, which is turned on according to a clock signal.
Lee (Fig. 5) teaches, wherein the inverting node (node QB) is charged with a low voltage (gate-low voltage VGL) applied by a turn-on operation of the switching transistor, which is turned on according to a clock signal (shift clock CLK3)(Fig. 5, ¶ 59: i.e. T4 turns on in response to CLK3 to apply VGL to node QB).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lee’s shift register structure into Park’s shift register, so as to improve the reliability of initialization (¶ 50, 52).
As to claim 16, Park teaches the display device of claim 1, but does not specifically teach the switch circuit includes a first to third transistors.
Lee (Fig. 5) teaches, wherein the switch circuit includes:
a first transistor (switch TFT T1) having a gate electrode connected to a start signal line (start pulse VST) and a first electrode (i.e. upper terminal) connected to a second gate voltage line (low-potential voltage VGL)(¶ 59),
a second transistor (switch TFT T2) having a gate electrode connected to a common node clock signal line (CLK4), a first electrode (i.e. upper electrode as shown in Fig. 5) connected to a second electrode (i.e. lower terminal of T1) of the first transistor, and a second electrode (i.e. lower terminal of T2) connected to the common node (Fig. 5: i.e. connects to node Q)(¶ 61), and
a third transistor (switch TFT T3) having a gate electrode connected to the inverting node (i.e. T3 connects to QB via gate electrode), a first electrode (i.e. lower terminal as shown in Fig. 5) connected to a first gate voltage line (high-potential voltage VGH), and a second electrode (i.e. upper terminal as shown in Fig. 5) connected to the common node (¶ 59).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lee’s shift register structure into Park’s shift register, so as to improve the reliability of initialization (¶ 50, 52).
As to claim 17, Park teaches the display device of claim 16, but does not specifically teach the switch circuit includes a fourth, fifth, eighth and ninth transistors.
Lee (Fig. 5) teaches, wherein the switch circuit includes:
a fourth transistor (switch TFT T4) having a gate electrode connected to an inverting node clock signal line (shift clock CLK3), a first electrode (i.e. upper terminal of T4) connected to the second gate voltage line, and a second electrode (i.e. lower terminal of T4) connected to the inverting node (Fig. 5)(¶ 59),
a fifth transistor (switch TFT T5) having a gate electrode connected to the start signal line (i.e. connects to Vst), a first electrode (i.e. lower terminal of T5 as shown in Fig. 5)connected to the first gate voltage line, and a second electrode (i.e. upper terminal) connected to the inverting node (Fig. 5)(¶ 61),
an eighth transistor (switch TFT T8) having a gate electrode connected to the common node, a first electrode (i.e. lower terminal as shown in fig. 5) connected to the first gate voltage line, and a second electrode (i.e. upper terminal) connected to the common node (Fig. 5)(¶ 61), and
a ninth transistor (switch TFT Tqrst) having a gate electrode connected to a reset signal line (initialization pulse QRST), a first electrode (i.e. lower terminal as shown in Fig. 5) connected to the first gate voltage line, and a second electrode (i.e. upper terminal) connected to the common node (Fig. 5)(¶ 35, 59).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lee’s shift register structure into Park’s shift register, so as to improve the reliability of initialization (¶ 50, 52).
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Li et al (PGPUB 2020/0243151 A1).
As to claim 12, Park teaches the display device of claim 1, but does not specifically teach wherein the driving transistor is selected as p-type.
Li (Fig. 1) teaches, wherein the driving transistor is selected as p-type (i.e. driving transistor M13 is a P-type transistor as shown in Fig. 1).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Li’s circuit structures into Park’s display device, so as to avoid leakage current loss and improve image display effect (¶ 69).
As to claim 13, Park teaches the display device of claim 1, but does not specifically teach double-gate transistor.
Li (Fig. 7) teaches, wherein the at least one switching transistor is a double-gate transistor (¶ 89).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Li’s circuit structures into Park’s display device, so as to avoid leakage current loss and improve image display effect (¶ 69).
Response to Arguments
Applicant's arguments filed 1/27/2026 have been fully considered but they are not persuasive.
Applicant has amended claim 1 to recite the new limitation, “wherein a voltage at the common node is input to a gate electrode of the first output transistor and a gate electrode of the third output transistor, and wherein a voltage at the inverting node is input to a gate electrode of the second output transistor and a gate electrode of the fourth output transistor”. Applicant argues that Park prior art does not specifically teach these limitations and discusses the operation of the first and second nodes, the transistors T1, T2, T27 and T28 regarding the sensing period. Examiner respectfully disagrees. On Fig. 5, DIS_ON is shown as high logic during display period DP, which transfer the voltage potential at the nodes N1 and N2 to QN1 and QN2 respectively. In response to the voltage potential at QN1 and QN2, the scan signals and sensing signals are generated by the output buffers. Despite Applicant argues that T12 and T12 are turned off during the sensing period, the claim languages use the comprising language and still reads on the claim language. For further discussion, please refer to the discussion above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623