Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. The Amendment filed on 01/07/2026 has been entered. Claims 1-3 and 20 have been amended. Claims 1-20 remain pending in the application. Objection to the drawings is withdrawn.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 20 is rejected under 35 U.S.C. 103 as unpatentable over YANG (US 20120120035 A1) in view of ZHANG (US 20200082765 A1).
Regarding claim 20, YANG discloses a display panel (e.g., Figs. 1-2), comprising:
a plurality of pixels, comprising a plurality of rows of pixels (Figs. 1-2; pixels PX); and a plurality of gate drive circuits, wherein each gate drive circuit comprises a plurality of shift register units cascade-connected in sequence (Figs. 1-2; e.g., a first gate driving circuit comprising shift register units 411, 413, 415, and 417, and a second gate driving circuit comprising shift register units 412, 414, 416, and 418), and each shift register unit is connected to at least one row of pixels (Figs. 1-2; each shift register unit is connected to one row of pixels PX); and the shift register unit is configured to output a gate control signal to the row of pixels (Fig. 2B; gate signal g), and effective pulses of the gate control signals output by the shift register units connected to adjacent rows of pixels overlap (Fig. 2B; gate signals g);
wherein each one of the plurality of pixels comprises a pixel circuit (Fig. 1; pixel PX) comprising a first functional transistor (Fig. 1; data writing transistor connected to gate line G and data line D), the shift register unit is configured to output a gate control signal to the first functional transistor of the pixel circuit in the row of pixels (Figs. 1-2; each shift register unit outputs a gate signal g to a switching transistor of a pixel PX in a row of pixels), effective pulses of gate control signals output by shift register units connected to adjacent rows of pixels overlap (Fig. 2B; gate signals g applied to adjacent rows of pixels overlap), the shift register units connected to the adjacent rows of pixels are located in different gate drive circuits (Figs. 1-2; e.g., the first shift register unit 411of the first gate driving circuit connected to the first row of pixels, and the second shift register units 412 of the second gate driving circuit connected to the second row of pixels).
YANG dos not disclose wherein the pixel circuit further comprises a first initialization transistor and a drive transistor, a first scanning signal output by an hth-stage shift register unit to the first initialization transistor of the pixel circuit in an hth row of pixels is reused as the gate control signal received by the first functional transistor of the pixel circuit in an (h-2)th row of pixels, h is greater than or equal to 3. However, ZHANG (Figs. 1-2, 4, and 6-8) discloses a display panel, wherein the pixel circuit (Fig. 1; pixel circuit) further comprises a first initialization transistor (initialization transistor M1) and a drive transistor (driving transistor M0), a first scanning signal output by an hth-stage shift register unit to the first initialization transistor of the pixel circuit in an hth row of pixels is reused as the gate control signal received by the first functional transistor of the pixel circuit in an (h-2)th row of pixels, h is greater than or equal to 2 (e.g., Figs. 4 and 6-8; scanning signal output from 2nd shift register is applied as scanning signal Scan1 to initialization transistor M1 of the pixel circuit in 2nd row of pixel and is reused as scanning signal Scan2 to data writing transistor M2 of the pixel circuit in 1st row of pixel. Therefore, ZHANG teaches h=2).
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Since YANG (Fig. 2A is reproduced above for reference) discloses the first gate driving circuit includes odd-numbered shift registers 411, 413, 415, and 417, and the second gate driving circuits includes even-numbered shift registers 412, 414, 416, and 418, the teaching from ZHANG is incorporated to the first gate driving circuit would result in the scanning signal output from 3rd shift register is supplied as a scanning signal to the pixel circuit in 3rd row of pixel and is reused as a scanning signal to of the pixel circuit in 1st row of pixel, which corresponds to h=3; and the teaching from ZHANG is incorporated to the second gate driving circuit would result in the scanning signal output from 4th shift register is supplied as a scanning signal to the pixel circuit in 4th row of pixel and is reused as a scanning signal to of the pixel circuit in 2nd row of pixel, which corresponds to h=4. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHANG to the display device of YANG. The combination/motivation would be to reduce a number of a gate driving circuits to a display panel.
5. Claim 20 is rejected under 35 U.S.C. 103 as unpatentable over KWON (US 20060284815 A1) in view of ZHANG (US 20200082765 A1).
Regarding claim 20, KWON discloses a display panel (e.g., Figs. 3, 6, 10, and 15; display panel), comprising: a plurality of pixels, comprising a plurality of rows of pixels (e.g., Figs. 6, 10, and 15; pixels 116); and a plurality of gate drive circuits, wherein each gate drive circuit comprises a plurality of shift register units cascade-connected in sequence (e.g., Figs. 6-8, 10-12, and 14-16; a first gate driving circuit 250 comprising shift register units 2521-252m and a second gate driving circuit 260 comprising shift register units 2621-262m), and each shift register unit is connected to at least one row of pixels (e.g., Figs. 6-8, 10-12, and 14-16; each shift register unit is connected to one row of pixels 116); and the shift register unit is configured to output a gate control signal to the row of pixels (Figs. 9, 13, 17, and 19; gate signal GL), and effective pulses of the gate control signals output by the shift register units connected to adjacent rows of pixels overlap (Figs. 9, 13, 17, and 19; gate signals GL supplied to adjacent pixel rows are overlapped);
wherein each one of the plurality of pixels comprises a pixel circuit (Figs. 1, 3, 6, and 10; pixel PX) comprising a first functional transistor (Figs. 1, 3, 6, and 10; data writing transistor TFT connected to gate line GL and data line DL), the shift register unit is configured to output a gate control signal to the first functional transistor of the pixel circuit in the row of pixels (Figs. 8 and 12; each shift register unit outputs a gate signal g to a switching transistor TFT of a pixel PX in a row of pixels), effective pulses of gate control signals output by shift register units connected to adjacent rows of pixels overlap (Figs. 9 and 13; gate signals GL applied to adjacent rows of pixels overlap), the shift register units connected to the adjacent rows of pixels are located in different gate drive circuits (Figs. 8-9 and 12-13; e.g., the first shift register unit 2521 of the first gate driving circuit 250 connected to the first row of pixels, and the second shift register units 2621 of the second gate driving circuit 260 connected to the second row of pixels).
KWON dos not disclose wherein the pixel circuit further comprises a first initialization transistor and a drive transistor, a first scanning signal output by an hth-stage shift register unit to the first initialization transistor of the pixel circuit in an hth row of pixels is reused as the gate control signal received by the first functional transistor of the pixel circuit in an (h-2)th row of pixels, h is greater than or equal to 3. However, ZHANG (Figs. 1-2, 4, and 6-8) discloses a display panel, wherein the pixel circuit (Fig. 1; pixel circuit) further comprises a first initialization transistor (initialization transistor M1) and a drive transistor (driving transistor M0), a first scanning signal output by an hth-stage shift register unit to the first initialization transistor of the pixel circuit in an hth row of pixels is reused as the gate control signal received by the first functional transistor of the pixel circuit in an (h-2)th row of pixels, h is greater than or equal to 2 (e.g., Figs. 4 and 6-8; scanning signal output from 2nd shift register is applied as scanning signal Scan1 to initialization transistor M1 of the pixel circuit in 2nd row of pixel and is reused as scanning signal Scan2 to data writing transistor M2 of the pixel circuit in 1st row of pixel. Therefore, ZHANG teaches h=2).
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Since KWON (Fig. 8 is reproduced above for reference) discloses the first gate driving circuit 250 includes odd-numbered shift registers 2521, 2522, 2523, and 252m, and the second gate driving circuits includes even-numbered shift registers 2621, 2622, 2624, and 262m, the teaching from ZHANG is incorporated to the first gate driving circuit would result in the scanning signal output from 3rd shift register is supplied as a scanning signal to the pixel circuit in 3rd row of pixel corresponding to GL3 and is reused as a scanning signal to of the pixel circuit in 1st row of pixel corresponding to GL1, which corresponds to h=3; and the teaching from ZHANG is incorporated to the second gate driving circuit would result in the scanning signal output from 4th shift register is supplied as a scanning signal to the pixel circuit in 4th row of pixel corresponding to GL4 and is reused as a scanning signal to of the pixel circuit in 2nd row of pixel corresponding to GL2, which corresponds to h=4. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHANG to the display device of KOWN. The combination/motivation would be to reduce a number of a gate driving circuits to a display panel.
6. Claims 1-8 are rejected under 35 U.S.C. 103 as unpatentable over LI (US 11727886 B1) in view of KANEYOSHI (US 20100315403 A1) and further in view of ZHANG (US 20200082765 A1).
Regarding claim 1, LI discloses a display panel (e.g., Fig. 1; display device 100), comprising: a plurality of pixels, comprising a plurality of rows of pixels (e.g., Figs. 11-12 and 15-16; pixels 70); a plurality of clock signal line groups, each clock signal line group comprising a first clock signal line and a second clock signal line (e.g., Figs. 11-12 and 15; a first clock signal line CK and a second clock signal line XCK); and a plurality of gate drive circuits corresponding to the plurality of clock signal line groups (e.g., Figs. 11-12 and 15; a first gate driving circuit 30 and a second gate driving circuit 40), wherein each gate drive circuit comprises a plurality of shift register units cascade-connected in sequence (e.g., Figs. 10-12 and 15; a first gate driving circuit 30 comprising shift register units 31 and a second gate driving circuit 40 comprising shift register units 41), each shift register unit is connected to at least one of the plurality of rows of pixels (Figs. 11-12 and 15; each shift register unit is connected to one row of pixels 70), and each shift register unit in each gate drive circuit is connected to the first clock signal line and the second clock signal line in the corresponding clock signal line group (Figs. 11-12 and 15; each shift register unit 31 in the first gate driving circuit 30 connected to a first clock signal line CK1 and a second clock signal line XCK1, each shift register unit 41 in the second gate driving circuit 40 connected to a first clock signal line CK2 and a second clock signal line XCK2); wherein in the clock signal line groups, pulses of first clock signals transmitted on the first clock signal lines are sequentially delayed by a preset duration (e.g., Figs. 13-14; first clock signals CK1 and CK2), and the pulses of the first clock signals transmitted on two adjacent first clock signal lines overlap (e.g., Figs. 13-14; first clock signals CK1 and CK2); and in the clock signal line groups, pulses of second clock signals transmitted on the second clock signal lines are sequentially delayed by the preset duration (e.g., Figs. 13-14; second clock signals XCK1 and XCK2), and the pulses of the second clock signals transmitted on two adjacent second clock signal lines overlap (e.g., Figs. 13-14; second clock signals XCK1 and XCK2).
LI discloses wherein each one of the plurality of pixels comprises a pixel circuit comprising a first functional transistor (e.g., Fig. 16; pixels 70, transistor M2), the shift register unit is configured to output a gate control signal to the first functional transistor of the pixel circuit in the row of pixels (e.g., Figs. 11-12 and 15-16; gate signal S is supplied to transistor M2), the shift register units connected to the adjacent rows of pixels are located in different gate drive circuits (e.g., Figs. 11-12 and 15-16; shift register units 31 and 41 connected to the adjacent rows of pixels 70 are located in gate driving circuits 30 and 40, respectively), and the first functional transistor is a data write transistor (e.g., Fig. 16; pixels 70, data writing transistor M2). LI does not disclose effective pulses of gate control signals output by shift register units connected to adjacent rows of pixels overlap. However, KANEYOSHI discloses a display device, comprising a plurality of gate drive circuits corresponding to a plurality of clock signal line groups, wherein each gate drive circuit comprises a plurality of shift register units cascade-connected in sequence (e.g., Figs. 16-18; a first gate driving circuit comprising shift register units SR0, SR2, and SR4 and clock signal lines CKA and CKB, and a second gate driving circuit comprising shift register units SR1, SR3, and SR5 and clock signal lines CKC and CKD), and effective pulses of gate control signals output by shift register units connected to adjacent rows of pixels overlap (e.g., Fig. 16 and 18; gate signals supplied to adjacent pixel rows are overlapped). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from KANEYOSHI to the display device of LI. The combination/motivation would be to provide a gate driver to a display panel to obtain a uniform image brightness.
LI discloses wherein the pixel circuit (Fig. 16; pixel circuit 70) further comprises a first initialization transistor (initialization transistor M4) and a drive transistor (driving transistor M3), and the first initialization transistor (initialization transistor M4) is configured to initialize a gate of the drive transistor (driving transistor M3) in the same pixel circuit. LI does not disclose a first scanning signal output by an hth-stage shift register unit to the first initialization transistor of the pixel circuit in an hth row of pixels is reused as the gate control signal received by the first functional transistor of the pixel circuit in an (h- 2)th row of pixels, h is greater than or equal to 3. However, ZHANG (Figs. 1-2, 4, and 6-8) discloses a display panel, wherein the pixel circuit (Fig. 1; pixel circuit) further comprises a first initialization transistor (initialization transistor M1) and a drive transistor (driving transistor M0), a first scanning signal output by an hth-stage shift register unit to the first initialization transistor of the pixel circuit in an hth row of pixels is reused as the gate control signal received by the first functional transistor of the pixel circuit in an (h-2)th row of pixels, h is greater than or equal to 2 (e.g., Figs. 4 and 6-8; scanning signal output from 2nd shift register is applied as scanning signal Scan1 to initialization transistor M1 of the pixel circuit in 2nd row of pixel and is reused as scanning signal Scan2 to data writing transistor M2 of the pixel circuit in 1st row of pixel. Therefore, ZHANG teaches h=2).
Since LI (Figs. 11-12 are reproduced above for reference) discloses a first gate driving circuit 30 comprising shift register units 31 and a second gate driving circuit 40 comprising shift register units 41, the teaching from ZHANG is incorporated to the first gate driving circuit 30 would result in the scanning signal output from 3rd shift register is supplied as a scanning signal to the pixel circuit in 3rd row of pixel corresponding to S3 and is reused as a scanning signal to of the pixel circuit in 1st row of pixel corresponding to S1, which corresponds to h=3; and the teaching from ZHANG is incorporated to the second gate driving circuit 40 would result in the scanning signal output from 4th shift register is supplied as a scanning signal to the pixel circuit in 4th row of pixel corresponding to S4 and is reused as a scanning signal to of the pixel circuit in 2nd row of pixel corresponding to S2, which corresponds to h=4. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHANG to the display device of KOWN. The combination/motivation would be to reduce a number of a gate driving circuits to a display panel.
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Regarding claim 2, LI in view of KANEYOSHI and further in view of ZHANG discloses the display panel according to claim 1, LI discloses wherein the first functional transistor is a data write transistor (e.g., Fig. 16; pixels 70, data writing transistor M2).
Regarding claim 3, LI in view of KANEYOSHI and further in view of ZHANG discloses the display panel according to claim 1, ZHANG (Figs. 1-2, 4, and 6-8) discloses wherein the first initialization transistor (initialization transistor M1) is configured to initialize a gate of the drive transistor (driving transistor M0) in the same pixel circuit.
Regarding claim 4, LI in view of KANEYOSHI and further in view of ZHANG discloses the display panel according to claim 2, LI discloses wherein the effective pulse of the gate control signal output by the shift register unit connected to an nth row of pixels and the effective pulse of the gate control signal output by the shift register unit connected to an (n+2)th row of pixels are set at an interval, wherein n is a positive integer; the shift register unit connected to the nth row of pixels and the shift register unit connected to the (n+2)th row of pixels are located in the same gate drive circuit (Figs. 11-15; e.g., shift register unit 31 connected to the first pixel row 11 and shift register unit 31 connected to the third pixel row 11 are located in the same gate drive circuit 30, and the output gate signal S1 and the output gate signal S3 are set at an interval).
Regarding claim 5, LI in view of KANEYOSHI and further in view of ZHANG discloses the display panel according to claim 2, LI discloses wherein the display panel comprises f clock signal line groups and f gate drive circuits, and an (fm+q)th row of pixels is connected to a qth gate drive circuit, wherein m is an integer greater than or equal to 0, and q is a positive integer greater than or equal to 1 and less than or equal to f (e.g., Figs. 11-12 and 15; f=2 clock signal line group, and f=2 gate driving circuits connected to 2m+1 and 2m+2 pixel rows, respectively).
Regarding claim 6, LI in view of KANEYOSHI and further in view of ZHANG discloses the display panel according to claim 2, LI discloses wherein each shift register unit comprises a first clock signal terminal and a second clock signal terminal (e.g., Figs. 11-12 and 15; shift register unit 31 comprises a first clock signal terminal a and a second clock signal terminal b, shift register unit 41 comprises a first clock signal terminal c and a second clock signal terminal d); in the same gate drive circuit, the first clock signal terminal of a (2i+1)th shift register unit is connected to the first clock signal line in the clock signal line group corresponding to the gate drive circuit, and the second clock signal terminal of the (2i+1)th shift register unit is connected to the second clock signal line in the clock signal line group corresponding to the gate drive circuit (e.g., Figs. 11-12 and 15; shift register unit 31 comprises a first clock signal terminal a connected to a first signal line CK1 and a second clock signal terminal b connected to a second clock signal line XCK1); and the first clock signal terminal of a (2i+2)th shift register unit is connected to the second clock signal line in the clock signal line group corresponding to the gate drive circuit, and the second clock signal terminal of the (2i+2)th shift register unit is connected to the first clock signal line in the clock signal line group corresponding to the gate drive circuit, wherein i is an integer greater than or equal to 0 (e.g., Figs. 11-12 and 15; shift register unit 41 comprises a first clock signal terminal c connected to a first signal line CK2 and a second clock signal terminal d connected to a second clock signal line XCK2).
Regarding claim 7, LI in view of KANEYOSHI and further in view of ZHANG discloses the display panel according to claim 2, LI discloses wherein the display panel comprises two clock signal line groups and two gate drive circuits (e.g., Figs. 11-12 and 15; two gate driving circuits 30 and 40, and two clock signal line groups CK1/XCK1 and CK2/XCK2), one of the two gate drive circuits comprises odd- numbered stage shift register units, and the other one of the two gate drive circuits comprises even-numbered stage shift register units (e.g., Figs. 10-12 and 15; a first gate driving circuit 30 comprising shift register units 31 and a second gate driving circuit 40 comprising shift register units 41); and each odd-numbered stage shift register unit is correspondingly connected to an odd- numbered row of pixels, and each even-numbered stage shift register unit is connected to an even-numbered row of pixels (e.g., Figs. 10-12 and 15; a first gate driving circuit 30 connected to an odd- numbered row of pixels and a second gate driving circuit 40 connected to an even- numbered row of pixels). In addition, KANEYOSHI discloses wherein the display panel comprises two clock signal line groups and two gate drive circuits (e.g., Figs. 16-18; two gate driving circuits and and two clock signal line groups), one of the two gate drive circuits comprises odd- numbered stage shift register units, and the other one of the two gate drive circuits comprises even-numbered stage shift register units (e.g., Figs. 16-18; a first gate driving circuit comprising shift register units SR0, SR2, and SR4 and a second gate driving circuit comprising shift register units SR1, SR3, and SR5); and each odd-numbered stage shift register unit is correspondingly connected to an odd- numbered row of pixels, and each even-numbered stage shift register unit is connected to an even-numbered row of pixels (e.g., Figs. 16-18; a first gate driving circuit comprising shift register units SR0, SR2, and SR4 and a second gate driving circuit comprising shift register units SR1, SR3, and SR5 connected to odd-number and even- numbered pixel rows, respectively).
Regarding claim 8, LI in view of KANEYOSHI and further in view of ZHANG discloses the display panel according to claim 2, LI discloses wherein the pulse of the first clock signal transmitted on the first clock signal line in the last clock signal line group is adjacent to and overlaps the pulse of the second clock signal transmitted on the second clock signal line in a first clock signal line group, and the pulse of the second clock signal transmitted on the second clock signal line in the first clock signal line group is delayed by the preset duration compared with the pulse of the first clock signal transmitted on the first clock signal line in the last clock signal line group (e.g., Figs. 13-14; first clock signal CK and second clock signal XCK); or the pulse of the second clock signal transmitted on the second clock signal line in the last clock signal line group is adjacent to and overlaps the pulse of the first clock signal transmitted on the first clock signal line in a first clock signal line group, and the pulse of the first clock signal transmitted on the first clock signal line in the first clock signal line group is delayed by preset duration compared with the pulse of the second clock signal transmitted on the second clock signal line in the last clock signal line group (e.g., Figs. 13-14; first clock signal CK and second clock signal XCK).
7. Claims 9-19 are rejected under 35 U.S.C. 103 as unpatentable over LI (US 11727886 B1) in view of KANEYOSHI (US 20100315403 A1) and ZHANG (US 20200082765 A1) and further in view of ZHAO (US 20230368721 A1).
Regarding claim 9, LI in view of KANEYOSHI and further in view of ZHANG discloses the display panel according to claim 2, LI (e.g., Figs. 11-12 and 15) discloses further comprising a plurality of gate lines (gate lines 11 and 12), and the plurality of pixels comprising a plurality of columns of pixels (columns of pixels 70); wherein the shift register unit is connected to the row of pixels through the gate line transmitting a gate control signal to a pixel circuit in the pixel (shift register unit 31 or 41 transmitting gate signal to pixel circuit 70); LI does not disclose in the column of pixels, the pixels in odd-numbered rows are connected to the same first data line, and the pixels in even-numbered rows are connected to the same second data line. However, ZHAO discloses a display panel (e.g., Figs. 23 and 27), comprising a plurality of first data lines (first data lines data1’), and a plurality of second data lines (second data lines data2’), in the column of pixels, the pixels in odd-numbered rows are connected to the same first data line (first data lines data1’), and the pixels in even-numbered rows are connected to the same second data line (second data lines data2’). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHAO to the display device of LI in view of KANEYOSHI and ZHNAG. The combination/motivation would be to multiplexing circuit to control image signal to a display panel with a reduced signal interference.
Regarding claim 10, LI in view of KANEYOSHI and ZHANG and further in view of HZAO discloses the display panel according to claim 9, ZHAO (e.g., Figs. 23 and 27) discloses the display panel further comprises a time division multiplexing circuit (e.g., Figs. 23 and 27; time division multiplexing circuit comprising a plurality of multiplexing modules 17), wherein the time division multiplexing circuit comprises a plurality of input terminals and a plurality of output terminal groups, one input terminal corresponds to at least one output terminal group, the output terminal group comprises two output terminals respectively connected to the first data line and the second data line (e.g., Figs. 23 and 27; time division multiplexing circuit comprising input terminals and output terminals), and the first data line and the second data line connected to the same output terminal group are connected to the same column of pixels (e.g., Figs. 23 and 27; the first data line data1’ and the second data line data2’); and the time division multiplexing circuit is configured to control each input terminal to transmit a data voltage to each corresponding output terminal in a time division manner (e.g., Figs. 23-24 and 27-28). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHAO to the display device of LI in view of KANEYOSHI and ZHANG for the same reason above.
Regarding claim 11, LI in view of KANEYOSHI and ZHANG and further in view of HZAO discloses the display panel according to claim 10, ZHAO (e.g., Figs. 23 and 27) discloses wherein the time division multiplexing circuit comprises a plurality of time division multiplexing modules, the time division multiplexing module comprises at least one time division multiplexing unit, the time division multiplexing unit is connected to one input terminal and one output terminal group (e.g., Figs. 23 and 27; time division multiplexing circuit comprising a plurality of multiplexing modules 17, each multiplexing module 17 comprising switching units 18 having input and output terminals); and the time division multiplexing circuit further comprises at least one gating signal line group, and one time division multiplexing unit is connected to one gating signal line group (e.g., Figs. 23 and 27; one switching unit 18 is connected to control signal line group CK); the gating signal line group comprises a first gating signal line and a second gating signal line (e.g., Figs. 23 and 27; one control signal line group CK comprises a first gating signal line ck1’ and a second gating signal line ck2’); a gating signal transmitted on the first gating signal line (e.g., Figs. 23 and 27; first gating signal line ck1’) is used to control whether the input terminal is connected to a corresponding first data line (e.g., Figs. 23 and 27; the first data line data1’), and a gating signal (e.g., Figs. 23 and 27; second gating signal line ck2’) transmitted on the second gating signal line is used to control whether the input terminal is connected to a corresponding second data line (e.g., Figs. 23 and 27; the second data line data2’). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHAO to the display device of LI in view of KANEYOSHI and ZHANG for the same reason above.
Regarding claim 12, LI in view of KANEYOSHI and ZHANG and further in view of HZAO discloses the display panel according to claim 11, ZHAO (e.g., Figs. 23 and 27) discloses wherein the time division multiplexing module comprises at least two time division multiplexing units (e.g., Figs. 23 and 27; each multiplexing module 17 comprising at least two switching units 18), different time division multiplexing units in the same time division multiplexing module are connected to different gating signal line groups and the same input terminal (e.g., Figs. 23 and 27; two different switching units 18 connected to two control signal line groups CK1 and CK2, respectively, two different switching units 18 connected to same input terminal S), and the columns of pixels (e.g., Figs. 23 and 27; columns of pixels) corresponding to the at least two time division multiplexing units (e.g., Figs. 23 and 27; two switching units 18) in the same time division multiplexing module (e.g., Figs. 23 and 27; multiplexing module 17) are arranged in sequence (e.g., Figs. 23 and 27). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHAO to the display device of LI in view of KANEYOSHI and ZHANG for the same reason above.
Regarding claim 13, LI in view of KANEYOSHI and ZHANG and further in view of HZAO discloses the display panel according to claim 11, ZHAO discloses wherein during a process of writing data voltages corresponding to two adjacent rows of pixels into the first data line and the second data line (e.g., Figs. 23-24 and 27-28), pulses of the gating signals transmitted on the first gating signal lines in each gating signal line group are adjacent (e.g., Figs. 24 and 28; timing diagram), and pulses of the gating signals transmitted on the second gating signal lines in each gating signal line group are adjacent (e.g., Figs. 24 and 28; timing diagram). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHAO to the display device of LI in view of KANEYOSHI and ZHANG for the same reason above.
Regarding claim 14, LI in view of KANEYOSHI and ZHANG and further in view of HZAO discloses the display panel according to claim 13, ZHAO discloses wherein in the same time division multiplexing module (e.g., Figs. 23-24 and 27-28), the pulse of the gating signal transmitted on the first gating signal line connected to the last time division multiplexing unit is adjacent to the pulse of the gating signal transmitted on the second gating signal line connected to a first time division multiplexing unit (e.g., Figs. 24 and 28; timing diagram). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHAO to the display device of LI in view of KANEYOSHI and ZHANG for the same reason above.
Regarding claim 15, LI in view of KANEYOSHI and ZHANG and further in view of HZAO discloses the display panel according to claim 11, ZHAO (e.g., Figs. 23-24 and 27-28) discloses wherein an end moment of the effective pulse of the gate control signal received by the data write transistor of the pixel circuit in an nth row of pixels coincides with or is earlier than a first moment at which a kth data line and a corresponding input terminal begin to connect to transmit a data signal corresponding to an (n+2)th row of pixels, wherein n is a positive integer; and n is an odd number, the kth data line is the first data line; or n is an even number, the kth data line is the second data line (e.g., Figs. 24 and 28; timing diagram of control signal ck and scanning signal, e.g., gate signal S2m-1 applied to 3rd row of pixels is earlier than the control signal ck1’ applied to control data signal transmitting to the 1st data line). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHAO to the display device of LI in view of KANEYOSHI and ZHANG for the same reason above.
Regarding claim 16, LI in view of KANEYOSHI and ZHANG and further in view of HZAO discloses the display panel according to claim 15, ZHAO (e.g., Figs. 23-24 and 27-28) discloses wherein a time period during which an eth data line and a corresponding input terminal connect to transmit a data signal corresponding to an (n+1 )th row of pixels is within a time period during which the gate control signal received by the data write transistor of the pixel circuit in the nth row of pixels has the effective pulse; and n is an odd number, the eth data line is the second data line; or n is an even number, the eth data line is the first data line (e.g., Figs. 24 and 28; timing diagram of control signal ck applied to control data signal transmitting to the data line and scanning signal applied to the pixel row). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHAO to the display device of LI in view of KANEYOSHI and ZHANG for the same reason above.
Regarding claim 17, LI in view of KANEYOSHI and ZHANG and further in view of HZAO discloses the display panel according to claim 16, ZHAO (e.g., Figs. 23-24 and 27-28) discloses wherein the time period during which the gate control signal received by the data write transistor of the pixel circuit in the nth row of pixels has the effective pulse overlaps a first time period during which the kth data line and the corresponding input terminal connect to transmit a data signal corresponding to an nth row of pixels (e.g., Figs. 24 and 28; timing diagram of control signal ck applied to control data signal transmitting to the kth data line and scanning signal applied to the nth pixel row). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHAO to the display device of LI in view of KANEYOSHI and ZHANG for the same reason above.
Regarding claim 18, LI in view of KANEYOSHI and ZHANG and further in view of HZAO discloses the display panel according to claim 17, ZHAO (e.g., Figs. 23-24 and 27-28) discloses wherein the effective pulse of the gate control signal received by the data write transistor of the pixel circuit in the nth row of pixels overlaps a first effective pulse of the last kth gating signal line, the first effective pulse of the last kth gating signal line is located within the first time period (e.g., Figs. 24 and 28; timing diagram of control signal ck applied to control data signal transmitting to the data line and scanning signal applied to the pixel row), wherein the last kth gating signal line is the kth gating signal line connected to the last time division multiplexing unit in the same time division multiplexing module (e.g., Figs. 23 and 27; one multiplexing module 17 comprising switching units 18 and control signal lines CK1 and CK2). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHAO to the display device of LI in view of KANEYOSHI and ZHNAG for the same reason above.
Regarding claim 19, LI in view of KANEYOSHI and ZHANG and further in view of HZAO discloses the display panel according to claim 18, ZHAO (e.g., Figs. 23-24 and 27-28) discloses wherein a start moment of the effective pulse of the gate control signal received by the data write transistor of the pixel circuit in the nth row of pixels is later than or coincides with a start moment of the first effective pulse of the last kth gating signal line (e.g., Figs. 23 and 27; one multiplexing module 17 comprising switching units 18 and control signal lines CK1 and CK2). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHAO to the display device of LI in view of KANEYOSHI and ZHANG for the same reason above.
Response to Arguments
8. Applicant's arguments filed 01/07/2025 have been fully considered but they are not persuasive.
9. Applicant has amended claims 1 and 20 by incorporating with some limitations of original claims 2 and 3. Applicant further argues that the cited references do not disclose the limitations “wherein the pixel circuit further comprises a first initialization transistor and a drive transistor, a first scanning signal output by an hth-stage shift register unit to the first initialization transistor of the pixel circuit in an hth row of pixels is reused as the gate control signal received by the first functional transistor of the pixel circuit in an (h-2)th row of pixels, h is greater than or equal to 3” recited in amended claims 1 and 20.
The examiner respectfully disagrees with applicant’s arguments. ZHANG (Figs. 1-2, 4, and 6-8) discloses a display panel, wherein the pixel circuit (Fig. 1) comprises a first initialization transistor M1 and a drive transistor M0. ZHANG (Figs. Figs. 4 and 6-8) further discloses a scanning signal output from 2nd shift register is applied as a scanning signal Scan1 to the initialization transistor M1 of the pixel circuit in 2nd row of pixel and is reused as a scanning signal Scan2 to the data writing transistor M2 of the pixel circuit in 1st row of pixel. Therefore, ZHANG teaches h=2.
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Now taking YANG as a reference. YANG (Fig. 2A is reproduced above for reference) discloses the first gate driving circuit includes odd-numbered shift registers 411, 413, 415, and 417, and the second gate driving circuits includes even-numbered shift registers 412, 414, 416, and 418, the teaching from ZHANG is incorporated to the first gate driving circuit would result in the scanning signal output from 3rd shift register is supplied as a scanning signal to the pixel circuit in 3rd row of pixel and is reused as a scanning signal to of the pixel circuit in 1st row of pixel, which corresponds to h=3; and the teaching from ZHANG is incorporated to the second gate driving circuit would result in the scanning signal output from 4th shift register is supplied as a scanning signal to the pixel circuit in 4th row of pixel and is reused as a scanning signal to of the pixel circuit in 2nd row of pixel, which corresponds to h=4.
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Taking KWON as another reference. KWON (Fig. 8 is reproduced above for reference) discloses the first gate driving circuit 250 includes odd-numbered shift registers 2521, 2522, 2523, and 252m, and the second gate driving circuits includes even-numbered shift registers 2621, 2622, 2624, and 262m, the teaching from ZHANG is incorporated to the first gate driving circuit would result in the scanning signal output from 3rd shift register is supplied as a scanning signal to the pixel circuit in 3rd row of pixel corresponding to GL3 and is reused as a scanning signal to of the pixel circuit in 1st row of pixel corresponding to GL1, which corresponds to h=3; and the teaching from ZHANG is incorporated to the second gate driving circuit would result in the scanning signal output from 4th shift register is supplied as a scanning signal to the pixel circuit in 4th row of pixel corresponding to GL4 and is reused as a scanning signal to of the pixel circuit in 2nd row of pixel corresponding to GL2, which corresponds to h=4.
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As a further example, LI (Figs. 11-12 are reproduced above for reference) discloses a first gate driving circuit 30 comprising shift register units 31 and a second gate driving circuit 40 comprising shift register units 41, which are similar to those disclosed by YANG and KWON. The teaching from ZHANG is incorporated to the first gate driving circuit 30 would result in the scanning signal output from 3rd shift register is supplied as a scanning signal to the pixel circuit in 3rd row of pixel corresponding to S3 and is reused as a scanning signal to of the pixel circuit in 1st row of pixel corresponding to S1, which corresponds to h=3; and the teaching from ZHANG is incorporated to the second gate driving circuit 40 would result in the scanning signal output from 4th shift register is supplied as a scanning signal to the pixel circuit in 4th row of pixel corresponding to S4 and is reused as a scanning signal to of the pixel circuit in 2nd row of pixel corresponding to S2, which corresponds to h=4.
Therefore, the combinations of YANG, KWON, LI with ZHAO teach the limitations “wherein the pixel circuit further comprises a first initialization transistor and a drive transistor, a first scanning signal output by an hth-stage shift register unit to the first initialization transistor of the pixel circuit in an hth row of pixels is reused as the gate control signal received by the first functional transistor of the pixel circuit in an (h-2)th row of pixels, h is greater than or equal to 3” recited in amended claims 1 and 20.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
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