Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 8-16 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/10/26
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7, 17 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al., US 20210335233 A1 (hereinafter “Chen”).
Regarding claim 1, Chen discloses a display panel (fig. 6, paragraphs 3-5, 71, 77, display panel with reduced wiring cost), comprising:
a plurality of pixel circuits and a plurality of light-emitting element groups, one light-emitting element group comprising N light-emitting elements (paragraph 65, “each pixel compensation circuit 011 is configured to be connected to a light-emitting unit group 02 in operation, each light-emitting unit group 02 may include M light-emitting units 021 located in the same column, and M is an integer greater than 1. For example, in the pixel circuit shown in FIG. 1, each pixel compensation circuit 011 may be connected to two light-emitting units 021 located in the same column, i.e., M=2.”), and all first electrodes of the N light-emitting elements electrically connected to an output terminal of the same pixel circuit (fig. 4, output P2 of pixel circuit connected to first electrode of each light emitting element 021, see annotated fig. 4);
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wherein the N light-emitting elements are located in different rows and emit light in different time periods within one frame, and N is an integer greater than 1 (fig. 6, paragraph 123, “Because a light-emitting unit group connected to each pixel compensation circuit of the pixel circuit includes two light-emitting units, i.e., M=2, the time when the pixel circuit performs scanning of one frame 1F on the light-emitting units in the display panel may be divided into two driving sub-frames SF1 and SF2 as shown in FIG. 6. Referring to FIG. 6, during the first driving sub-frame SF1, the pixel circuit may drive the light-emitting units of the odd-numbered rows in the display panel to emit light row by row, that is, during the first driving sub-frame SF1, the pixel circuit may sequentially drive the light-emitting units of the first row, the third row, the fifth row to the last odd-numbered row in the display panel to emit light; during the second driving sub-frame SF2, the pixel circuit may drive the light-emitting units of the even-numbered rows in the display panel to emit light row by row, that is, during the second driving sub-frame SF2, the pixel circuit may sequentially drive the light-emitting units of the second row, the fourth row, the sixth row, and the last even-numbered row in the display panel to emit light”).
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Regarding claim 2, Chen discloses the display panel according to claim 1, wherein a plurality of second electrodes of the N light-emitting elements in the same light-emitting element group are connected to different power lines (see annotated fig. 4 below, different light emitting element in .
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Regarding claim 3, Chen discloses the display panel according to claim 1, wherein a working process of the display panel within one frame comprises M subframes, one of the N light-emitting elements emits light in one subframe, and the N light-emitting elements sequentially emit light respectively in the M subframes, wherein M=N. (paragraph 65: “each pixel compensation circuit 011 is configured to be connected to a light-emitting unit group 02 in operation, each light-emitting unit group 02 may include M light-emitting units 021 located in the same column, and M is an integer greater than 1. For example, in the pixel circuit shown in FIG. 1, each pixel compensation circuit 011 may be connected to two light-emitting units 021 located in the same column, i.e., M=2”, paragraph 70: “the pixel circuit adopts two driving sub-frames (i.e., M=2) when driving the light-emitting unit to emit light, during a certain driving stage of the first driving sub-frame, in the light-emitting control signal terminal group 03 corresponding to the driving stage, the potential of the light-emitting control signal provided by the first light-emitting control signal terminal EM may be an valid potential, that is, the first light-emitting control signal terminal EM is the target light-emitting control signal terminal. At this time, the light-emitting unit 021 corresponding to the first light-emitting control signal terminal EM emits light. During the driving stage of the second driving sub-frame, in the light-emitting control signal terminal group 03 corresponding to the driving stage, the potential of the light-emitting control signal provided by the second light-emitting control signal terminal EM may be an valid potential, that is, the second light-emitting control signal terminal EM is the target light-emitting control signal terminal. At this time, the light-emitting unit 021 corresponding to the second light-emitting control signal terminal EM emits light.”, that is both claimed M and N are 2)
Regarding claim 4, Chen discloses the display panel according to claim 3, wherein one light-emitting element group comprises two light-emitting elements, wherein the two light-emitting elements are located in two adjacent rows and the same column, or the two light-emitting elements are located in two adjacent rows and two adjacent columns. (paragraphs 63, 64, 65 “the pixel circuit may include a plurality of pixel compensation circuit groups 01 arranged in an array, each pixel compensation circuit group 01 may include K rows of pixel compensation circuits 011, K is an integer greater than 1, and each row of pixel compensation circuits includes at least one pixel compensation circuit 011. For example, in the pixel circuit shown in FIG. 1, each pixel compensation circuit group 01 includes two rows of pixel compensation circuits 011, i.e., K=2.”, “each pixel compensation circuit 011 is configured to be connected to a light-emitting unit group 02 in operation, each light-emitting unit group 02 may include M light-emitting units 021 located in the same column, and M is an integer greater than 1. For example, in the pixel circuit shown in FIG. 1, each pixel compensation circuit 011 may be connected to two light-emitting units 021 located in the same column, i.e., M=2.” paragraphs 76, 79, 81: “Referring to FIGS. 1 and 2, assuming that each pixel compensation circuit 011 is connected to two light-emitting units 021 located in the same column, one light-emitting control signal terminal EM can control two rows of light-emitting units in some embodiments of the present disclosure”; “each pixel compensation circuit group 01 may include adjacent K rows of pixel compensation circuits. By taking the pixel compensation circuits 01 in adjacent rows as a group, it is possible to prevent the light-emitting control signal terminal EM from crossing the rows to be connected to the pixel compensation circuit 01, so that the wiring costs can be reduced.” “In some embodiments of the present disclosure, the mth light-emitting control signal terminal of the M light-emitting control signal terminals connected to each pixel compensation circuit corresponds to the mth light-emitting unit of the M light-emitting units connected thereto, and m is a positive integer not greater than M. By making the light-emitting control signal terminal EM connected to each pixel compensation circuit 011 correspond to the light-emitting unit 021 connected to the pixel compensation circuit 011, each light-emitting control signal terminal group 03 can orderly drive, through the pixel compensation circuit 011, each row of the light-emitting units 021 at an equal row interval to emit light.”)
Regarding claim 5, Chen discloses the display panel according to claim 4, wherein one subframe is used as one time period, and the M subframes comprise a first time period, a second time period, . . . , and an Mth time period; and in the case of M=2, the two light-emitting elements located in two adjacent rows and the same column emit light of the same color, wherein within the first time period, the light-emitting element located in an odd-numbered row emits light; and within the second time period, the light-emitting element located in an even-numbered row emits light. (fig. 6, paragraph 123, “Because a light-emitting unit group connected to each pixel compensation circuit of the pixel circuit includes two light-emitting units, i.e., M=2, the time when the pixel circuit performs scanning of one frame 1F on the light-emitting units in the display panel may be divided into two driving sub-frames SF1 and SF2 as shown in FIG. 6. Referring to FIG. 6, during the first driving sub-frame SF1, the pixel circuit may drive the light-emitting units of the odd-numbered rows in the display panel to emit light row by row, that is, during the first driving sub-frame SF1, the pixel circuit may sequentially drive the light-emitting units of the first row, the third row, the fifth row to the last odd-numbered row in the display panel to emit light; during the second driving sub-frame SF2, the pixel circuit may drive the light-emitting units of the even-numbered rows in the display panel to emit light row by row, that is, during the second driving sub-frame SF2, the pixel circuit may sequentially drive the light-emitting units of the second row, the fourth row, the sixth row, and the last even-numbered row in the display panel to emit light”)
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Regarding claim 7, Chen discloses the display panel according to claim 4, wherein one subframe is used as one time period, and the M subframes comprise a first time period, a second time period, . . . , and an Mth time period; and in the case of M=2, (paragraphs 123, “a light-emitting unit group connected to each pixel compensation circuit of the pixel circuit includes two light-emitting units, i.e., M=2, the time when the pixel circuit performs scanning of one frame 1F on the light-emitting units in the display panel may be divided into two driving sub-frames SF1 and SF2 as shown in FIG. 6”), the two light-emitting elements located in two adjacent rows and two adjacent columns emit light of different colors (see annotated fig. 6 below, light emitting element located in two adjacent row and two adjacent column, that is, any two “diagonally adjacent” light emitting elements, are of different colors),
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wherein within the first time period, the light-emitting element located in an odd-numbered row emits light; and within the second time period, the light-emitting element located in an even-numbered row emits light (paragraph 123, “Referring to FIG. 6, during the first driving sub-frame SF1, the pixel circuit may drive the light-emitting units of the odd-numbered rows in the display panel to emit light row by row, that is, during the first driving sub-frame SF1, the pixel circuit may sequentially drive the light-emitting units of the first row, the third row, the fifth row to the last odd-numbered row in the display panel to emit light; during the second driving sub-frame SF2, the pixel circuit may drive the light-emitting units of the even-numbered rows in the display panel to emit light row by row, that is, during the second driving sub-frame SF2, the pixel circuit may sequentially drive the light-emitting units of the second row, the fourth row, the sixth row, and the last even-numbered row in the display panel to emit light”).
Regarding claim 17, this is a display method claim counterpart of display device claim 1, both reciting substantially similar subject matter. Accordingly, claim 17 is rejected for the same reasons as claim 1.
Regarding claim 18, this is a display method claim counterpart of display device claim 5, both reciting substantially similar subject matter. Accordingly, claim 18 is rejected for the same reasons as claim 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, as applied rejection of claim 4 above, and in further view of Lee et al., US 20150041790 A1 (hereinafter “Lee”).
Regarding claim 6, Chen discloses the display panel according to claim 4, wherein one subframe is used as one time period, and the M subframes comprise a first time period, a second time period, . . . , and an Mth time period; and in the case of M=2, the two light-emitting elements located in two adjacent rows and the same column emit light of the same color (paragraph 67, 70, 78, 123, “a light-emitting unit group connected to each pixel compensation circuit of the pixel circuit includes two light-emitting units, i.e., M=2, the time when the pixel circuit performs scanning of one frame 1F on the light-emitting units in the display panel may be divided into two driving sub-frames SF1 and SF2”).
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Chen does not disclose in particular:
wherein within the first time period, the light-emitting element located in both an odd-numbered row and an odd-numbered column emits light, and the light-emitting element located in both an even-numbered row and an even-numbered column emits light; and within the second time period, the light-emitting element located in both an odd-numbered row and an even-numbered column emits light, and the light-emitting element located in both an even-numbered row and an odd-numbered column emits light.
In other words, Chen discloses the emission pattern of “row inversion” (every other row of light emitting element emit light in sub-frame) instead of “dot inversion” (every diagonally disposed light emitting element emit light in sub-frame), in comparison of the disclosure of pending application as annotated below:
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However, the “dot inversion” pattern is simply a variation from “row inversion” emission pattern with positional offset of emitters turned on between adjacent columns, both emission pattern may be implemented with pixel circuit disclosed by Chen, wherein one pixel circuit controls emission of two light emitting element by turning on one of two light emitting elements in one of two sub-frames. In similar field of endeavor, Lee discloses such “zigzag” emission pattern wherein during a first sub-frame pixels diagonally disposed adjacent to each other are configured to emit light, while during a second sub-frame the other pixel in a pair of adjacent pixel are configured to emit light, resulting in a “dot inversion” emission pattern.
(Lee, paragraph 103: “Referring to FIGS. 8A to 8C, in a display unit 100 of an organic light emitting display device, the first pixel groups 110 may emit light in the zigzag shape as illustrated in FIG. 8B in the first field because the first emission signal is provided from the emission driver through the first emission control-lines 410. The second pixel groups 120 may emit light in the zigzag shape as illustrated in FIG. 8C in the second field because the second emission signal is provided from the emission driver through the second emission control-lines 420. Although driving frequencies are different according to a kind of a display device, generally, a time for driving one frame is very short. Thus, the first pixel groups 110 and the second pixel groups 120 which emit light in the zigzag shape may be recognized that all pixels emit light in one frame as illustrated in FIG. 8A although the organic light emitting display device is driven by dividing one frame into the first field and the second field as illustrate in FIGS. 8B and 8C”)
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It would have been obvious to one of ordinary skill in the art at the time of filing, to incorporate the concept of “zigzag” emission pattern, such as disclosed by Lee, into the device of Chen, such that the emission states of pixel groups of in adjacent columns are offset from each other, to constitute wherein within the first time period, the light-emitting element located in both an odd-numbered row and an odd-numbered column emits light, and the light-emitting element located in both an even-numbered row and an even-numbered column emits light; and within the second time period, the light-emitting element located in both an odd-numbered row and an even-numbered column emits light, and the light-emitting element located in both an even-numbered row and an odd-numbered column emits light,
such is replacement of a known element (row inversion emission pattern) with another known element (dot inversion emission pattern) to create a predictable result, the result would have been predictable and function of allowing all pixels to emit light in one complete frame by having different pixels emit light during different sub-frames would have been the same.
Regarding claim 19, this is a display method claim counterpart of display device claim 6, both reciting substantially similar subject matter. Accordingly, claim 19 is rejected for the same reasons as claim 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEIJIE SHEN whose telephone number is (571)272-5522. The examiner can normally be reached Monday - Friday 10AM - 6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 5712727603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PEIJIE SHEN/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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