Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keller(US 2010/0235670) and Mannava(US 2020/0133865).
Regarding claims 1, 19 and 20, Keller discloses an apparatus comprising: a power domain comprising a cache, wherein the power domain is configured to transition between power states, at least one of the power states being a power-saving state(Paragraph 23, The processors 12A-12B may each include a data cache, and may also be configured to enter a low power state); receiving circuitry configured to receive, from an external agent, cache maintenance requests targeting the cache, in which: while the power domain is in the power-saving state, the receiving circuitry is configured to: buffer, in request buffer circuitry configured to operate outside of the power domain, one or more cache maintenance requests targeting the cache of the power domain(Paragraph 40, other external circuitry may be configured to queue one or more invalidating snoops for presentation to the processor 12A upon transition to the higher power state).
Keller does not specifically disclose return, before the power domain is caused to transition out of the power-saving state, an indication to the external agent that the one or more cache maintenance requests are guaranteed to be completed. However, Mannava discloses a master device issuing a cache maintenance request to an intermediate device, wherein the intermediate device sends an ack to the master indicative that the intermediate device has taken on the responsibility froe completion of the cache maintenance operation, wherein the acknowledgment releases the master from the responsibility of the cache maintenance request(Paragraph 18) and cease storage of request details of the cache maintenance request(Paragraph 20). It would have been obvious to one of ordinary skill in the art and before the effective filing date to combine the teachings of Keller and Mannava to return, before the power domain is caused to transition out of the power-saving state, an indication to the external agent that the one or more cache maintenance requests are guaranteed to be completed. The motivation to do so would be to not be burdened by requesting agent’s full administration until completion, where this responsibility is taken on by the intermediate device in the interconnect system(Mannava: Paragraph 19).
Regarding claim 2, Keller and Mannava disclose the apparatus of claim 1, wherein data stored in the cache is retained while the power domain is in the power-saving state(Keller: Paragraph 40, each valid cache block may be changed to shared state in the data cache 34. External circuitry may be configured to queue one or more invalidating snoops for presentation to the processor 12A upon transition to the higher power state).
Regarding claim 3, Keller and Mannava disclose the apparatus of claim 1, wherein the receiving circuitry and request buffer circuitry are configured to operate in a powered state at least while the power domain is in the power-saving state(Keller: Paragraph 40, External circuitry may be configured to queue one or more invalidating snoops for presentation to the processor 12A upon transition to the higher power state).
Regarding claim 4, Keller and Mannava disclose the apparatus of claim 1, wherein the receiving circuitry is responsive to the power domain transitioning out of the power-saving state, to forward the one or more cache maintenance requests to be performed by the cache(Keller: Paragraph 40, each valid cache block may be changed to shared state in the data cache 34. External circuitry may be configured to queue one or more invalidating snoops for presentation to the processor 12A upon transition to the higher power state).
Regarding claim 5, Keller and Mannava disclose the apparatus of claim 4, comprising request control circuitry configured to stall at least one data processing operation from being performed in the power domain until the one or more cache maintenance requests have been performed((Mannava: Paragraph 26, Similarly the master can ensure that cache maintenance operations associated with a state of the master device having a particular translation table configuration (e.g. a virtual to physical address translation table configuration) are complete before a state change (e.g. to allow a new virtual machine to begin operation) occurs. The master device can also ensure that a barrier instruction has its desired effect in the wider interconnect system, by associating certain cache maintenance operations with the barrier instruction. Indeed, any set of instructions may be associated with a cache maintenance operation such that it is ensured that the cache maintenance operation is complete before other instructions are then executed).
Regarding claim 6, Keller and Mannava disclose the apparatus of claim 5, wherein the at least one data processing operation comprises a memory access operation(Mannava: Paragraph 26, Similarly the master can ensure that cache maintenance operations associated with a state of the master device having a particular translation table configuration (e.g. a virtual to physical address translation table configuration) are complete before a state change (e.g. to allow a new virtual machine to begin operation) occurs. The master device can also ensure that a barrier instruction has its desired effect in the wider interconnect system, by associating certain cache maintenance operations with the barrier instruction. Indeed, any set of instructions may be associated with a cache maintenance operation such that it is ensured that the cache maintenance operation is complete before other instructions are then executed).
Regarding claim 7, Keller and Mannava disclose the apparatus of claim 1, wherein the receiving circuitry is configured to cause the power domain to transition out of the power-saving state in response to a number of cache maintenance requests in the request buffer circuitry reaching a predetermined threshold(Keller: Paragraph 40, the processor 12A may be transitioned to the higher power state temporarily if the queue fills).
Regarding claim 8, Keller and Mannava disclose the apparatus of claim 7, wherein the receiving circuitry is configured to determine that the number of cache maintenance requests in the request buffer circuitry has reached the predetermined threshold in response to an overflow in the request buffer circuitry(Keller: Paragraph 40, the processor 12A may be transitioned to the higher power state temporarily if the queue fills).
Regarding claim 9, Keller and Mannava disclose the apparatus of claim 1, wherein the one or more cache maintenance requests comprise invalidation requests; and the receiving circuitry is responsive to a number of cache maintenance requests in the request buffer circuitry reaching a predetermined threshold to cause all data stored in the cache to be invalidated after the power domain transitions from the power-saving state(Keller: Paragraph 40, external circuitry may detect a snoop invalidate (or a snoop hit invalidate) and may cause the entire data cache 34 to be invalidated when the processor 12A transitions to a higher power state).
Regarding claim 10, Keller and Mannava disclose the apparatus of claim 9, wherein the receiving circuitry is configured to determine that the number of cache maintenance requests in the request buffer circuitry has reached the predetermined threshold in response to an overflow in the request buffer circuitry(Keller: Paragraph 40, the processor 12A may be transitioned to the higher power state temporarily if the queue fills).
Regarding claim 11, Keller and Mannava disclose the apparatus of claim 1, wherein the request buffer circuitry is configured to record, for a given cache maintenance request, at least one invalidation condition identifier identifying one or more invalidation conditions which when satisfied by a given entry in the cache indicates that the given entry is to be invalidated during performance of the given cache maintenance request(Keller: Paragraph 40: external circuitry may be configured to queue one or more invalidating snoops for presentation to the processor 12A upon transition to the higher power state, and the processor 12A may be transitioned to the higher power state temporarily if the queue fills. In yet another alternative, the L2 cache 14 may be configured to tag cache blocks that were flushed from the data cache 34 but retained in shared state and may detect snoop invalidations to such cache blocks for queuing or to transition to the processor 12A to a higher power state for servicing the snoop. In still another alternative, the L2 cache 14 or other external circuitry may detect a snoop invalidate (or a snoop hit invalidate) and may cause the entire data cache 34 to be invalidated when the processor 12A transitions to a higher power state).
Regarding claim 12, Keller and Mannava disclose the apparatus of claim 11, wherein the one or more invalidation conditions comprises a condition satisfied by the given entry when the given entry is associated with a virtual machine identifier or an address space identifier specified by the given cache maintenance request(Mannava: Paragraph 26, Similarly the master can ensure that cache maintenance operations associated with a state of the master device having a particular translation table configuration (e.g. a virtual to physical address translation table configuration) are complete before a state change (e.g. to allow a new virtual machine to begin operation) occurs. The master device can also ensure that a barrier instruction has its desired effect in the wider interconnect system, by associating certain cache maintenance operations with the barrier instruction. Indeed, any set of instructions may be associated with a cache maintenance operation such that it is ensured that the cache maintenance operation is complete before other instructions are then executed).
Regarding claim 13, Keller and Mannava disclose the apparatus of claim 11, wherein the one or more invalidation conditions comprises a condition satisfied by the given entry when the given entry is associated with a memory address corresponding to a memory address or memory address range specified by the given cache maintenance request(Mannava: Paragraph 26, Similarly the master can ensure that cache maintenance operations associated with a state of the master device having a particular translation table configuration (e.g. a virtual to physical address translation table configuration) are complete before a state change (e.g. to allow a new virtual machine to begin operation) occurs. The master device can also ensure that a barrier instruction has its desired effect in the wider interconnect system, by associating certain cache maintenance operations with the barrier instruction. Indeed, any set of instructions may be associated with a cache maintenance operation such that it is ensured that the cache maintenance operation is complete before other instructions are then executed).
Regarding claim 14, Keller and Mannava disclose the apparatus of claim 1, wherein the cache is an address translation cache configured to store address translation data based on translation table structures obtained from memory(Mannava: Paragraph 26, Similarly the master can ensure that cache maintenance operations associated with a state of the master device having a particular translation table configuration (e.g. a virtual to physical address translation table configuration) are complete before a state change (e.g. to allow a new virtual machine to begin operation) occurs. The master device can also ensure that a barrier instruction has its desired effect in the wider interconnect system, by associating certain cache maintenance operations with the barrier instruction. Indeed, any set of instructions may be associated with a cache maintenance operation such that it is ensured that the cache maintenance operation is complete before other instructions are then executed).
Regarding claim 15, Keller and Mannava disclose the apparatus of claim 1, wherein the cache comprises an instruction cache configured to store data processing instructions(Mannava: Paragraph 26, Similarly the master can ensure that cache maintenance operations associated with a state of the master device having a particular translation table configuration (e.g. a virtual to physical address translation table configuration) are complete before a state change (e.g. to allow a new virtual machine to begin operation) occurs. The master device can also ensure that a barrier instruction has its desired effect in the wider interconnect system, by associating certain cache maintenance operations with the barrier instruction. Indeed, any set of instructions may be associated with a cache maintenance operation such that it is ensured that the cache maintenance operation is complete before other instructions are then executed).
Regarding claim 16, Keller and Mannava disclose the apparatus of claim 1, wherein the power domain further comprises processing circuitry configured to access the cache for executing data processing instructions(Keller: Paragraph 23, The processors 12A-12B may each include a data cache, and may also be configured to enter a low power state);
Regarding claim 17, Keller and Mannava disclose a system comprising: the apparatus of claim 1, implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board(Keller: Paragraph 18, In one embodiment, the system 10 may be integrated onto a single integrated circuit chip (e.g. a system on a chip configuration). In other embodiments, the system 10 may comprise two or more integrated circuit components coupled together via a circuit board. Any level of integration may be implemented in various embodiments).
Regarding claim 18, Keller and Mannava disclose the chip-containing product comprising the system of claim 17, wherein the system is assembled on a further board with at least one other product component(Keller: Paragraph 18, In one embodiment, the system 10 may be integrated onto a single integrated circuit chip (e.g. a system on a chip configuration). In other embodiments, the system 10 may comprise two or more integrated circuit components coupled together via a circuit board. Any level of integration may be implemented in various embodiments).
Conclusion
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/NIMESH G PATEL/ Primary Examiner, Art Unit 2185
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