Prosecution Insights
Last updated: July 17, 2026
Application No. 19/074,796

METHOD FOR MITIGATION OF DROOP TIMING ERRORS INCLUDING A DROOP DETECTOR AND DUAL MODE LOGIC

Non-Final OA §102§103
Filed
Mar 10, 2025
Priority
Nov 22, 2020 — provisional 63/116,856 +1 more
Examiner
KIM, SEOKJIN
Art Unit
Tech Center
Assignee
BAR ILAN UNIVERSITY
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
430 granted / 553 resolved
+17.8% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
19 currently pending
Career history
579
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
75.3%
+35.3% vs TC avg
§102
13.2%
-26.8% vs TC avg
§112
8.1%
-31.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 553 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-4, 6 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by English (US 10,742,202 B1). Regarding claim 1, English teaches a circuit comprising: at least one comparator (Fig. 1) that autozeroes in a first cycle (Fig. 2, 201), and an offset (col. 4, lines 21~35, a difference between the first offset and the second offset is stored as a trip point of the comparator) which is programmed into said at least one comparator in a second cycle (Fig. 2, 202), wherein said offset determines a signal threshold to be detected (col. 4, lines 21~35, a difference between the first offset and the second offset is stored as a trip point of the comparator). Regarding claim 2, all the limitations of claim 1 are taught by English. English further teaches the circuit, wherein said signal threshold comprises a droop threshold to be detected in a supply voltage of a logic circuit (Fig. 2, droop condition, col. 3, lines 3~5). Regarding claim 3, all the limitations of claim 1 are taught by English. English further teaches the circuit, wherein a noisy supply voltage to be measured is coupled to said at least one comparator in said first and second cycles, and a reference voltage is coupled to said at least one comparator in said second and first cycles (Fig. 3, col. 5, lines 7~30). Regarding claim 4, all the limitations of claim 3 are taught by English. English further teaches the circuit, wherein said reference voltage is a filtered version of said noisy supply voltage (Fig. 1, Vfilt 106, LPF 105). Regarding claim 6, all the limitations of claim 1 are taught by English. English further teaches the circuit, wherein said at least one comparator comprises two comparators which are instantiated in parallel such that when one of said comparators evaluates, the other one of said comparators integrates (Fig. 3, col. 5, lines 7~30). Regarding claim 8, all the limitations of claim 1 are taught by English. English further teaches the circuit, wherein said at least one comparator comprises multiple comparator pairs operating simultaneously and detecting crossings of different droop thresholds (Fig. 3, col. 5, lines 7~30). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over English (US 10,742,202 B1) in view of Crispie (US 5,332,931 A). Regarding claim 5, all the limitations of claim 1 are taught by English. English does not explicitly teach the circuit, wherein said at least one comparator is an auto-zeroed inverter. Crispie teaches a circuit wherein at least one comparator is an auto-zeroed inverter (Fig. 1, 10, Abstract, inverters). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the inverter based comparator of Crispie to the comparator of English in order to provide high speed operations with fewer components (Crispie, col. 1, lines 66~68). Regarding claim 9, all the limitations of claim 1 are taught by English. English does not explicitly teach the circuit, wherein said at least one comparator is coupled to two capacitors and uses a capacitance ratio of said two capacitors to generate said offset, and said signal threshold is tuned by capacitor switching of said capacitors. Crispie teaches a circuit wherein at least one comparator is coupled to two capacitors (Fig. 1, 21, 24, 22, 23) and uses a capacitance ratio of said two capacitors to generate said offset (col. 4, lines 37~39), and said signal threshold is tuned by capacitor switching of said capacitors (col. 4, lines 15~39). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the inverter based comparator of Crispie to the comparator of English in order to provide high speed operations with fewer components (Crispie, col. 1, lines 66~68). Regarding claim 10, this claim has substantially the same subject matter as that in claim 9. Therefore, claim 10 is rejected under the same rationale as claim 9 above. Allowable Subject Matter Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 7, the prior arts fail to teach or reasonably suggest a circuit comprising a clock phase generator that produces clock phases for operation of said comparators, said clock phases comprising two evaluation phases that overlap to mask transition effects between integration and evaluation phases of said comparators and to prevent a dead-zone in an output of said comparators, in combination with the other limitations of the claim. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at (571) 272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEOKJIN KIM/Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Mar 10, 2025
Application Filed
Jun 15, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
92%
With Interview (+13.8%)
2y 3m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 553 resolved cases by this examiner. Grant probability derived from career allowance rate.

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