CTNF 19/075,093 CTNF 87379 Detailed Action 12-151 AIA 26-51 12-51 Status of Claims Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-15 are presented for examination. Claims 1-15 are rejected. This Action is Non-Final. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 03/10/2025 and 04/07/2026,the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Miller et al. (US Patent No: 10,496,593 B1) in view of Bae et al. (US Patent No: 10,158,554 B1) . As per claim 1, Miller teaches a method comprising: configuring, by a hardware control manager [Fig.3, Signaling and flow control manager 357], of an electronic device, a die-to-die (D2D) constraint for a topology, wherein the hardware control manager manages a D2D interface [Fig.1; Abstract, col.2, ll.15-40, A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package,….]; performing, by the hardware control manager, D2D synchronization based on the D2D constraint [claim 7,…the first semiconductor die and the second semiconductor die contained in a common integrated circuit (IC) package; selectively enabling destination synchronizers for scalar or Gray-coded scalar signaling events of the first discrete signaling events;….]; configuring, by the hardware control manager, an inter-accelerator link constraint for the topology, wherein the hardware control manager manages a high-speed inter-accelerator link [col.1,ll.31-40, One of the challenges is to provide both inter-processor communication (IPC) and discrete signaling between dies via a single high-speed serial die-to-die interface, while meeting conflicting needs posed by each…..]; performing, by the hardware control manager, high-speed inter-accelerator link synchronization based on the inter-accelerator link constraint [col.1,ll.31-40, ….inter-processor communication (IPC) and discrete signaling between dies via a single high-speed serial die-to-die interface,…]; and monitoring, by the hardware control manager, the D2D interface and the high-speed inter- accelerator link based on the topology [col.1,ll.31-40, One of the challenges is to provide both inter-processor communication (IPC) and discrete signaling between dies via a single high-speed serial die-to-die interface, while meeting conflicting needs posed by each…..]. Miller does not explicitly disclose constraint for topology. Bae discloses constraint for topology [Abstract,col.2,ll.16-26, …determining a link topology solution based upon the at least one class of overlay and the one or more specified constraints, and publishing a topology policy based upon an optimized link topology solution to the plurality of communications nodes.]. It would have been obvious one ordinary skill in the art before the effective filling, date of the claimed invention, to include Bae ’s system for managing network link topology into Miller ’s system for facilitating inter-processor communication and signaling between dies in system-in-package products for the benefit of an efficient allocation of available network resources among uncoordinated application traffic flows is achieved by optimizing the network link topology and routing of application data traffic ( Bae , col.1, ll.7-12) to obtain the invention as specified in claim 1. As per claim 2, Miller and Bae teach all the limitations of claim 1 above, Miller and Bae teach, a method, wherein the D2D [ Miller , Fig.1; Abstract, col.2, ll.15-40, A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package,….] constraint comprises at least one of a physical transport layer (PTL) constraint, an application data link (ADL) constraint, or a physical layer (PHY) constraint [ Bae , col.1,ll.58-66, …. configure at least the network link topology based upon varying resource requests, varying physical layer constraints, and varying mission criteria which create additional constraints with respect to network resources and demand.]. As per claim 3, Miller and Bae teach all the limitations of claim 1 above, Miller and Bae teach, a method, wherein the inter-accelerator link constraint comprises at least one of a PTL constraint, a timing layer constraint [ Miller , col.7,ll.41-49, At block 413, a discrete signaling processing pipeline latency is constrained to a constant time.], a data link layer constraint, and a PHY constraint [ Bae , col.1,ll.58-66, …. configure at least the network link topology based upon varying resource requests, varying physical layer constraints, and varying mission criteria which create additional constraints with respect to network resources and demand.]. As per claim 4, Miller and Bae teach all the limitations of claim 1 above, Miller teaches, a method, wherein: the D2D synchronization is performed within a maximum number of synchronization attempts [ Miller , claim 7,…the first semiconductor die and the second semiconductor die contained in a common integrated circuit (IC) package; selectively enabling destination synchronizers for scalar or Gray-coded scalar signaling events of the first discrete signaling events;….]; and the high-speed inter-accelerator link synchronization is performed within the maximum number of synchronization attempts [ Miller , col.1,ll.31-40, One of the challenges is to provide both inter-processor communication (IPC) and discrete signaling between dies via a single high-speed serial die-to-die interface, while meeting conflicting needs posed by each…..]. As per claim 5, Miller and Bae teach all the limitations of claim 1 above, Miller teaches, a method, wherein the topology is valid with respect to a bandwidth, a current setting is unacceptable with respect to a parameter of the topology, and further comprising: setting, by the hardware control manager, a constraint with respect to at least one of a number of replies, enablement of replies, credit information, or bandwidth allocation [ Miller ,col.4,ll.58-61, By contrast, a processor bus conveys higher bandwidth data of a general nature between processors, as opposed to the lower bandwidth particular signaling values of signals of discrete signal lines.]. As per claim 6, Miller and Bae teach all the limitations of claim 5 above, Miller teaches, a method, wherein an inter-accelerator link parameter and a D2D parameter are valid for the constraint [ Miller , col.4,ll.1-12; col.4,ll.58-61, As noted above, at least one embodiment can provide technological improvement of performance of die-to-die communications. One or more features, such as the above-described multiple message classifications, per-classification QoS parameter values,….]. As per claim 7, Miller and Bae teach all the limitations of claim 5 above, Miller teaches, a method, wherein an inter-accelerator link parameter or a D2D parameter are not valid for the constraint, and further comprising: resetting the constraint by the hardware control manager [ Miller ,col.4,ll.58-61, By contrast, a processor bus conveys higher bandwidth data of a general nature between processors, as opposed to the lower bandwidth particular signaling values of signals of discrete signal lines.]. As per claims 8-14, claims 8-14 are rejected in accordance to the same rational and reasoning as the above claims 1-7 above, wherein claims 8-14 are the device claims for the method of claims 1-7. As per claim 15, claim 15 is rejected in accordance to the same rational and reasoning as the above claim 1 above, wherein claim 15 is the device claim for the method of claim 1. Conclusion RELEVANT ART CITED BY THE EXAMINER The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). References Considered Pertinent but not relied upon Lim et al. (US Patent Application Pub. No: 20190140647 A1) teaches systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices.; and also employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies. LI et al. (US Patent Application Pub. No: 20160013799 A1) teaches an apparatus for clock synchronization. Li discloses a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GETENTE A YIMER whose telephone number is (571)270-7106. The examiner can normally be reached on Monday-Friday 6:30-3:00.Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached on 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair my.uspto.gov/pair/ PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GETENTE A YIMER/Primary Examiner, Art Unit 2181 Application/Control Number: 19/075,093 Page 2 Art Unit: 2181
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