DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
Patent application filed on 3/10/2025.
Allowable Subject Matter
Claims 1-14 are allowed.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Heil et al. (U.S. 2009/0260013) and Paczkowski et al. (U.S. 2019/0258796) are the closest prior art references to reading upon the dependent and independent claim limitations of claims 1-14 and 20. However, neither of these references disclosed a set of programmable controllers with executable instructions for generating sets of events in response to computation data received through the network-on-chip layer.
Priority
The effective filing date for the subject matter defined in the pending claims in this application is 8/2/2019.
Drawings
The Examiner contends that the drawings submitted on 3/10/2025 are acceptable for examination proceedings.
Specification
The disclosure is objected to because of the following informalities:
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The Applicant’s cooperation is requested in correcting any errors of which the Applicant may become aware.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Applicants can file an eTerminal Disclaimer (eTD) in utility applications filed under 35 U.S.C. 111(a) or in compliance with 35 U.S.C. 371, and design applications. Filing an eTD via EFS-Web is highly recommended due to an extensive backlog for processing paper TDs. However, applicants may still file a TD for manual review.
Claims 15 and 19 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1 and 14 of U.S. Patent No. 12,248,430. Although the conflicting claims are not identical, they are not patentably distinct from each other because U.S. Patent No. 12,248,430 contains every element of claims 15 and 19 of the instant application and thus anticipates the claims of the instant application. Claims of the instant application therefore are not patently distinct from earlier patent claims and as such are unpatentable over obvious-type double patenting. A later application claim is not patently distinct from an earlier claim if the later claim is anticipated by the earlier claim.
Instant Application
U.S. Patent No. 12,248,430
15. A multicore processor, comprising a multicore processor stack, wherein the multicore processor stack comprises:
1. A multicore processor stack, stored on non-transitory computer readable media in a multicore processor, comprising:
a computation layer, for conducting computations using a set of processing cores in the multicore processor, with executable instructions for a set of processing pipelines in the set of processing cores;
a computation layer, for conducting computations using a set of processing cores in the multicore processor, with executable instructions for a set of processing pipelines in the set of processing cores;
a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for a set of routers and a set of network interface units in the multicore processor; and
a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for a set of routers and a set of network interface units in the multicore processor;
a set of programmable controllers, with executable instructions for reformatting computational data from the computation layer for transmission through the network- on-chip layer, wherein each processing core in the set of processing cores has a programmable controller from the set of programmable controllers; and
a network-on-chip overlay layer that logically isolates the computation layer and the network-on-chip layer.
a NoC overlay layer that logically isolates the computation layer and the network- on-chip layer.
Dependent claim 19 is read upon by the dependent claim 14 of U.S. Patent No. 12,248,430.
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 12,248,430, in view of Paczkowski et al. (U.S. 2019/0258796), in view of Official Notice.
Claims 17-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 12,248,430, in view of Heil et al. (U.S. 2009/0260013).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15 and 17-18 are rejected under 35 U.S.C. 102(a)(1 & 2) as being anticipated by Heil et al. (U.S. 2009/0260013).
As per claim 15:
Heil disclosed a multicore processor, comprising a multicore processor stack, wherein the multicore processor stack comprises:
a computation layer, for conducting computations using a set of processing cores in the multicore processor, with executable instructions for a set of processing pipelines in the set of processing cores (Heil: Figures 2-3 elements 104, 126, and 455-457, paragraphs 35, 45, and 59)(The set of processors within the set of IP blocks reads upon the computation layer. Each processor includes a plurality of executable hardware threads executed on pipelines.);
a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for a set of routers and a set of network interface units in the multicore processor (Heil: Figures 2-3 elements 108-110, paragraphs 36, 43, 48, 56-57)(The set of routers and NICs reads upon the network-on-chip layer. The virtual channel logic performs the function of examining packets and placing packets into virtual channel buffers. The instruction conversion logic converts command instructions from a command format to a network packet format.); and
a network-on-chip overlay layer that logically isolates the computation layer and the network-on-chip layer (Heil: Figures 2-3 elements 104, 107-110, and 124-126, paragraphs 36 and 43-44)(The set of interconnects reads upon the network-on-chip overlay layer. These elements logically isolates the processors within the IP Blocks and the set of routers and NICs.).
As per claim 17:
Heil disclosed the multicore processor of claim 15, wherein:
the network-on-chip overlay layer is hardware-instantiated via a set of network overlay units in the multicore processor (Heil: Figures 2-3 elements 104, 107-110, and 124-126, paragraphs 36 and 43-44)(The set of interconnects reads upon the network-on-chip overlay layer. These elements are hardware elements.); and
the set of network overlay units physically isolate: (i) the set of network interface units; and (ii) the set of routers; from: (i) a set of memories on the set of processing cores; and (ii) the set of processing pipelines (Heil: Figures 2-3 elements 104, 107-110, 124-126, 318-319, and 455-457, paragraphs 36 and 43-45)(The set of interconnects reads upon the network-on-chip overlay layer. The interconnects physically isolate the routers and NICs from the processor, which includes pipelines and memories.).
As per claim 18:
Heil disclosed the multicore processor of claim 15, wherein:
the network-on-chip overlay layer is hardware-instantiated via the set of network interface units in the multicore processor (Heil: Figures 2-3 elements 104, 107-110, and 124-126, paragraphs 36 and 43-44)(The set of interconnects reads upon the network-on-chip overlay layer. These elements are hardware elements.); and
the set of network interface units physically isolate the set of routers from: (i) a set of memories on the set of processing cores; and (ii) the set of processing pipelines (Heil: Figures 2-3 elements 104, 107-110, 124-126, 318-319, and 455-457, paragraphs 36 and 43-45)(The set of interconnects reads upon the network-on-chip overlay layer. The NIC physically isolate the routers from the processor, which includes pipelines and memories.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Paczkowski et al. (U.S. 2019/0258796), in view of Official Notice.
As per claim 15:
Paczkowski disclosed a multicore processor, comprising a multicore processor stack, wherein the multicore processor stack comprises:
a computation layer, for conducting computations using a set of processing cores in the multicore processor, with executable instructions for a set of processing pipelines in the set of processing cores (Paczkowski: Figures 1 and 4-5 elements 111, 121, 411, 421, 511, and 521, paragraphs 13-14, 26, 39, and 46)(The set of SoC cores reads upon the computation layer. The SoC cores execute VNF networking software to perform virtual network functions. In addition, official notice is given that CPUs include processing pipelines to execute instructions for the advantage of executing software programs. Thus, it would have been obvious to one of ordinary skill in the art to implement processing pipelines in the SoC cores to execute software programs.);
a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for a set of routers and a set of network interface units in the multicore processor (Paczkowski: Figures 1 and 4-5 elements 112- 114, 122-124, 412-416, 422-426, 512-516, and 522-526, paragraphs 13-14, 39, and 46) (The set of NoC cores reads upon the network-on-chip layer. The NoC cores include software data switches (i.e. set of routers) and hardware transceivers (i.e. network interface units).); and
a network-on-chip overlay layer that logically isolates the computation layer and the network-on-chip layer (Paczkowski: Figures 1 and 4-5 elements 101-106, 401-406, 415, 425, 501-506, 515, and 525, paragraphs 13-14, 39, and 46)(The set of VNFs and hypervisors/operating systems read upon the network-on-chip overlay layer. This set of elements isolates the processing pipelines of the SoC cores and the elements of the NoC cores.).
As per claim 16:
Paczkowski disclosed the multicore processor of claim 15, wherein:
the network-on-chip overlay layer is software-instantiated via storage of executable instructions in a set of memories on the set of processing cores in the multicore processor (Paczkowski: Figures 1 and 4-5 elements 101-106, 401-406, 415, 425, 501-506, 515, and 525, paragraphs 13-14, 39, and 46)(The set of VNFs and hypervisors/operating systems read upon the network-on-chip overlay layer. This set of elements isolates the processing pipelines of the SoC cores and the elements of the NoC cores. The OS is software-instantiated. Official notice is given that OS operations can be stored in processor caches while performing CPU operations in a privileged mode for the advantage of executing OS operations. Thus, it would have been obvious to one of ordinary skill in the art to implement storing OS operations within the CPUs of Paczkowski.); and
the executable instructions of the network-on-chip overlay layer are executed by the set of processing pipelines in the set of processing cores (Paczkowski: Figures 1 and 4-5 elements 101-106, 401-406, 415, 425, 501-506, 515, and 525, paragraphs 13-14, 39, and 46)(The set of VNFs and hypervisors/operating systems read upon the network-on-chip overlay layer. Official notice is given that OS operations are executed on CPU hardware for the advantage of performing privileged operations. Thus, it would have been obvious to one of ordinary skill in the art to implement OS operations on the CPUs of Paczkowski.).
As per claim 19:
Paczkowski disclosed the multicore processor of claim 15, wherein:
the network-on-chip overlay layer distributively instantiates a network-on-chip overlay graph across the set of processing cores (Paczkowski: Figures 1-2 and 4-5 elements 101-106, 401-406, 415, 425, 501-506, 515, and 525, paragraphs 13-14, 23-26, 39, and 46)(The set of VNFs and hypervisors/operating systems read upon the network-on-chip overlay layer. A NOC API is used for data transfer between different CPUs with SOC Cores and NOC Cores. The broadest reasonable interpretation of network-on-chip overlay graph is based on figure 4 showing a graph path between a source and destination core. The connection path established by the various APIs between a first and second SOC core reads upon the NOC overlay graph.); and
the network-on-chip overlay graph is configured by a runtime system during an application execution (Paczkowski: Figures 1-2 and 4-5 elements 101-106, 401-406, 415, 425, 501-506, 515, and 525, paragraphs 13-14, 23-26, 39, and 46)(The set of VNFs and hypervisors/operating systems read upon the network-on-chip overlay layer. A NOC API is used for data transfer between different CPUs with SOC Cores and NOC Cores. The broadest reasonable interpretation of network-on-chip overlay graph is based on figure 4 showing a graph path between a source and destination core. The connection path established by the various APIs between a first and second SOC core reads upon the NOC overlay graph. This connection path is established during processing as NOC API calls are made.).
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Pakhunov et al. (U.S. 8,966,222), taught message passing on a compute cluster.
Gonzalez et al. (U.S. 8,001,266), taught a multi-processor system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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