CTNF 19/075,313 CTNF 81527 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 4 recites that the operating environment comprises one of an operating system or a hypervisor. The examiner is interpreting this as only requiring it be one of an operating system or a hypervisor. However, the hypervisor appears to be an essential part of the invention. Par. 43 of Applicant’s specification states “Hypervisor 120 may be a native or bare-metal hypervisor that runs directly on platform logic 110 to control the platform logic and manage the guest operating systems.” Applicant should clarify whether the claim requires a hypervisor. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ould-Ahmed-Vall, US PGPub 2023/0205605, hereafter “Vall,” in view of Thyagaturu et al., US PGPub 2024/0353915, hereafter “Thyagaturu.” With respect to claim 1, Vall teaches an apparatus comprising: a plurality of hardware blocks (pars. 33-34, the functional units) ; a memory-based cross-domain solutions (M-CDS) device coupled to a plurality of hardware blocks (par. 30 and fig. 1, the operation monitor and/or hardware scheduler 129) , wherein the M-CDS device comprises: a processor (par. 28 and fig. 1, processor 101) ; a memory, wherein the memory comprises a shared memory region (par. 30 and fig. 1, the operation monitor and/or hardware scheduler includes memory containing global table 140 and unit off resources 120) ; and instructions executable by the processor to: create a buffer in the shared memory region to restrict transmission of data through the buffer to a given hardware block in the plurality of hardware blocks based on a configuration of the buffer (par. 51 and fig. 5, the storage for unit off resources comprises the buffer in the shared memory, which indicates whether a given unit 501 is on or off. Par. 34 discloses the restricting of transmission of data by locking a supply voltage from reaching a functional unit (hardware block)) , Vall doesn’t specifically mention that the buffer hides the presence of the hardware block from the operating environment. Thyagaturu teaches: wherein the buffer is to temporarily hide presence of the given hardware block on an interconnect from an operating environment (par. 111, making functions invisible to operating systems, where the function corresponds to “hardware block,” making invisible corresponds to “temporarily hide presence” and operating system corresponds to “operating environment.” The making invisible is temporary, as at a later time, it may be made visible to the OS by adding to the active function list and pushed to the OS, as described in par. 22) . It would have been obvious to one of ordinary skill in the art, having the teachings of Vall and Thyagaturu before him before the earliest effective filing date, to modify the memory system of Vall with the memory system of Thyagaturu, in order to improve the efficiency of using a computing device by preventing unnecessary and/or excessive function execution and/or power consumption, yet still permit external entity awareness that those particular functions may be activated at a future time, as taught by Thyagaturu in par. 111. With respect to claim 2, Vall and Thyagaturu teach all limitations of the parent claim. Vall further teaches the apparatus of claim 1, wherein the buffer is to implement a memory-based communication channel coupled to the given hardware block (par. 30 and fig. 1, operation monitor 129 implements a memory-based communication channel between memory 130 and processor 101/accelerators 107, which contain the hardware blocks) . With respect to claim 3, Vall and Thyagaturu teach all limitations of the parent claim. Vall further teaches the apparatus of claim 2, wherein the configuration of the buffer is based on a buffer scheme, the buffer scheme defines attributes of the buffer and one or more policies to apply at the buffer to implement the memory-based communication channel (par. 51 and fig. 5, the unit off resources indications comprise the buffer, which controls the communication between memory and the processors) . With respect to claim 4, Vall and Thyagaturu teach all limitations of the parent claim. Vall further teaches the apparatus of claim 1, wherein the operating environment comprises one of an operating system or a hypervisor (par. 26, operating system. The claim only requires one of an operating system or a hypervisor. However, Thyagaturu teaches that the operating environment can be a hypervisor and/or an OS, in par. 48 and fig. 6, 618) . With respect to claim 5, Vall and Thyagaturu teach all limitations of the parent claim. Vall further teaches the apparatus of claim 1, wherein the given hardware block is to be powered down in association with isolation of the given hardware block on the interconnect by the buffer (par. 34, the unit off resources of the buffer cause turning off the power to the function unit being turned off- “In some examples, the circuitry to cause an aspect to be off utilizes a transistor to block a supply voltage from reaching…a functional unit,” which corresponds to “powered down.” This powering down is in association with the change in the unit off resources, which corresponds to isolating the given hardware block on the interconnect, as the function will be unused or “isolated”) . With respect to claim 6, Vall and Thyagaturu teach all limitations of the parent claim. Vall further teaches the apparatus of claim 5, wherein the instructions are further executable by the processor to cancel the buffer based on a request to use the given hardware block, wherein management of the given hardware block by the operating environment is restored in association with cancellation of the buffer (par. 41, turning the indication from off to on corresponds to cancelling the buffer based on a request to use the given hardware block, turning it on gives access to the functional unit) . With respect to claim 7, Vall teaches at least one non-transitory machine-readable storage medium with instructions stored thereon, the instructions executable by a machine to cause the machine to: determine a subset of hardware blocks in a plurality of hardware blocks on a computing platform to be placed in a passive state, wherein other hardware blocks in the plurality of hardware blocks outside the subset of hardware blocks are to be in an active state (par. 34, the functional units being turned off correspond to the hardware blocks placed in a passive state, while the ones remaining on are the hardware blocks in the active state) ; configure a cross-domain solutions (CDS) device to implement one or more restricted memory-based communication channels to block access by an operating environment to the subset of hardware blocks while in the passive state (par. 34 and fig. 1, the operation monitor and/or hardware scheduler 129 blocks access to particular functional units when they are turned off) ; Vall uses one list, as shown in fig. 5, to control which functional units are turned off or on, and does not teach a passive list separate from an active list. Thyagaturu teaches: populate an active list with functions associated with the other hardware blocks in the active state (par. 86, the active list containing the cores that are active) ; and populate a passive list with functions associated with the subset of hardware blocks in the passive state (par. 86, the passive list containing the cores that are deactivated) . It would have been obvious to one of ordinary skill in the art, having the teachings of Vall and Thyagaturu before him before the earliest effective filing date, to modify the memory system of Vall with the memory system of Thyagaturu, in order to improve the efficiency of using a computing device by preventing unnecessary and/or excessive function execution and/or power consumption, yet still permit external entity awareness that those particular functions may be activated at a future time, as taught by Thyagaturu in par. 111. With respect to claim 8, Vall and Thyagaturu teach all limitations of the parent claim. Thyagaturu further teaches the at least one storage medium of claim 7, wherein the active list and the passive list are visible to the operating environment (par. 22, the AFL and PFL are published/made available to an external entity such an OS) . With respect to claim 9, Vall and Thyagaturu teach all limitations of the parent claim. Thyagaturu further teaches the at least one storage medium of claim 7, wherein the subset of the hardware blocks are to be powered-off in association with the passive state (par. 29, functions in the PFL are powered off) . With respect to claim 10, Vall and Thyagaturu teach all limitations of the parent claim. Thyagaturu further teaches the at least one storage medium of claim 7, wherein the instructions are further executable to: receive a request to activate a given hardware block in the subset of hardware blocks in the passive state (par. 50, a wake-up request for a particular function) ; reconfigure the CDS device to allow access to the given hardware block by the operating environment (par. 50, allowing the OS to access the function) ; remove a hardware function performed through the given hardware block from the passive list (par. 65, the function is swapped form the PFL to the AFL) ; and populate the active list with the hardware function performed through the given hardware block (par. 65, the function is swapped form the PFL to the AFL) . With respect to claim 11, Vall and Thyagaturu teach all limitations of the parent claim. Thyagaturu further teaches the at least one storage medium of claim 10, wherein the request to activate the given hardware block is based on an asset allocation request for an application or a virtual machine (pars. 46-49, the activation request is based on resources being need by the host (asset allocation request), the host comprising virtual machines and applications) . With respect to claim 12, Vall and Thyagaturu teach all limitations of the parent claim. Thyagaturu further teaches the at least one storage medium of claim 10, wherein the instructions are further executable to cause power to be reapplied to the given hardware block based on the request and prior to restoration of access to the given hardware block by the operating environment (par. 50, specific functions that are not otherwise known to the OS are powered up) . With respect to claim 13, Vall and Thyagaturu teach all limitations of the parent claim. Thyagaturu further teaches the at least one storage medium of claim 7, wherein the instructions are further executable to: determine an opportunity to transition a particular hardware block in the other hardware blocks from the active state to the passive state (par. 32, function directive for deactivation) ; configure the CDS device to cause the one or more restricted memory-based communication channels to further block access by the operating environment to the particular hardware block (par. 32, the function is powered off, restricting access) ; cause power to be removed from the particular hardware block (par. 32, the function is powered off) ; and move a hardware function performed through the particular hardware block from the active list to the passive list (par. 32, moving the hardware function from the AFL to PFL) . With respect to claim 14, Vall and Thyagaturu teach all limitations of the parent claim. Thyagaturu further teaches the at least one storage medium of claim 13, wherein the instructions are further executable to monitor one or more performance characteristics of the computing platform, wherein the opportunity to transition the particular hardware block from the active state to the passive state is based on the performance characteristics (par. 69, factors that influence the overall performance influence selections of the AFL and PFL) . With respect to claim 15, Vall teaches a system comprising: a computing platform (par. 28 and fig. 1, SOC 102) comprising: a processor (par. 28 and fig. 1, processor 101) ; an operating environment executed by the processor (par. 26, the operating system) ; a plurality of hardware blocks (pars. 33-34, the functional units) ; at least one memory-based cross-domain solutions (M-CDS) device (par. 30 and fig. 1, the operation monitor and/or hardware scheduler 129) ; an interconnect fabric to couple the plurality of hardware blocks and the M-CDS device (par. 30 and fig. 1, the processor 101 and accelerator 107, which contain the hardware blocks, are connected to the operation monitor and hardware scheduler 129) ; and a platform manager executable to: determine a subset of hardware blocks in the plurality of hardware blocks to place in a passive state, wherein power is to be removed from the subset of hardware blocks in the passive state (par. 34, the functional units being turned off correspond to the hardware blocks placed in a passive state) ; and Vall doesn’t specifically mention isolating the subset of hardware blocks from access by the operating environment. Thyagaturu teaches: configure the M-CDS device to implement a restricted memory-based communication channel on the interconnect fabric to isolate the subset of hardware blocks from access by the operating environment (par. 111, making functions invisible to the operating system) . It would have been obvious to one of ordinary skill in the art, having the teachings of Vall and Thyagaturu before him before the earliest effective filing date, to modify the memory system of Vall with the memory system of Thyagaturu, in order to improve the efficiency of using a computing device by preventing unnecessary and/or excessive function execution and/or power consumption, yet still permit external entity awareness that those particular functions may be activated at a future time, as taught by Thyagaturu in par. 111. With respect to claim 16, Vall and Thyagaturu teach all limitations of the parent claim. Vall further teaches the system of claim 15, wherein the M-CDS device comprises: a microcontroller (par. 30, the embedded microcontroller) ; a memory, wherein the memory comprises a shared memory region (par. 30 and fig. 1, the operation monitor and/or hardware schedule, which includes memory containing global table 140 and unit off resources 120) ; and a cross-domain solutions (CDS) manager executable by the microcontroller to create a buffer, based on a buffer scheme definition provided to the M-CDS device to implement the restricted memory-based communication channel (par. 51 and fig. 5, the unit off resources indications comprise the buffer, which restricts the memory-based communication between memory and the processors) . With respect to claim 17, Vall and Thyagaturu teach all limitations of the parent claim. Thyagaturu further teaches the system of claim 15, wherein isolation of the subset of hardware blocks from access by the operating environment is to prevent leakage voltage from management of the subset of hardware blocks by the operating environment (par. 18) . With respect to claim 18, Vall and Thyagaturu teach all limitations of the parent claim. Vall further teaches the system of claim 15, further comprising a system on chip comprising the processor, the plurality of hardware blocks, the interconnect fabric, and the M-CDS device (par. 27 and fig. 1, the SOC 102) . With respect to claim 19, Vall and Thyagaturu teach all limitations of the parent claim. Thyagaturu further teaches the system of claim 15, wherein the subset of hardware blocks comprises two or more hardware blocks isolated from access by the operating environment by the M-CDS device (par. 111, making functions invisible to the operating system) . With respect to claim 20, Vall and Thyagaturu teach all limitations of the parent claim. Vall further teaches the system of claim 15, wherein the plurality of hardware blocks comprises a plurality of processor cores and at least one of a memory block, an inputs/output (I/O) block, or a hardware accelerator block (pars. 26-29 the processing cores comprising the plurality of processor cores, and the functional aspects of the accelerator comprising the hardware accelerator block) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al., US PGPub 2022/0004338, discloses turning off processing cores based on power consumption. Yan et al., US PGPub 2019/0041823, and Govinden et al., US PGPub 2016/0321183 also disclose turning off processing cores. Chavan et al., US PGPub 2007/0266179 teaches activating hardware blocks . Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RYAN DARE/Examiner, Art Unit 2132 /HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132 Application/Control Number: 19/075,313 Page 2 Art Unit: 2132 Application/Control Number: 19/075,313 Page 3 Art Unit: 2132 Application/Control Number: 19/075,313 Page 4 Art Unit: 2132
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