DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-7 and 9-22 of U.S. Patent 12/265,710 contains every element of claims 2-4, 6-15 and 17-21 of the instant application and as such anticipates claims 2-4, 6-15 and 17-21 of the instant application. Claim 1 of the patent anticipates claims 2-4 of the instant application. Claims 2-8 of the patent anticipate claims 6-12 of the instant application, respectively. Claim 10 of the patent anticipates claims 13-15 of the instant application. Claims 11-14 of the patent anticipate claims 17-20 of the instant application, respectively. Claim 16 of the patent anticipates claim 20 of the instant application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-4, 6-15 and 17-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fultz et al. (US 9,256,381).
Consider claim 2, Fultz et al. discloses a memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: receive a signal to activate a write booster mode of the one or more memory devices; select, from a first location of the one or more memory devices associated with a first access mode and while the write booster mode is activated, a first portion of data to rewrite to the one or more memory devices using a second access mode for storing three or more bits per memory cell, a second portion of the data to maintain in a block associated with the first access mode, or both, the selection in response to one or more parameters satisfying one or more thresholds; and rewrite the first portion of the data to a second location of the one or more memory devices using the second access mode in response to the selection and receiving the signal to activate the write booster mode (abstract, Col. 5 lines 25-64, Col. 6 lines 26-54, Col. 8 lines 21-26 Col. 11 lines 55-63, Col. 12 lines 19-33 and 52-57, Col. 13 lines 13-15, Col. 14 lines 15-20, Col. 15 lines 31-67 and Col. 16 lines 1-3 and 51-67, data can be written to SLC memory than when performance parameters of the data change, such as temperature, the data can be migrated to MLC memory. The system can work in such a way that write temperature is tracked and write hot slices are moved or stay in the SLC memory. Fultz's method can be performed by a user.).
Consider claim 3, Fultz et al. discloses the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: write the data to the first location of the one or more memory devices prior to the selection using the first access mode for storing one bit per memory cell, the data written in response to receiving a command to write the data and receiving the signal to activate the write booster mode (abstract, Col. 5 lines 25-64, Col. 6 lines 26-54, Col. 8 lines 21-26 Col. 11 lines 55-63, Col. 12 lines 19-33 and 52-57, Col. 13 lines 13-15, Col. 14 lines 15-20, Col. 15 lines 31-67 and Col. 16 lines 1-3 and 51-67, data can be written to SLC memory than when performance parameters of the data change, such as temperature, the data can be migrated to MLC memory.).
Consider claim 4, Fultz et al. discloses the memory system of claim 2, wherein the block associated with the first access mode comprises the first location associated with the first access mode, and wherein the processing circuitry is further configured to cause the memory system to: maintain the second portion of the data at the first location of the one or more memory devices in response to the one or more parameters satisfying the one or more thresholds (abstract, Col. 5 lines 25-64, Col. 6 lines 26-54, Col. 8 lines 21-26 Col. 11 lines 55-63, Col. 12 lines 19-33 and 52-57, Col. 13 lines 13-15, Col. 14 lines 15-20, Col. 15 lines 31-67 and Col. 16 lines 1-3 and 51-67, The system can work in such a way that write temperature is tracked and write hot slices are moved or stay in the SLC memory.).
Consider claim 6, Fultz et al. discloses the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: determine whether a recency parameter of the one or more parameters satisfies a recency threshold of the one or more thresholds, the recency parameter indicating a duration between writing the data to the first location and selecting the first portion of the data, the second portion of the data, or both, wherein the first portion of the data, the second portion of the data, or both is selected in response to determining whether the recency parameter satisfies the recency threshold (abstract, Col. 5 lines 25-64, Col. 6 lines 26-54, Col. 8 lines 21-26 Col. 11 lines 55-63, Col. 12 lines 19-33 and 52-57, Col. 13 lines 13-15, Col. 14 lines 15-20, Col. 15 lines 31-67 and Col. 16 lines 1-3 and 51-67, the determined temperature of a slice is based on recency.).
Consider claim 7, Fultz et al. discloses the memory system of claim 2, wherein: the first portion of the data is rewritten to the second location in response to a first recency parameter of the one or more parameters associated with the first portion of the data failing to satisfy a recency threshold of the one or more thresholds, and the second portion of the data is maintained in the block associated with the first access mode in response to a second recency parameter associated with the second portion of the data satisfying the recency threshold (abstract, Col. 5 lines 25-64, Col. 6 lines 26-54, Col. 8 lines 21-26 Col. 11 lines 55-63, Col. 12 lines 19-33 and 52-57, Col. 13 lines 13-15, Col. 14 lines 15-20, Col. 15 lines 31-67 and Col. 16 lines 1-3 and 51-67, the determined temperature of a slice is based on recency. Slices are moved based on the temperature/current storage tier.).
Consider claim 8, Fultz et al. discloses the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: determine whether a frequency parameter of the one or more parameters satisfies a frequency threshold of the one or more thresholds, the frequency parameter indicating a frequency of access operations associated with the data, wherein the first portion of the data, the second portion of the data, or both is selected in accordance with whether the frequency parameter satisfies the frequency threshold (abstract, Col. 5 lines 25-64, Col. 6 lines 26-54, Col. 8 lines 21-26 Col. 11 lines 55-63, Col. 12 lines 19-33 and 52-57, Col. 13 lines 13-15, Col. 14 lines 15-20, Col. 15 lines 31-67 and Col. 16 lines 1-3 and 51-67, the determined temperature of a slice is based on frequency.).
Consider claim 9, Fultz et al. discloses the memory system of claim 2, wherein: the first portion of the data is rewritten to the second location in response to a first frequency parameter of the one or more parameters associated with the first portion of the data failing to satisfy a frequency threshold of the one or more thresholds, and the second portion of the data is maintained in the block associated with the first access mode in response to a second frequency parameter associated with the second portion of the data satisfying the frequency threshold (abstract, Col. 5 lines 25-64, Col. 6 lines 26-54, Col. 8 lines 21-26 Col. 11 lines 55-63, Col. 12 lines 19-33 and 52-57, Col. 13 lines 13-15, Col. 14 lines 15-20, Col. 15 lines 31-67 and Col. 16 lines 1-3 and 51-67, the determined temperature of a slice is based on frequency. Slices are moved based on the temperature/current storage tier.).
Consider claim 10, Fultz et al. discloses the memory system of claim 9, wherein the first portion of the data corresponds to a first access frequency lower than a second access frequency corresponding to the second portion of the data (abstract, Col. 5 lines 25-64, Col. 6 lines 26-54, Col. 8 lines 21-26 Col. 11 lines 55-63, Col. 12 lines 19-33 and 52-57, Col. 13 lines 13-15, Col. 14 lines 15-20, Col. 15 lines 31-67 and Col. 16 lines 1-3 and 51-67, different slices have different temperatures.).
Consider claim 11, Fultz et al. discloses the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: compare a quantity of writes associated with the one or more memory devices to a threshold quantity of writes, wherein the first portion of the data is written to the second location of the one or more memory devices using the second access mode in response to the quantity of writes satisfying the threshold quantity of writes (abstract, Col. 5 lines 25-64, Col. 6 lines 26-54, Col. 8 lines 21-26 Col. 11 lines 55-63, Col. 12 lines 19-33 and 52-57, Col. 13 lines 13-15, Col. 14 lines 15-20, Col. 15 lines 31-67 and Col. 16 lines 1-3 and 51-67, quantities of I/Os, reads and writes are used to determine when slices should be moved.).
Consider claim 12, Fultz et al. discloses the memory system of claim 2, wherein: the first access mode comprises a single level cell (SLC) mode, and the second access mode comprises a tri level cell (TLC) mode, or a quad level cell (QLC) mode (abstract, Col. 5 lines 25-64, Col. 6 lines 26-54, Col. 8 lines 21-26 Col. 11 lines 55-63, Col. 12 lines 19-33 and 52-57, Col. 13 lines 13-15, Col. 14 lines 15-20, Col. 15 lines 31-67 and Col. 16 lines 1-3 and 51-67, SLC and MLC is disclosed.).
Claims 13-15 and 17-20 are the medium claims to system claims 2-4 and 6-9 above and are rejected in the same manner.
Claim 21 is the medium claim to system claim 2-4 above and is rejected in the same manner.
Allowable Subject Matter
Claims 5 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2139
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