DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Receipt is acknowledged of the Preliminary Amendment filed on June 30, 2026. Accordingly, claim 1 is cancelled, and newly added claims 2-22 are currently pending in the application.
Claim Objections
Claim 8 is objected to because of the following informalities: “A” in line 1 should be replaced with -- An --. Appropriate correction is required.
Claim Interpretation
The Office's position is that “calibration system” or “integrated circuit” is just in the preamble and not tied to the body of the claim, so it is not given any patentable weight.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 of Lofthouse et al. (U.S. Patent No. 12,270,843 B2).
Although the claims at issue are not identical, they are not patentably distinct from each other because Lofthouse et al. claims all that is claimed.
With regard to claim 2, Lofthouse et al. does not explicitly claim “a first current path including the transistor and the sense resistor” (emphasis added). However, Lofthouse et al. recites a limitation, “while the transistor is on, perform a first resistance measurement of the sense resistor using the first current path”, that is, the sense resistor must be inherently included in the first current path (emphasis added).
With regard to claim 4, Lofthouse et al. does not explicitly claim “bypass circuitry”. However, Lofthouse et al. recites a limitation, “a second current path that bypasses the transistor”, that is, the second current path must inherently include “bypass circuitry”.
With regard to claim 7, the recitations of “the third current” and “the fourth current” correspond to “the first current” and “the second current”, respectively, as recited in claim 5 of Lofthouse et al.
With regard to claims 8-18, 21 and 22, it is noted that the feature upon which applicants rely (i.e., an “integrated circuit”) is just in the preamble and not tied to the body of the claim, so it is not given any patentable weight. In addition, according to MPEP 2144.04 V. B., “Making integral” is not an allowable subject matter.
With regard to claim 19, it is noted that the feature upon which applicants rely (i.e., “ the transistor and the sense resistor are external to a package of the integrated circuit”) is just a mere rearrangement of parts and not sufficient by itself to patentably distinguish over Lofthouse et al. In fact, “The mere fact that a worker in the art could rearrange the parts of the reference device to meet the terms of the claims on appeal is not by itself sufficient to support a finding of obviousness. The prior art must provide a motivation or reason for the worker in the art, without the benefit of appellant’s specification, to make the necessary changes in the reference device.” Ex parte Chicago Rawhide Mfg. Co., 223 USPQ 351, 353 (Bd. Pat. App. & Inter.1984). Therefore, the court held that mere rearrangement of parts has no patentable significance since it would both not have modified the operation of the device and an obvious matter of design choice (In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) and In re Kuhle, 526 F.2d 553, 188 USPQ7 (CCPA 1975): please see MPEP 2144.04 VI. C. Rearrangement of Parts for more details).
With regard to claim 20, it is noted that the feature upon which applicants rely (i.e., “the integrated circuit is used in power sourcing equipment (PSE)”) is just an intended use, which is not given any patentable weight.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the calibration circuit of Lofthouse et al. to apply the missing features (“integrated circuit” and “external to a package of the integrated circuit”) as identified above since such an arrangement is beneficial to improve upon what is already generally known and to provide a desirable and exemplary choices, which are well-known to one having ordinary skill in the art, for the purpose of a process or the intended use of a structure. Such an implementation can significantly increase the effectiveness of cost-effective manufacturability and physical compactness with desirable levels of accuracy, resolution, stability and reliability in the calibration circuit.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2, 3, 8-11 and 21 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chen et al. (US 2010/012767 A1).
Chen et al. teaches a battery charging system comprising:
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With regard to claim 2, a calibration system (FIG. 4B, LDO linear regulator 500) comprising: a transistor (FIG. 4B, switch 520); a sense resistor (FIG. 4B, second resistive divider 540); a first current path (FIG. 4B, path including switch 520, first resistive divider 530, and second resistive divider 540) including the transistor (FIG. 4B, switch 520) and the sense resistor (FIG. 4B, second resistive divider 540); an amplifier (FIG. 4B, amplifier 510) coupled to the sense resistor (FIG. 4B, second resistive divider 540) to provide an indication of voltage across the sense resistor (FIG. 4B, second resistive divider 540); and control logic (FIG. 4B, controller 700) configured to, while the transistor (FIG. 4B, switch 520) is on, cause a first current (first charging current) to flow through the first current path (FIG. 4B, path including switch 520, first resistive divider 530, and second resistive divider 540) and cause a second current (second charging current) to flow through the first current path (FIG. 4B, path including switch 520, first resistive divider 530, and second resistive divider 540) (For more details, please read: Abstract; paragraphs: [0038]-[0052]; and claims 1, 5 and 9).
With regard to claim 3, the control logic (FIG. 4B, controller 700) is further configured to measure with the amplifier (FIG. 4B, amplifier 510) a first voltage measurement (first output voltage) across the sense resistor (FIG. 4B, second resistive divider 540) resulting from the first current (first charging current), measure with the amplifier (FIG. 4B, amplifier 510) a second voltage measurement (second output voltage) across the sense resistor (FIG. 4B, second resistive divider 540) resulting from the second current (second charging current); and determine a first resistance value using the first voltage measurement (first output voltage) and the second voltage measurement (second output voltage) (For more details, please read: Abstract; paragraphs: [0038]-[0052]; and claims 1, 5 and 9).
With regard to claim 8, an integrated circuit (FIG. 4B, LDO linear regulator 500) comprising: a first terminal (FIG. 4B, input terminal 522); a pair of sense input terminals (FIG. 4B, two ends of second resistive divider 540); an amplifier (FIG. 4B, amplifier 510) coupled to the sense input terminals (FIG. 4B, two ends of second resistive divider 540) to provide an indication of voltage across a sense resistor (FIG. 4B, second resistive divider 540) (FIG. 4B, second resistive divider 540); and control logic (FIG. 4B, controller 700) configured to: cause a first current (first charging current) to flow through a first current path (FIG. 4B, path including switch 520, first resistive divider 530, and second resistive divider 540) and cause a second current (second charging current) to flow through the first current path (FIG. 4B, path including switch 520, first resistive divider 530, and second resistive divider 540), the first current path (FIG. 4B, path including switch 520, first resistive divider 530, and second resistive divider 540) extending from the first terminal (FIG. 4B, input terminal 522) through the sense resistor (FIG. 4B, second resistive divider 540) (For more details, please read: Abstract; paragraphs: [0038]-[0052]; and claims 1, 5 and 9).
With regard to claim 9, a control terminal (FIG. 4A, reference voltage Vref) configured to output a transistor control signal to a control terminal (FIG. 4B, switch control terminal 521) of a transistor (FIG. 4B, switch 520) coupled in the first current path between the first terminal and the sense resistor (FIG. 4B, second resistive divider 540) (For more details, please read: Abstract; paragraphs: [0038]-[0052]; and claims 1, 5 and 9).
With regard to claim 10, the control logic (FIG. 4B, controller 700) is further configured to output the transistor control signal to cause the transistor (FIG. 4B, switch 520) to enter an on state, and the control logic (FIG. 4B, controller 700) causes the first current (first charging current) and the second current (second charging current) to flow through the first current path while the transistor (FIG. 4B, switch 520) is in the on state (For more details, please read: Abstract; paragraphs: [0038]-[0052]; and claims 1, 5 and 9).
With regard to claim 11, the control logic (FIG. 4B, controller 700) is further configured to: measure with the amplifier (FIG. 4B, amplifier 510) a first voltage measurement (first output voltage) across the sense resistor (FIG. 4B, second resistive divider 540) resulting from the first current (first charging current); measure with the amplifier (FIG. 4B, amplifier 510) a second voltage measurement (second output voltage) across the sense resistor (FIG. 4B, second resistive divider 540) resulting from the second current (second charging current); and determine a first resistance value of the sense resistor (FIG. 4B, second resistive divider 540) using the first voltage measurement (first output voltage) and the second voltage measurement (second output voltage) (For more details, please read: Abstract; paragraphs: [0038]-[0052]; and claims 1, 5 and 9).
With regard to claim 21, an integrated circuit (FIG. 4B, LDO linear regulator 500) configured to measure a sense resistance, the integrated circuit (FIG. 4B, LDO linear regulator 500) comprising: a first terminal (FIG. 4B, input terminal 522); a first current source (FIG. 4F in view of FIG. 4A, one of the current sources) and a second current source (FIG. 4F in view of FIG. 4A, another one of the current sources) each coupled to the first terminal (FIG. 4B, input terminal 522); a pair of sense input terminals (FIG. 4B, two ends of second resistive divider 540); an amplifier (FIG. 4B, amplifier 510) coupled to the sense input terminals (FIG. 4B, two ends of second resistive divider 540) to provide an indication of voltage across a sense resistor (FIG. 4B, second resistive divider 540); and control logic (FIG. 4B, controller 700) configured to: control the first current source (FIG. 4F in view of FIG. 4A, one of the current sources) to cause a first current (first charging current) to flow through a first current path (FIG. 4B, path including switch 520, first resistive divider 530, and second resistive divider 540) extending from the first terminal (FIG. 4B, input terminal 522) through the sense resistor (FIG. 4B, second resistive divider 540) (FIG. 4B, second resistive divider 540); measure with the amplifier (FIG. 4B, amplifier 510) a first voltage measurement (first output voltage) across the sense resistor (FIG. 4B, second resistive divider 540) resulting from the first current (first charging current); control the second current source (FIG. 4F in view of FIG. 4A, another one of the current sources) to cause a second current (second charging current) to flow through the first current path (FIG. 4B, path including switch 520, first resistive divider 530, and second resistive divider 540); measure with the amplifier (FIG. 4B, amplifier 510) a second voltage measurement (second output voltage) across the sense resistor (FIG. 4B, second resistive divider 540) (FIG. 4B, second resistive divider 540) resulting from the second current (second charging current); and determine a first resistance value of the sense resistor (FIG. 4B, second resistive divider 540) (FIG. 4B, second resistive divider 540) using the first voltage measurement (first output voltage) and the second voltage measurement (second output voltage) (For more details, please read: Abstract; paragraphs: [0038]-[0052]; and claims 1, 5 and 9).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al.
Chen et al. teaches all that is claimed as discussed in the rejections of claims 2, 3, 8-11 and 21 above including the transistor (FIG. 4B, switch 520) and the sense resistor (FIG. 4B, second resistive divider 540), but it does not specifically teach the following features:
The transistor and the sense resistor are external to a package of the integrated circuit.
The integrated circuit is used in power sourcing equipment (PSE).
It is noted that:
With regard to claim 19, it is noted that the feature upon which applicants rely (i.e., “ the transistor and the sense resistor are external to a package of the integrated circuit”) is just a mere rearrangement of parts and not sufficient by itself to patentably distinguish over Lofthouse et al. In fact, “The mere fact that a worker in the art could rearrange the parts of the reference device to meet the terms of the claims on appeal is not by itself sufficient to support a finding of obviousness. The prior art must provide a motivation or reason for the worker in the art, without the benefit of appellant’s specification, to make the necessary changes in the reference device.” Ex parte Chicago Rawhide Mfg. Co., 223 USPQ 351, 353 (Bd. Pat. App. & Inter.1984). Therefore, the court held that mere rearrangement of parts has no patentable significance since it would both not have modified the operation of the device and an obvious matter of design choice (In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) and In re Kuhle, 526 F.2d 553, 188 USPQ7 (CCPA 1975): please see MPEP 2144.04 VI. C. Rearrangement of Parts for more details).
With regard to claim 20, it is noted that the feature upon which applicants rely (i.e., “the integrated circuit is used in power sourcing equipment (PSE)”) is just an intended use, which is not given any patentable weight.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the calibration circuit of Lofthouse et al. to apply the missing features (“integrated circuit” and “external to a package of the integrated circuit”) as identified above since such an arrangement is beneficial to improve upon what is already generally known and to provide a desirable and exemplary choices, which are well-known to one having ordinary skill in the art, for the purpose of a process or the intended use of a structure. Such an implementation can significantly increase the effectiveness of cost-effective manufacturability and physical compactness with desirable levels of accuracy, resolution, stability and reliability in the calibration circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants’ attention is invited to the followings whose inventions disclose similar devices.
Ahn (ES 2 994 607 T3) teaches a battery management system for estimating the parameters of an equivalent circuit model for a battery.
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HOAI-AN D. NGUYEN
Primary Examiner
Art Unit 2858
/HOAI-AN D. NGUYEN/ Primary Examiner, Art Unit 2858
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