DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 16, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over JO et al (US Pub 2021/0056909) in view of LEE et al (US Pub 2022/0114936) and Kim et al (US Pub 2020/0265785).
With respect to claim 1, JO discloses a display panel comprising a display area, wherein the display area comprises a first area and a second area at least partially surrounding the first area, (par 0045; discloses the organic light emitting diode display device includes a display area 110 in which a pixel 111 is formed on a substrate 100 to display an image, and a non-display area that is an area other than the display area 110) pixel circuits electrically connected to the gate driving circuits are provided in the first area, (fig. 1; discloses plurality of pixels 111 are formed in the display area 110 and are connected to gate drivers (i.e. stages 150) on both sides) trigger traces are provided in the second area, no pixel circuits are provided in the second area, and the trigger traces are electrically connected to the gate driving circuits (fig. 1; discloses plurality of signal line FLM Ck1-Ck4 are formed in the non-display area; par 0048; discloses the scan driver includes a plurality of stages 150 that respectively output one scan signal, and signal lines (FLM, CLK1, CLK2, CLK3, CLK4, GCK, and VGL) that are inputted to and outputted from respective stages 150); and the display panel satisfies at least one of the following: the display area comprises a plurality of light-emitting-device columns arranged along a first direction, the light-emitting-device columns comprise a plurality of light-emitting devices arranged along a second direction, the first direction intersects the second direction, (fig. 1; discloses the display panel comprises plurality of light emitting pixels (i.e. data lines, gate lines, circuit structure) arrange in a column extending in vertical direction and plurality of columns arranged in the horizontal direction that is perpendicular to vertical direction) and or the display area comprises a plurality of light-emitting-device rows arranged along the second direction, the light-emitting-device rows comprise a plurality of light-emitting devices arranged along the first direction, the first direction intersects the second direction, (fig. 1; discloses the display panel comprises plurality of light emitting pixels (i.e. data lines, gate lines, circuit structure) arrange in a row extending in horizontal direction and plurality of rows arranged in the vertical direction that is perpendicular to horizontal direction);
JO doesn’t expressly disclose gate driving circuits are provided in the first area;
In the same field of endeavor, LEE discloses a display device where the gate driving circuits and pixels connected to the gate driving circuits are provided in the first area (fig. 5; gate drivers NSA, NSB; par 0082; discloses the gate driver 300 may be integrated in a display area of the display panel 100. The gate driver 300 may be disposed between the pixels P of the display panel 100);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO to integrate the gate drivers between the pixels of the display panel as disclosed by LEE in order to reduce the peripheral area of the display panel such that a display device with reduced bezel is made;
JO as modified by LEE don’t expressly disclose along a thickness direction of the display panel, the trigger traces overlap the 1st one of the light-emitting- device columns or the last one of the light-emitting-device columns; and along the thickness direction of the display panel, the trigger traces at least partially overlap the 1st one of the light- emitting-device rows;
In the same filed of endeavor, Kim discloses display device (see abstract); Kim discloses along a thickness direction of the display panel, the trigger traces overlap the 1st one of the light-emitting- device columns or the last one of the light-emitting-device columns; and along the thickness direction of the display panel, the trigger traces at least partially overlap the 1st one of the light- emitting-device rows; (Par 0083; discloses the plurality of G-TFTs GT can be electrically arranged with respect to each other. A gate driver 130 (see FIG. 3) composed of a plurality of G-TFTs GT may be elongated in the column direction Y and overlap the pixel PXL; par 0188; discloses The first gate driver 130a can be electrically connected to a plurality of wires 134a. The plurality of wires 134a can carry a driving signal or control signal to the first gate driver 130a. The plurality of wires 134a can be electrically connected to the data driver 120 and the source COF 122. Fig. 3; discloses the plurality of wires 134 are formed at the edge that overlaps the plurality that are located at the edges of the panel);
Therefore, it would have been obvious one having ordinary skill in the art to modify the invention disclosed by Jo as modified by LEE to incorporate the teachings of Kim to form trigger traces to overlap the pixels located at the edges of the panel in order to further reduce the non-display region of the display device.
With respect to claim 2, JO as modified by LEE and Kim discloses wherein the 1st one to the n-th one of the trigger traces are electrically connected to the 1st one to the n-th one of the gate driving circuits in a one-to-one correspondence, and n>2; and the 1st one to the n-th one of the trigger traces do not intersect with each other (JO; fig. 5; discloses a first FLM line transmitting a start signal to the left side scan driver and a second FLM line transmitting a start signal to the right side scan driver and they do not interest with each other).
With respect to claim 3, JO as modified by LEE and Kim discloses wherein one of the trigger traces comprises a first segment, a second segment, and a third segment which are connected to one another, (JO; fig. 1; discloses each FLM lines includes multiple segments that are connected to one another to form a single line; see annotated fig. 1 below) the second segment is electrically connected between the first segment and the third segment, the first segment is electrically connected to a trigger signal terminal, the third segment is electrically connected to the gate driving circuit, the second segment extends along a first direction, the first segment and the third segment extend along a second direction, and the first direction intersects with the second direction (JO; the first segment and third segment extend in one direction while the second segment extend in second direction that crosses the first direction; see annotated fig. 1 below); and along the first direction, arrangement order of the first segments of the 1st one to the n-th one of the trigger traces is opposite to arrangement order of the 1st one to the n-th one of the gate driving circuits (JO; fig. 1; discloses first segment of line FLM is at the bottom of the panel where the first gate driver stage is at the top of the panel); and arrangement order of the third segments of the 1st one to the n-th one of the trigger traces is the same as arrangement order of the 1st one to the n-th one of the gate driving circuits (JO; fig. 1; discloses the third segment of the line FLM is at the same location as the first stage of the gate driver ).
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With respect to claim 16, JO as modified by LEE and Kim wherein first ends of the trigger traces are electrically connected to trigger signal terminals, along a second direction, the trigger signal terminals are located at a side of the gate driving circuits, and along a first direction, the trigger signal terminals are located between the gate driving circuits and the trigger traces (JO; fig. 1; discloses trigger signal FLM are connected to gate driver terminal on second direction and the terminal are location between the gate drivers and the FLM traces).
With respect to claim 20, JO discloses a display apparatus comprising a display panel, (JO; par 0044; discloses the display device according to the present exemplary embodiment is an organic light emitting diode display device, and displays a high resolution such as 4K or 8K) the display panel comprising a display area, wherein the display area comprises a first area and a second area at least partially surrounding the first area, (par 0045; discloses the organic light emitting diode display device includes a display area 110 in which a pixel 111 is formed on a substrate 100 to display an image, and a non-display area that is an area other than the display area 110) pixel circuits electrically connected to the gate driving circuits are provided in the first area, (fig. 1; discloses plurality of pixels 111 are formed in the display area 110 and are connected to gate drivers (i.e. stages 150) on both sides) trigger traces are provided in the second area, no pixel circuits are provided in the second area, and the trigger traces are electrically connected to the gate driving circuits (fig. 1; discloses plurality of signal line FLM Ck1-Ck4 are formed in the non-display area; par 0048; discloses the scan driver includes a plurality of stages 150 that respectively output one scan signal, and signal lines (FLM, CLK1, CLK2, CLK3, CLK4, GCK, and VGL) that are inputted to and outputted from respective stages 150); and the display panel satisfies at least one of the following: the display area comprises a plurality of light-emitting-device columns arranged along a first direction, the light-emitting-device columns comprise a plurality of light-emitting devices arranged along a second direction, the first direction intersects the second direction, (fig. 1; discloses the display panel comprises plurality of light emitting pixels arrange in a column extending in vertical direction and plurality of columns arranged in the horizontal direction that is perpendicular to vertical direction) and or the display area comprises a plurality of light-emitting-device rows arranged along the second direction, the light-emitting-device rows comprise a plurality of light-emitting devices arranged along the first direction, the first direction intersects the second direction, (fig. 1; discloses the display panel comprises plurality of light emitting pixels arrange in a row extending in horizontal direction and plurality of rows arranged in the vertical direction that is perpendicular to horizontal direction);
JO doesn’t expressly disclose gate driving circuits are provided in the first area;
In the same field of endeavor, LEE discloses a display device where the gate driving circuits and pixels connected to the gate driving circuits are provided in the first area (fig. 5; gate drivers NSA, NSB; par 0082; discloses the gate driver 300 may be integrated in a display area of the display panel 100. The gate driver 300 may be disposed between the pixels P of the display panel 100);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO to integrate the gate drivers between the pixels of the display panel as disclosed by LEE in order to reduce the peripheral area of the display panel such that a display device with reduced bezel is made;
JO as modified by LEE don’t expressly disclose along a thickness direction of the display panel, the trigger traces overlap the 1st one of the light-emitting- device columns or the last one of the light-emitting-device columns; and along the thickness direction of the display panel, the trigger traces at least partially overlap the 1st one of the light- emitting-device rows;
In the same filed of endeavor, Kim discloses display device (see abstract); Kim discloses along a thickness direction of the display panel, the trigger traces overlap the 1st one of the light-emitting- device columns or the last one of the light-emitting-device columns; and along the thickness direction of the display panel, the trigger traces at least partially overlap the 1st one of the light- emitting-device rows; (Par 0083; discloses the plurality of G-TFTs GT can be electrically arranged with respect to each other. A gate driver 130 (see FIG. 3) composed of a plurality of G-TFTs GT may be elongated in the column direction Y and overlap the pixel PXL; par 0188; discloses The first gate driver 130a can be electrically connected to a plurality of wires 134a. The plurality of wires 134a can carry a driving signal or control signal to the first gate driver 130a. The plurality of wires 134a can be electrically connected to the data driver 120 and the source COF 122. Fig. 3; discloses the plurality of wires 134 are formed at the edge that overlaps the plurality that are located at the edges of the panel);
Therefore, it would have been obvious one having ordinary skill in the art to modify the invention disclosed by Jo as modified by LEE to incorporate the teachings of Kim to form trigger traces to overlap the pixels located at the edges of the panel in order to further reduce the non-display region of the display device.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over JO et al (US Pub 2021/0056909) in view of LEE et al (US Pub 2022/0114936), Kim et al (US Pub 2020/0265785) and LV et al (US Pub 2024/0221548).
With respect to claim 4, JO as modified by LEE and Kim discloses wherein the trigger traces comprise first trigger traces and second trigger traces, and along a first direction, the first trigger traces and the second trigger traces are located at two sides of a center of the display area, respectively (JO; fig. 1; discloses FLM trigger line is disposed on both sides of the panel);
JO as modified by LEE and Kim don’t expressly disclose trigger connection lines are provided in the second area and are electrically connected between the first trigger traces and the second trigger traces;
In the same field of endeavor, LV discloses a display device and driving method where the driving circuit are disposed within the panel between the pixels (see abstract); LV discloses trigger connection lines are provided in the second area and are electrically connected between the first trigger traces and the second trigger traces (par 0075; discloses as shown in FIG. 7, the plurality of pixel driving chips 2 are divided into a first portion a and a second portion b having the same number of rows, and the gate line corresponding to the n-th row of pixel driving chips 2 in the first portion a and the gate line corresponding to the n-th row of pixel driving chips 2 in the second portion b are coupled to the same signal output line 61;);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO as modified by LEE and Kim to incorporate the teachings of LV to connect the trigger lines connected to different scan driver of different section so display such that driving time of the each frame is greatly reduced, thereby improving the electronic frame frequency of the display panel and further improving the display effect.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over JO et al (US Pub 2021/0056909) in view of LEE et al (US Pub 2022/0114936), Kim et al (US Pub 2020/0265785), LV et al (US Pub 2024/0221548) and SU et al (US Pub 2024/0213262).
With respect to claim 5, JO as modified by LEE, Kim and LV don’t expressly disclose wherein at least one of the trigger connection lines comprises a first connection segment and a second connection segment which are connected to each other, the first connection segment at least partially overlaps the trigger traces, and the second connection segment does not overlap the trigger traces; and a line width of the first connection segment is less than a line width of the second connection segment;
In the same field of endeavor, SU discloses a display device and method for connecting control lines for scan drivers; SU discloses wherein at least one of the trigger connection lines comprises a first connection segment and a second connection segment which are connected to each other, the first connection segment at least partially overlaps the trigger traces, and the second connection segment does not overlap the trigger traces; and a line width of the first connection segment is less than a line width of the second connection segment (fig. 5A, 5C; discloses a connector 300 that connects elements 220 and line 120 where the connector 300 includes first segment 310, that overlaps and connects to element 220, and a second segment 330 that is connected to first segment and has a width less than the first segment 310);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO as modified by LEE, Kim and LV to connect the two trigger lines using a connector disclosed by SU in order to securely connect two different lines while simplifying the preparation process flow, a production cost may be saved, and production efficiency may be improved.
With respect to claim 6, JO as modified by LEE, Kim, LV and SU discloses wherein the first connection segment is located in a first metal layer of the display panel, the second connection segment is located in a second metal layer of the display panel, and sheet resistance of the second metal layer is less than sheet resistance of the first metal layer (SU; par 0097; discloses the bridge portion and the signal lead-in portion are located at different layers. Illustratively, the bridge portion and the data line may be arranged on the same layer and made of the same material; par 0113; discloses the first signal lead-in portion 210 is divided into the first signal lead-in sub-portion 211 and the third signal lead-in sub-portion 213, and the first signal lead-in sub-portion 211 is electrically connected to the third signal lead-in sub-portion 213 by means of the fifth bridge connection portion 450, such that a resistance of a current flow path from the first signal lead-in portion 210 to the signal lead-in line in the first line set may be increased, and then a voltage difference between a flow path of the signal stv_a and a flow path of the signal stv_b may be reduced, so as to reduce a difference in delay when the signals stv_a and stv_b are input into the signal input end IP, and further to improve the display effect).
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over JO et al (US Pub 2021/0056909) in view of LEE et al (US Pub 2022/0114936), Kim et al (US Pub 2020/0265785) and KIM et al (US Pub 2019/0197961) referred to as KIM961.
With respect to claim 8, JO as modified by LEE, Kim don’t expressly discloses wherein the display area comprises a first middle line, a width of the display panel along the first direction is D, the first middle line extends along the second direction, a distance between the first middle line and one of first edges of the display panel along the first direction is dl, dl= D/2, at least one of the gate driving circuits is provided at each of two sides of the first middle line along the second direction, and the first direction intersects with the second direction;
In the same field of endeavor, KIM961 discloses display device and control method (see abstract); wherein the display area comprises a first middle line, (fig. 6; discloses display area comprises a center line in the form of center GIP 157C) a width of the display panel along the first direction is D, the first middle line extends along the second direction, a distance between the first middle line and one of first edges of the display panel along the first direction is dl, dl= D/2 (fig. 6; discloses the center GIP divides the display area into two equal parts), at least one of the gate driving circuits is provided at each of two sides of the first middle line along the second direction, and the first direction intersects with the second direction (fig. 6; discloses gate driver 157L and 157R are provided on both sides of the middle GIP 157C);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO as modified by LEE, Kim to incorporate the teachings of KIM961 to equally divide the display area in two parts where each part is driven using a separate scan driver in order to prevent any delay in scan signals being provided to display panel that are large in size. Hence preventing image degradation.
With respect to claim 9, JO as modified by LEE, Kim and KIM961 further discloses wherein n of the gate driving circuits are provided at each of two sides of the first middle line along the first direction, and the gate driving circuits at two sides of the first middle line are symmetrically provided (KIM961; fig. 6; discloses gate driving circuits 157l and 157R are provided on both sides of the panel and are symmetrical with respect to the middle driver 157C );
JO as modified by LEE, Kim and KIM961 don’t expressly disclose a distance between one of second middle lines of the display area and the first middle line of the display area along the first direction is d2, d2 = D/4, and at least one of the gate driving circuits is provided at each of two sides of the second middle line along the first direction;
KIM961 further discloses a distance between one of second middle lines of the display area and the first middle line of the display area along the first direction is d2, d2 = D/4, and at least one of the gate driving circuits is provided at each of two sides of the second middle line along the first direction; (KIM; see fig. 2; discloses second middle line indicated by dotted line between GIP 157L and Middle GIP 157C; KIM; par 0066; discloses pixels adjacent to the central area of the display panel 110 may be defined as subpixels which are included in the left and right adjacent areas of the central scan driver 157C, except the left and right outer areas, among quadrants of the display panel 110 with reference to the central scan driver 157C (for example, equally dividing the display area into four areas as shown in FIG. 6).
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO as modified by LEE, Kim and KIM961 to incorporate the teachings of KIM to equally divide the display area in multiple parts where each part is driven using a separate scan driver in order to prevent any delay in scan signals being provided to display panel that are large in size. Hence preventing image degradation.
With respect to claim 10, JO as modified by LEE, Kim and KIM961 wherein the display panel comprises N pixel- circuit columns arranged along the first direction, and one of the pixel-circuit columns comprises a plurality of the pixel circuits arranged along the second direction; and at least one of the gate driving circuits is provided at each of two sides of the N/4-th one of the pixel-circuit columns along the first direction, and N/4 takes an integer part;
LEE further discloses wherein the display panel comprises N pixel- circuit columns arranged along the first direction, and one of the pixel-circuit columns comprises a plurality of the pixel circuits arranged along the second direction (fig. 3; pixels P; par 0073; discloses the display panel 100 may include a plurality of gate lines GL, a plurality of data lines DL and a plurality of pixels P electrically connected to the gate lines GL and the data lines DL. The gate lines GL may extend in a first direction D1 and the data lines DL extend in a second direction D2 crossing or intersecting the first direction D1); and at least one of the gate driving circuits is provided at each of two sides of the N/4-th one of the pixel-circuit columns along the first direction, and N/4 takes an integer part (fig. 10; discloses plurality of scan driver NSA-NSF are provide between the columns of pixels);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO as modified by LEE, Kim and KIM961 to incorporate the teachings of LEE to dispose plurality of scan drivers through the panel between the columns of pixels in order to quickly supply the scan signals to the plurality of pixels preventing delays.
Claim(s) 11-15, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over JO et al (US Pub 2021/0056909) in view of LEE et al (US Pub 2022/0114936), Kim et al (US Pub 2020/0265785) and JEONG et al (US Pub 2023/0082959).
With respect to claim 11, JO as modified by LEE, Kim don’t expressly disclose wherein the display panel further comprises static electricity ring lines, and at least part of the static electricity ring lines is located at a side of the trigger traces away from a center of the display panel; or the display panel further comprises fixed-voltage signal lines, and at least part of the fixed- voltage signal lines is located at a side of the trigger traces close to a center of the display panel;
In the same field of endeavor, JEONG discloses display device with scan driver disposed between the pixels (see abstract); JEONG discloses wherein the display panel further comprises static electricity ring lines, and at least part of the static electricity ring lines is located at a side of the trigger traces away from a center of the display panel (par 0109; discloses the antistatic area ESA may include a plurality of electrostatic discharging circuits ESD. The plurality of electrostatic discharging circuits ESD may overlap the first to third pixels SP1, SP2, and SP3 of the first pixel row PROWL The electrostatic discharging circuit ESD may protect a fan-out line FOL, a demultiplexer DMX, and the pixel circuit PC from static electricity. The electrostatic discharging circuit ESD may dissipate static electricity flowing from the outside to prevent the static electricity from flowing into the display area DA); or the display panel further comprises fixed-voltage signal lines, and at least part of the fixed- voltage signal lines is located at a side of the trigger traces close to a center of the display panel (par 0100; discloses The gate driver GDR may be connected to a clock line, a voltage line, and a carry line extending in the pixel circuit area CCA. Par 0115; discloses The voltage line VL may extend in the second direction (Y-axis direction) between two adjacent demultiplexers DMX. In an embodiment, for example, the voltage line VL may be disposed between the third data line DL3 connected to the left demultiplexer DMX between two demultiplexers DMX adjacent in the first direction (X-axis direction) and the first data line DL1 connected to the right demultiplexer DMX. The voltage line VL and the clock line CLK may be spaced apart from each other with the first to third data lines DL1, DL2, and DL3 interposed therebetween. The voltage line VL may supply at least one selected from a gate high voltage, a gate low voltage, a power voltage, or a control voltage to the first to third stages STG1, STG2, and STG3. The voltage line VL may pass or extend through the first to third stages STG1, STG2, and STG3, but the disclosure is not limited thereto.);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO as modified by LEE and Kim to incorporate the teachings of JEONG to dispose electrostatic circuits around the display panel in order to dissipate static electricity flowing from the outside to prevent the static electricity from flowing into the display area DA, hence improving display quality.
With respect to claim 12, JO as modified by LEE and Kim wherein one of the gate driving circuits comprises a first end and a second end which are opposite to each other along a first direction, and the first ends of the gate driving circuits are connected to the trigger traces (JO; fig. 1; discloses the FLM line on both side of the panel is connected to first stages of the gate drivers);
JO as modified by LEE, and Kim don’t expressly disclose the display panel further comprises first static electricity protection circuits electrically connected to the trigger traces, and the first static electricity protection circuits are adjacent to the first ends of the gate driving circuits;
In the same field of endeavor, JEONG discloses display device with scan driver disposed between the pixels (see abstract); JEONG discloses the display panel further comprises first static electricity protection circuits electrically connected to the trigger traces, and the first static electricity protection circuits are adjacent to the first ends of the gate driving circuits; (par 0109; discloses the antistatic area ESA may include a plurality of electrostatic discharging circuits ESD. The plurality of electrostatic discharging circuits ESD may overlap the first to third pixels SP1, SP2, and SP3 of the first pixel row PROWL The electrostatic discharging circuit ESD may protect a fan-out line FOL, a demultiplexer DMX, and the pixel circuit PC from static electricity. The electrostatic discharging circuit ESD may dissipate static electricity flowing from the outside to prevent the static electricity from flowing into the display area DA);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO as modified by LEE and Kim to incorporate the teachings of JEONG to dispose electrostatic circuits around the display panel in order to dissipate static electricity flowing from the outside to prevent the static electricity from flowing into the display area DA, hence improving display quality.
With respect to claim 13, JO as modified by LEE, Kim and JEONG discloses wherein the display area comprises a plurality of light-emitting-device rows, (JEONG; fig. 2; discloses panel with plurality of pixel rows PROWs) and orthographic projections of the first static electricity protection circuits on a plane where the display panel is located are located between an orthographic projection of the first one of the light-emitting-device rows on the plane where the display panel is located and an orthographic projection of the second one of the light- emitting-device rows on the plane where the display panel is located (JEONG; fig. 2; discloses the antistatic area ESA is disposed between the first row of pixels PROW1 and second row of pixels PROW2).
With respect to claim 14, JO as modified by LEE, Kim and JEONG discloses wherein the 1 st one to the n-th one of the trigger traces are electrically connected to the 1st one to the n-th one of the gate driving circuits in a one-to-one correspondence, and the 1st one to the n-th one of trigger traces are electrically connected to the 1st one to the n-th one of the first static electricity protection circuits in a one- to-one correspondence (JO; fig. 1; discloses FLM line on the left side if connected to left side scan driver and FLM on the right side is connected to right side scan driver in one-to-one correspondence), and the j-th one of the first static electricity protection circuits is adjacent to the first end of the j-th one of the gate driving circuits, and j is any one of 1 to n (par 0109; discloses the antistatic area ESA may include a plurality of electrostatic discharging circuits ESD. The plurality of electrostatic discharging circuits ESD may overlap the first to third pixels SP1, SP2, and SP3 of the first pixel row PROWL The electrostatic discharging circuit ESD may protect a fan-out line FOL, a demultiplexer DMX, and the pixel circuit PC from static electricity. The electrostatic discharging circuit ESD may dissipate static electricity flowing from the outside to prevent the static electricity from flowing into the display area DA; JEONG; fig. 2; discloses the antistatic area ESA is disposed around the edges of the panel);
JO as modified by LEE, Kim and JEONG expressly disclose n gate driving circuits n > 2;
LEE further disclose n gate driving circuits n > 2 (see fig. 10; scan drivers NSA-NSF; each receiving one trigger signals);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO as modified by LEE, Kim and JEONG to incorporate the teachings of LEE to dispose plurality of scan driver in the display panel in order to prevent any delay in scan signal transmitted to the pixels in large display panel, hence preventing image deterioration.
With respect to claim 15, JO as modified by LEE, Kim and JEONG wherein one of the trigger traces comprises a first segment, a second segment, and a third segment which are connected to one another, (JO; fig. 1; discloses each FLM lines includes multiple segments that are connected to one another to form a single line; see annotated fig. 1 above) the second segment is electrically connected between the first segment and the third segment, the first segment is electrically connected to a trigger signal terminal, the third segment is electrically connected to the gate driving circuit, the first segment and the third segment extend along a second direction, the second segment extends along a first direction, and the first direction intersects with the second direction; (JO; the first segment and third segment extend in one direction while the second segment extend in second direction that crosses the first direction; see annotated fig. 1 above); and along the second direction, the first static electricity protection circuits are located between the second segments and the gate driving circuits (JEONG; par 0109; discloses the antistatic area ESA may include a plurality of electrostatic discharging circuits ESD. The plurality of electrostatic discharging circuits ESD may overlap the first to third pixels SP1, SP2, and SP3 of the first pixel row PROWL The electrostatic discharging circuit ESD may protect a fan-out line FOL, a demultiplexer DMX, and the pixel circuit PC from static electricity. The electrostatic discharging circuit ESD may dissipate static electricity flowing from the outside to prevent the static electricity from flowing into the display area DA; JEONG; fig. 2; discloses the antistatic area ESA is disposed around the edges of the panel).
With respect to claim 17, JO as modified by LEE and Kim don’t expressly disclose wherein the display panel further comprises second static electricity protection circuits which are electrically connected to the trigger traces and adjacent to the trigger signal terminals;
In the same field of endeavor, JEONG discloses display device with integrated scan circuits with the pixels (see abstract); JEONG discloses wherein the display panel further comprises second static electricity protection circuits which are electrically connected to the trigger traces and adjacent to the trigger signal terminals (par 0106; discloses the antistatic area ESA is disposed at the outer part of the display area DA, such that electrostatic discharge and a short-circuit failure between lines may be effectively prevented. Par 0121; discloses the electrostatic discharging circuit ESD may be disposed adjacent to the fan-out line FOL. Some of the electrostatic discharging circuits ESD may be connected between the fan-out line FOL and a gate-off voltage line VGHL, and some others of the electrostatic discharging circuits ESD may be connected between the fan-out line FOL and a gate-on voltage line VGLL. The electrostatic discharging circuit ESD may be connected to the portion between the first and second line resistors R1 and R2 of the fan-out line FOL, but the disclosure is not limited thereto. Therefore, the electrostatic discharging circuit ESD may dissipate static electricity flowing from the outside to prevent the static electricity from flowing into the display area DA.);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO as modified by LEE and Kim to incorporate the teachings of JEONG to dispose electrostatic circuits around the display panel in order to dissipate static electricity flowing from the outside to prevent the static electricity from flowing into the display area DA, hence improving display quality.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over JO et al (US Pub 2021/0056909) in view of LEE et al (US Pub 2022/0114936), Kim et al (US Pub 2020/0265785) and JEONG et al (US Pub 2023/0186836).
With respect to claim 18, JO as modified by LEE and Kim don’t expressly disclose wherein one of the pixel circuits comprises an amplitude modulation sub-circuit and a pulse width modulation sub-circuit, the gate driving circuits comprise first-type gate driving circuits and second-type gate driving circuits, the first- type gate driving circuits are configured to drive the amplitude modulation sub-circuits, and the second-type gate driving circuits are configured to drive the pulse width modulation sub- circuits; and fixed-voltage signal lines of the display panel comprise first-type fixed-voltage signal lines and second-type fixed-voltage signal lines, the first-type fixed-voltage signal lines are electrically connected to the first-type gate driving circuits, and the second-type fixed-voltage signal lines are electrically connected to the second-type gate driving circuits;
In the same field of endeavor, JEONG discloses display device and control method (see abstract); JEONG discloses wherein one of the pixel circuits comprises an amplitude modulation sub-circuit and a pulse width modulation sub-circuit, (fig. 2; discloses pixel circuit include pulse width modulation circuit PDU2 and amplitude modulation circuit PDU3) the gate driving circuits comprise first-type gate driving circuits and second-type gate driving circuits, the first- type gate driving circuits are configured to drive the amplitude modulation sub-circuits, and the second-type gate driving circuits are configured to drive the pulse width modulation sub- circuits (par 0069; discloses Each of the first to third pixels SP1, SP2, and SP3 may be connected to the scan initialization line GIL, the scan write line GWL, the scan control line GCL, the sweep line SWPL, the PWM emission line PWEL, and the PAM emission line PAEL. Par 0072; discloses The gate driver 110 may include a first scan signal output unit 111, a second scan signal output unit 112, a sweep signal output unit 113, and an emission signal output unit 114; see par 0071 as well); and fixed-voltage signal lines of the display panel comprise first-type fixed-voltage signal lines and second-type fixed-voltage signal lines, the first-type fixed-voltage signal lines are electrically connected to the first-type gate driving circuits, and the second-type fixed-voltage signal lines are electrically connected to the second-type gate driving circuits (par 0079; discloses The power supply unit 400 may commonly supply a first PAM data voltage to the first PAM data lines RDL, commonly supply a second PAM data voltage to the second PAM data lines GDL, and commonly supply a third PAM data voltage to the third PAM data lines BDL. The power supply unit 400 may generate a plurality of power voltages and output them to the display panel 100. Par 0080; discloses The power supply unit 400 may supply a first power voltage VDD1, a second power voltage VDD2, a third power voltage VSS, an initialization voltage VINT, a gate-on voltage VGL, and a gate-off voltage VGH to the display panel 100. The first power voltage VDD1 and the second power voltage VDD2 may be high-potential voltages for driving the light emitting elements of the first to third pixels SP1, SP2, and SP3. The third power voltage VSS may be a low-potential voltage for driving the light emitting elements of the first to third pixels SP1, SP2, and SP3. The initialization voltage VINT and the gate-off voltage VGH may be applied to each of the first to third pixels SP1, SP2, and SP3, and the gate-on voltage VGL and the gate-off voltage VGH may be applied to the gate driver 110.);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO as modified by LEE and Kim to incorporate the teachings of JEONG to form pixel comprising PWM circuit and PAM circuit that is controlled via the gate driver and data driver in order to achieve a display device capable of increasing a constant current driving region in a low grayscale region and also capable of improving expression of low gray levels.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over JO et al (US Pub 2021/0056909) in view of LEE et al (US Pub 2022/0114936), Kim et al (US Pub 2020/0265785), JEONG et al (US Pub 2023/0186836) and JEONG et al (US Pub 2023/0082959) referred to as JEONG959.
With respect to claim 19, JO as modified by LEE, Kim and JEONG don’t expressly disclose wherein the static electricity protection circuits of the display panel comprise first-type static electricity protection circuits and second- type static electricity protection circuits, the first-type static electricity protection circuits are electrically connected to the trigger traces connected to the first-type gate driving circuits, and the second-type static electricity protection circuits are electrically connected to trigger traces connected to the second-type gate driving circuits; and the first-type static electricity protection circuits are electrically connected to the first-type static electricity fixed-voltage signal lines, and the second-type static electricity protection circuits are electrically connected to the second-type fixed-voltage signal lines;
In the same field of endeavor, JEONG959 discloses a display device and control method (see abstract); JEONG959 discloses wherein the static electricity protection circuits of the display panel comprise first-type static electricity protection circuits and second- type static electricity protection circuits, the first-type static electricity protection circuits are electrically connected to the trigger traces connected to the first-type gate driving circuits, and the second-type static electricity protection circuits are electrically connected to trigger traces connected to the second-type gate driving circuits (par 0109; discloses The antistatic area ESA may include a plurality of electrostatic discharging circuits ESD. The plurality of electrostatic discharging circuits ESD may overlap the first to third pixels SP1, SP2, and SP3 of the first pixel row PROWL The electrostatic discharging circuit ESD may protect a fan-out line FOL, a demultiplexer DMX, and the pixel circuit PC from static electricity; par 0121; discloses The electrostatic discharging circuit ESD may be disposed adjacent to the fan-out line FOL. Some of the electrostatic discharging circuits ESD may be connected between the fan-out line FOL and a gate-off voltage line VGHL, and some others of the electrostatic discharging circuits ESD may be connected between the fan-out line FOL and a gate-on voltage line VGLL.); and the first-type static electricity protection circuits are electrically connected to the first-type static electricity fixed-voltage signal lines, and the second-type static electricity protection circuits are electrically connected to the second-type fixed-voltage signal lines (par 0121; discloses The electrostatic discharging circuit ESD may be disposed adjacent to the fan-out line FOL. Some of the electrostatic discharging circuits ESD may be connected between the fan-out line FOL and a gate-off voltage line VGHL, and some others of the electrostatic discharging circuits ESD may be connected between the fan-out line FOL and a gate-on voltage line VGLL. The electrostatic discharging circuit ESD may be connected to the portion between the first and second line resistors R1 and R2 of the fan-out line FOL, but the disclosure is not limited thereto. Therefore, the electrostatic discharging circuit ESD may dissipate static electricity flowing from the outside to prevent the static electricity from flowing into the display area DA);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by JO as modified by LEE, Kim and JEONG to incorporate the teachings of JEONG959 to dispose electrostatic circuits around the display panel in order to dissipate static electricity flowing from the outside to prevent the static electricity from flowing into the display area DA, hence improving display quality.
Response to Arguments
Applicant's arguments filed with respect to claim 1, 20 have been fully considered but they are not persuasive and do not put the application in condition for allowance.
With respect to claims 1 and 20 applicant’s representatives argued that the cited references fail to teach the claimed invention. More specifically applicant’s representative argued that cited reference JO discloses display area and non-display area and the traces are disposed in the non-display area.
However, examiner respectfully disagrees because the language of the claimed inventions are broad and the broad reasonable interpretation of the claim language reads on the disclosure of the cited references. The term first area and second in the claims 1 and 20 are broad and can be interpreted to read on the disclosure of the cited reference. Further the claim limitation expressly mentions that that second area includes no pixel circuits which allows one to interpret the second area may correspond to non-display area of the panel. Therefore, the broad reasonable interpretation of claimed invention reads on the disclosure of the cited references.
Further JO discloses the plurality of pixels in the display panel are arranged in plurality of columns and plurality of rows that intersect each other (see fig. 1).
Furthermore, the traces connected to gate driver is also a broad limitation and traces could be interpreted to read on any lines such as scan lines, control lines, clock lines that are connected to gate drivers. Jo discloses plurality of scan lines that are connected to gate driver and extends in the pixel area to connect to each pixels (JO; fig. 1; discloses plurality scan lines overlap the plurality of pixels);
Similarly, light emitting device columns and light emitting device rows are boards terms and could be interpreted as pixel circuit, gate lines, data lines, etc.; Kim discloses plurality of traces such as power lines, clock lines that extend towards the panel and crosses the plurality of gate lines formed in the panel and are connected to the gate driver (Kim; fig. 3; plurality of lines 134a connect to gate driver 131 and overlaps the pixels gate lines in the display panel; par 0083; discloses A gate driver 130 (see FIG. 3) composed of a plurality of G-TFTs GT may be elongated in the column direction Y and overlap the pixel PXL);
Therefore the limitation of the claimed invention is broad and allows one to interpret these limitation differently and the disclosure of the cited references reads on the broad reasonable interpretation. Hence the rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SUJIT SHAH/ Examiner, Art Unit 2624
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