MULTI-TIER NONVOLATILE MEMORY WITH FAILURE AND ERROR MITIGATION

Application No. 19/075,844

• Filed: Mar 11, 2025
• Examiner: YANG, HAN
• Art Unit: 2824
• Tech Center: 2800 — Semiconductors & Electrical Systems
• Assignee: SanDisk Technologies Inc.
• OA Round: 1 (Non-Final)

Office Action

Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

DETAILED ACTION
Claim Rejections - 35 USC § 112
1. Claims 2-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: claim 2 and claim 3 claimed first and second number but the claim did not specific number of what? The examiner not sure they are first/second number of program pulses or wordlines? Please be specific.

Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.

3. Claim(s) 1-20, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al (Pub. No.: US 2012/0250426).
4. Regarding independent claim 1, Lu et al teaches one or more control circuits (Fig. 1, #110) configured to connect to a plurality of nonvolatile memory cells (Fig. 1, #126) in NAND strings (Fig. 1, #126, Fig. 7) that are coupled to word lines (Fig. 11C, WL0-WL10 for example), wherein the one or more control circuits (Fig. 1, #110) are configured to: apply a first number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup1 SB1, SB5 in Fig. 11C for example) to program nonvolatile memory cells (Fig. 1, #126) of a first set (Fig. 11C WL_group1 (WL0-WL2), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) to a target data state according to a first program scheme (Fig. 11A2, for WL_group1 in Fig. 11C), apply a second number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup2 SB1, SB5 in Fig. 11C for example) to program nonvolatile memory cells (Fig. 1, #126) of a second set (Fig. 11C WL_group2 (WL3-WL5), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) to the target data state according to a second program scheme (Fig. 11A2, for WL_group2 in Fig. 11C), the second set (Fig. 11C WL_group2 (WL3-WL5), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) includes one or more edge word line or joint word line (Fig. 11C, WL3 as an example, where WL3 in WL_group 2 is a joint WL since WL3 is adjacent to WL2 in WL_group1) and the second number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup2 SB1, SB5 in Fig. 11C for example) is greater than (Fig. 11B, #1113, where WL_group initial Vpgm=acquired Vpgm + offset voltage, and the offset voltage of WL_group2 is larger than offset voltage of WL_group1 in SB1/SB5) the first number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup1 SB1, SB5 in Fig. 11C for example).
5. Regarding claim 2, Lu et al teaches the first number is one and the second number is two or more (see Fig. 11C).
6. Regarding claim 3, Lu et al teaches the first number is more than one and the second number is more than the first number by at least two (see Fig. 11C).
7. Regarding claim 4, Lu et al teaches the NAND strings (Fig. 1, #126, Fig. 7) are formed in a lower tier (Fig. 11C, WL_group1 for example) and an upper tier (Fig. 11C, WL_group2 for example) that are joined along an interface, the second set (Fig. 11C WL_group2 (WL3-WL5), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) consists of an edge word line (Fig. 11C, WL0) at the bottom of the lower tier (Fig. 11C, WL_group1 for example), a first joint word line (Fig. 11C, WL3 as an example, where WL3 in WL_group 2 is a joint WL since WL3 is adjacent to WL2 in WL_group1) at the top of the lower tier (Fig. 11C, WL_group1) and a second joint word line (Fig. 11C, WL3 as an example, where WL3 in WL_group 2 is a joint WL since WL3 is adjacent to WL2 in WL_group1) at the bottom of the upper tier (Fig. 11C, WL_group1).
8. Regarding claim 5, Lu et al teaches the first set (Fig. 11C WL_group1 (WL0-WL2), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) consists of all word lines (Fig. 11C, WL0-WL10 for example) coupled to the NAND strings (Fig. 1, #126, Fig. 7) except the edge word line (Fig. 11C, WL0), the first joint word line (Fig. 11C, WL3 as an example, where WL3 in WL_group 2 is a joint WL since WL3 is adjacent to WL2 in WL_group1) and the second joint word line (Fig. 11C, WL3 as an example, where WL3 in WL_group 2 is a joint WL since WL3 is adjacent to WL2 in WL_group1).
9. Regarding claim 6, Lu et al teaches the NAND strings (Fig. 1, #126, Fig. 7) are formed in a lower tier (Fig. 11C, WL_group1), a middle tier (Fig. 11C, WL_group2) and an upper tier (Fig. 11C, WL_group3), the lower tier (Fig. 11C, WL_group1) is joined to the middle tier (Fig. 11C, WL_group2) along a first interface (Fig. 11C) and the upper tier (Fig. 11C, WL_group3) joined to the middle tier (Fig. 11C, WL_group2) along a second interface (Fig. 11C), the second set (Fig. 11C WL_group2 (WL3-WL5), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) consists of an edge word line (Fig. 11C, WL0) at the bottom of the lower tier (Fig. 11C, WL_group1), a first joint word line (Fig. 11C, WL2 as an example) at the top of the lower tier (Fig. 11C, WL_group1), a second joint word line (Fig. 11C, WL3 as an example, where WL3 in WL_group 2 is a joint WL since WL3 is adjacent to WL2 in WL_group1) at the bottom of the middle tier (Fig. 11C, WL_group2), a third joint word line (Fig. 11C, WL5) at the top of the middle tier (Fig. 11C, WL_group2) and a fourth joint word line (Fig. 11C, WL6) at the bottom of the upper tier (Fig. 11C, WL_group3).
10. Regarding claim 7, Lu et al teaches the first set (Fig. 11C WL_group1 (WL0-WL2), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) consists of all word lines (Fig. 11C, WL0-WL10 for example) coupled to the NAND strings (Fig. 1, #126, Fig. 7) except the edge word line (Fig. 11C, WL0) and the first, second, third and fourth joint word line (Fig. 11C, WL2, WL3, WL5, WL6) (Fig. 11C, WL0-WL10 for example).
11. Regarding claim 8, Lu et al teaches the program pulses (Fig. 11A2, #1106) of the first program scheme (Fig. 11A2, for WL_group1 in Fig. 11C) have a first voltage (Fig. 11A2, initial Vpgm), the program pulses (Fig. 11B, acquired Vpgm + off set voltage) of the second program scheme (Fig. 11A2, for WL_group2 in Fig. 11C) have a second voltage pulses (Fig. 11B, acquired Vpgm + off set voltage) and the second voltage pulses (Fig. 11B, acquired Vpgm + off set voltage) is less than (see Fig.11D) the first voltage (Fig. 11A2, initial Vpgm).
12. Regarding claim 9, Lu et al teaches the first program scheme (Fig. 11A2, for WL_group1 in Fig. 11C) includes applying the first number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup1 SB1, SB5 in Fig. 11C for example) over a first time period (Fig. 11A2) and the second program scheme (Fig. 11A2, for WL_group2 in Fig. 11C) includes applying the second number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup2 SB1, SB5 in Fig. 11C for example) over a second time period (Fig. 11B) that is longer than (Fig. 11C) the first time period (Fig. 11A2).
13. Regarding independent claim 10, Lu et al teaches a method of programming a plurality of nonvolatile memory cells (Fig. 1, #126) in a memory structure that includes NAND strings (Fig. 1, #126, Fig. 7) extending through two or more tiers (Fig. 11C, WL_group1-WL_group4) with word lines (Fig. 11C, WL0-WL10 for example) of the two or more tiers (Fig. 11C, WL_group1-WL_group4) coupled to the plurality of nonvolatile memory cells (Fig. 1, #126), comprising: applying a first number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup1 SB1, SB5 in Fig. 11C for example) to a first set (Fig. 11C WL_group1 (WL0-WL2), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) to program memory cells of the first set (Fig. 11C WL_group1 (WL0-WL2), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) to a target data state according to a first program scheme (Fig. 11A2, for WL_group1 in Fig. 11C); identifying a second set (Fig. 11C WL_group2 (WL3-WL5), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) according to their locations within the two or more tiers (Fig. 11C, WL_group1-WL_group4); and applying a second number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup2 SB1, SB5 in Fig. 11C for example) that is greater than (Fig. 11B, #1113, where WL_group initial Vpgm=acquired Vpgm + offset voltage, and the offset voltage of WL_group2 is larger than offset voltage of WL_group1 in SB1/SB5) the first number to program memory cells of the second set (Fig. 11C WL_group2 (WL3-WL5), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) to the target data state according to a second program scheme (Fig. 11A2, for WL_group2 in Fig. 11C).
14. Regarding claim 11, Lu et al teaches applying the first number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup1 SB1, SB5 in Fig. 11C for example) consists of applying a single pulse (Fig. 11C, WL0, offset voltage) and applying the second number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup2 SB1, SB5 in Fig. 11C for example) consists of applying two or more pulses (see Fig. 11C, WL3-WL5, offset voltages).
15. Regarding claim 12, Lu et al teaches applying the first number of pulses (Fig. 11A2, #1105) consists of applying two or more pulses (See Fig. 11C, SB1, SB2) and applying the second number of pulses (Fig. 11B, #1113) consists of applying more than the first number of pulses (Fig. 11C, SB1, SB2, SB3).
16. Regarding claim 13, Lu et al teaches identifying the second set (Fig. 11C WL_group2 (WL3-WL5), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) includes identifying at least one edge word line (Fig. 11C, WL0) at the bottom of a lowest tier (Fig. 11C, WL_group1) of the two or more tiers (Fig. 11C, WL_group1-WL_group4).
17. Regarding claim 14, Lu et al teaches identifying the second set (Fig. 11C WL_group2 (WL3-WL5), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) further includes identifying at least one joint word line (Fig. 11C, WL3 as an example, where WL3 in WL_group 2 is a joint WL since WL3 is adjacent to WL2 in WL_group1) at the top of the lowest tier (Fig. 11C, WL_group1) of the two or more tiers (Fig. 11C, WL_group1-WL_group4).
18. Regarding claim 15, Lu et al teaches identifying the second set (Fig. 11C WL_group2 (WL3-WL5), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) further includes identifying at least one joint word line (Fig. 11C, WL3 as an example, where WL3 in WL_group 2 is a joint WL since WL3 is adjacent to WL2 in WL_group1) at the bottom of a tier (Fig. 11, WL_group2) above the lowest tier (Fig. 11, WL_group1) of the two or more tiers (Fig. 11C, WL_group1-WL_group4).
19. Regarding claim 16, Lu et al teaches the program pulses (Fig. 11A, #1106 initial Vpgm) of the first program scheme (Fig. 11A2, for WL_group1 in Fig. 11C) have a first voltage (Fig. 11A2, initial Vpgm), the program pulses of the second program scheme (Fig. 11A2, for WL_group2 in Fig. 11C) have a second voltage (Fig. 11A2, acquired Vpgm + Voffset) and the second voltage (Fig. 11A2, acquired Vpgm + Voffset) is less than (see Fig. 11D) the first voltage (Fig. 11A2, initial Vpgm).
20. Regarding claim 17, Lu et al teaches the program pulses of the first program scheme (Fig. 11A2, for WL_group1 in Fig. 11C) have a first pulse width (Fig. 11A2), the program pulses of the second program scheme (Fig. 11A2, for WL_group2 in Fig. 11C) have a second pulse width (Fig. 11B) and the second pulse width (Fig. 11B) is less than the first pulse width (Fig. 11A2).
21. Regarding independent claim 18, Lu et al teaches a plurality of nonvolatile memory cells (Fig. 1, #126) arranged in NAND strings (Fig. 1, #126, Fig. 7) that extend through two or more tiers (Fig. 11C, WL_group1-WL_group4) and connect to word lines (Fig. 11C, WL0-WL10 for example) in each tier; and means for selecting a program scheme (Fig. 11A) for a word line (Fig. 11C, WL0 for example) according to word line location in a respective tier of the two or more tiers (Fig. 11C, WL_group1-WL_group4), applying a first number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup1 SB1, SB5 in Fig. 11C for example) to program nonvolatile memory cells (Fig. 1, #126) of a first set (Fig. 11C WL_group1 (WL0-WL2), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) located in the middle of respective tiers (Fig. 11C, WL_group1-WL_group4) to a target data state according to a first program scheme (Fig. 11A2, for WL_group1 in Fig. 11C), applying a second number of program pulses (Fig. 11A2, #1107a apply initial Vpgm on WLgroup2 SB1, SB5 in Fig. 11C for example) that is greater than (Fig. 11B, #1113, where WL_group initial Vpgm=acquired Vpgm + offset voltage, and the offset voltage of WL_group2 is larger than offset voltage of WL_group1 in SB1/SB5) the first number to program nonvolatile memory cells (Fig. 1, #126) of a second set (Fig. 11C WL_group2 (WL3-WL5), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) located at or near boundaries (Fig. 11C, WL_group 3 can be first set WLs and WL_group4 would be second set WLs which has same functionality as WL_group1 vs WL_group2) of respective tiers (Fig. 11C, WL_group1-WL_group4) to the target data state according to a second program scheme (Fig. 11A2, for WL_group2 in Fig. 11C).
22. Regarding claim 19, Lu et al teaches the plurality of nonvolatile memory cells (Fig. 1, #126) are located in a memory die (Fig. 1) and the means for selecting is located in a control die (Fig. 1, #122) that is coupled to the memory die (Fig. 1, #108).
23. Regarding claim 20, Lu et al teaches the two or more tiers (Fig. 11C, WL_group1-WL_group4) includes at least a first tier (Fig. 11C, WL_group1) and a second tier (Fig. 11C, WL_group2) that are physically (see Fig. 11C) connected along a joint and the second set (Fig. 11C WL_group2 (WL3-WL5), SB1/SB5 for example) of word lines (Fig. 11C, WL0-WL10 for example) includes at least a word line (Fig. 11C, WL2) in the first tier (Fig. 11C, WL_group1) that is nearest to the joint and a word line (Fig. 11C,WL3) in the second tier (Fig. 11C, WL_group2) that is nearest to the joint (Fig. 11C).

Conclusion

24. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, CHOI et al (Pub. No: US 2026/0148777).
CHOI et al (Pub. No: US 2026/0148777) shows first set wordline voltage and second set wordline voltages.
25. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is [phone]. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].
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HY
09/16/2026
/HAN YANG/
Primary Examiner, Art Unit 2824

Prosecution Timeline

• Mar 11, 2025: Application Filed
• Sep 18, 2026: Non-Final Rejection mailed — §102, §112 (current)