DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“an external bus connecting unit for connecting the data transferring unit, the local memory, and the command list processing unit to an external memory” in claim 1.
“the data transferring unit transfers data which are conditions of calculation stored in the external memory to the local memory” in claim 1.
“the command list processing unit reads the list of commands from the local memory” in claim 1.
“the command list processing unit… generates a command to execute calculation by a calculation processing unit while transferring the data from the external memory to the local memory” in claim 1.
“the calculation processing unit executes the calculation” in claim 1.
“the calculation processing unit… processing the data” in claim 1.
“the command list processing unit… generates a command to execute calculation… when …the transfer of one unit of data… from the external memory to the local memory is completed” from claim 2.
“the transfer size monitoring unit detects that the transfer of one unit of data… from the external memory to the local memory is completed” from claim 2.
“the command list processing unit rearranges and links multiple transfer commands… into multiple transfer commands of the same attribute for consecutive addresses inside the local memory” from claim 3.
“the command list processing unit… requests the transfer of the data to the external bus connecting unit by issuing the transfer commands” from claim 3.
“the command list processing unit… generates a command to execute calculation by the calculation processing unit when the transfer of the required amount of data to the local memory is completed” from claim 3.
“the command list processing unit… generates a command to start the transfer of the data being processed from the local memory to the external memory during the calculation by the calculation processing unit” in claim 4.
“a second transfer size monitoring unit… which generates a command to execute calculation by the calculation processing unit when… the transfer of one unit of data, which can be computed by the calculation processing unit, from the local memory to the second local memory is completed” in claim 6.
“a second transfer size monitoring unit… detects that the transfer of one unit of data, which can be computed by the calculation processing unit, from the local memory to the second local memory is completed” in claim 6.
“a mechanism to determine the access range” in claim 7.
“the command list processing unit generates a command to execute calculation by the calculation processing unit when… transfer of one unit of data, which can be computed by the calculation processing unit, from the external memory to the local memory is completed” in claim 7.
“command list processing unit generates a command to execute calculation by the calculation processing unit when the transfer size monitoring unit detects that the transfer of a unit of data, which can be calculated by the calculation processing unit, from the external memory to the local memory is complete” in claim 8.
“the data transferring unit specifies a source and destination for the transfer of two or more sets of data, performs the transfer of each set of data in divided portions in sequence, and independently specifies the amount of data to be divided for each set” in claim 9.
“an external bus connecting unit connects a local memory, a data transferring unit, and a command list processing unit to an external memory” in claim 11.
“the data transferring unit transfers data” in claim 11.
“the command list processing unit reads the list of commands from the local memory” in claim 11.
“the command list processing unit… generates a command to execute calculation by a calculation processing unit while transferring the data from the external memory to the local memory” in claim 11.
“the calculation processing unit executes the calculation” in claim 11.
“the calculation processing unit… processing the data” in claim 11.
“the command list processing unit generates a command to execute calculation… when …the transfer of one unit of data… from the external memory to the local memory is completed” from claim 12.
“the transfer size monitoring unit detects that the transfer of one unit of data… from the external memory to the local memory is completed” from claim 2.
“the command list processing unit rearranges and links multiple transfer commands… into multiple transfer commands of the same attribute for consecutive addresses inside the local memory” from claim 13.
“the command list processing unit… issues the transfer commands to request the transfer of data by the external bus connecting unit” from claim 13.
“the command list processing unit… generates a command to execute calculation by the calculation processing unit when the transfer of the required amount of data to the local memory is completed” from claim 13.
“the data transferring unit specifies a source and destination for the transfer of two or more sets of data, performs transferring of each set of data in divided portions in sequence, and independently specifies the amount of data to be divided for each set” in claim 9.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. In particular:
In claim 1, “an external bus connecting unit for connecting the data transferring unit, the local memory, and the command list processing unit to an external memory” is interpreted as covering the structure of a bus bridge [pg. 10, lines 5-6].
In claim 1 “the data transferring unit transfers data which are conditions of calculation stored in the external memory to the local memory” is interpreted as covering the structure of a direct memory access controller (DMAC) [pg. 9, lines 14-15].
In claim 1, “the command list processing unit reads the list of commands from the local memory” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. For a computer-implemented means plus function limitation, the specification must additionally disclose an algorithm for performing the claimed function, and the structure is additionally interpreted to cover the disclosed algorithm. However, "For a computer-implemented means-plus-function claim limitation invoking 35 U.S.C. 112(f) the Federal Circuit has stated that 'a microprocessor can serve as structure for a computer-implemented function only where the claimed function is ‘coextensive’ with a microprocessor itself'…. Examples of such coextensive functions are ‘receiving’ data, ‘storing’ data, and ‘processing’ data—the only three functions on which the Katz court vacated the district court’s decision and remanded for the district court to determine whether disclosure of a microprocessor was sufficient." [MPEP 2181(II)(B): ¶3]. In the present case, the limitation is computer implemented and the function of reading data (the list of commands from the local memory) is considered coextensive with the functioning of the computer and an algorithm for performing the computer-implemented function is therefore not required.
In claim 1, “the command list processing unit… generates a command to execute calculation by a calculation processing unit while transferring the data from the external memory to the local memory” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 10, lines 13-17], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 1, “the calculation processing unit executes the calculation” is interpreted to cover the structure of a generic computer processor/microprocessor with instructions for performing the claimed function [pg. 8: lines 22-23]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 8, last line – continued onto pg. 9], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 1, “the calculation processing unit… processing the data” in claim 1 is interpreted to cover the structure of a generic computer processor/microprocessor for performing the claimed function [pg. 8: lines 22-23]. As the limitation is computer implemented and the function of processing data is considered coextensive with the functioning of the computer, an algorithm for performing the computer-implemented function is not required.
In claim 2, “the command list processing unit… generates a command to execute calculation… when… the transfer of one unit of data… from the external memory to the local memory is completed” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 16, lines 19-24], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 2, “the transfer size monitoring unit detects that the transfer of one unit of data… from the external memory to the local memory is completed” is interpreted to cover a generic computer processor/microprocessor. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 15, lines 21-24], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 3, “the command list processing unit rearranges and links multiple transfer commands… into multiple transfer commands of the same attribute for consecutive addresses inside the local memory” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 17, lines 20-25], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 3, “the command list processing unit… requests the transfer of the data to the external bus connecting unit by issuing the transfer commands” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 17, line 25 – pg. 18, line 2], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 3, “the command list processing unit… generates a command to execute calculation by the calculation processing unit when the transfer of the required amount of data to the local memory is completed” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 18, lines 2-5], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 4, “the command list processing unit… generates a command to start the transfer of the data being processed from the local memory to the external memory during the calculation by the calculation processing unit” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 19, lines 8-12], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 6, “a second transfer size monitoring unit… which generates a command to execute calculation by the calculation processing unit when… the transfer of one unit of data, which can be computed by the calculation processing unit, from the local memory to the second local memory is completed” was searched for in the specification for a corresponding structure, but was not found. For example, the specification appears to disclose that the command list processing unit generates a command (rather than the second transfer size monitoring unit) to execute calculation by the calculation processing unit when the second data transferring unit detects the completion of the transfer of one unit of data. Accordingly, the corresponding function is not clearly linked to the claimed structure for performing the claimed function and the corresponding structure for performing the limitation cannot be determined.
In claim 6, “a second transfer size monitoring unit… detects that the transfer of one unit of data, which can be computed by the calculation processing unit, from the local memory to the second local memory is completed” is interpreted to cover a generic computer processor/microprocessor. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 15, lines 21-24], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 7, “a mechanism to determine the access range” was searched for in the specification for a corresponding structure, but was not found. For example, the specification merely repeats the function without a specific structure clearly linked to the function for performing the claimed function other than “mechanism” [pg. 18: lines 18-25]. Accordingly, the corresponding structure for performing the claimed function could not be found.
In claim 7, “the command list processing unit generates a command to execute calculation by the calculation processing unit when the mechanism to determine the access range detects that the transfer of one unit of data, which can be computed by the calculation processing unit, from the external memory to the local memory is completed” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 18, lines 19-25], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 8, “command list processing unit generates a command to execute calculation by the calculation processing unit when the transfer size monitoring unit detects that the transfer of a unit of data, which can be calculated by the calculation processing unit, from the external memory to the local memory is complete” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 18, lines 1-5], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 9, “the data transferring unit specifies a source and destination for the transfer of two or more sets of data, performs the transfer of each set of data in divided portions in sequence, and independently specifies the amount of data to be divided for each set” in interpreted to cover the structure of a direct memory access controller (DMAC) [pg. 19, lines 16-21].
In claim 11, “an external bus connecting unit connects a local memory, a data transferring unit, and a command list processing unit to an external memory” is interpreted as covering the structure of a bus bridge [pg. 10, lines 5-6].
In claim 11 “the data transferring unit transfers data” is interpreted as covering the structure of a direct memory access controller (DMAC) [pg. 9, lines 14-15].
In claim 11, “the command list processing unit reads the list of commands from the local memory” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. In the present case, the limitation is computer implemented and the function of reading data (the list of commands from the local memory) is considered coextensive with the functioning of the computer and an algorithm for performing the computer-implemented function is therefore not required.
In claim 11, “the command list processing unit… generates a command to execute calculation by a calculation processing unit while transferring the data from the external memory to the local memory” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 10, lines 13-17], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 11, “the calculation processing unit executes calculation” is interpreted to cover the structure of a generic computer processor/microprocessor with instructions for performing the claimed function [pg. 8: lines 22-23]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 8, last line – continued onto pg. 9], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 11, “the calculation processing unit… processes the data” in claim 1 is interpreted to cover the structure of a generic computer processor/microprocessor for performing the claimed function [pg. 8: lines 22-23]. As the limitation is computer implemented and the function of processing data is considered coextensive with the functioning of the computer, an algorithm for performing the computer-implemented function is not required.
In claim 12, “the command list processing unit generates a command to execute calculation… when… the transfer of one unit of data… from the external memory to the local memory is completed” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 16, lines 19-24], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 12, “the transfer size monitoring unit detects that the transfer of one unit of data… from the external memory to the local memory is completed” is interpreted to cover a generic computer processor/microprocessor. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 15, lines 21-24], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 13, “the command list processing unit rearranges and links multiple transfer commands… into multiple transfer commands of the same attribute for consecutive addresses inside the local memory” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 17, lines 20-25], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 13, “the command list processing unit… issues the transfer commands to request the transfer of data by the external bus connecting unit” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 17, line 25 – pg. 18, line 2], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 13, “the command list processing unit… generates a command to execute calculation by the calculation processing unit when the transfer of the required amount of data to the local memory is completed” is interpreted as covering the structure of a generic purpose computer/processor [pg. 10, lines 17-18]. Furthermore, the specification was reviewed for the disclosure of a sufficient algorithm for performing the claimed function as required by [MPEP 2181(II)(B)]. Although the specification repeats the claimed function in [pg. 18, lines 2-5], “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps.” [MPEP 2181(II)(B) -¶12]. Accordingly, a sufficient algorithm for performing the claimed function was not found.
In claim 14, “the data transferring unit specifies a source and destination for the transfer of two or more sets of data, performs transferring of each set of data in divided portions in sequence, and independently specifies the amount of data to be divided for each set” in interpreted to cover the structure of a direct memory access controller (DMAC) [pg. 19, lines 16-21].
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Objections
Claims 1-15 are objected to because of the following informalities:
Claim 1 recites, “transfers data which are conditions”, which as best understood by the Examiner in light of the specification should be amended to recite, “transfers data that are conditions”.
Claim 1 recites, “wherein the calculation processing unit… processing the data”, which as best understood by the Examiner in light of the specification should be amended to recite, “wherein the calculation processing unit… processes the data”.
Claims 2-4, 6-8 and 12-13 recite “a command to execute calculation”, which as best understood by the Examiner in light of the specification should be amended to recite, “[[a]]the command to execute calculation”.
Claims 2, 6-8, and 12 recite, “transfer of one [“a” in the case of claim 12] unit of data, which can be calculated by the calculation processing unit, from the external memory”, which as best understood by the Examiner in light of the specification should be amended to recite, “transfer of one unit of data[[,]] that can be calculated by the calculation processing unit[[,]] from the external memory”.
Claim 3 should be rearranged for readability to recite,
wherein the command list processing unit:
rearranges and links multiple transfer commands, which transfer a size of data larger than one unit that can be calculated by the calculation processing unit, into multiple transfer commands of the same attribute for consecutive addresses inside the local memory,
requests the transfer of the data to the external bus connecting unit by issuing the transfer commands, and
generates a command to execute calculation by the calculation processing unit when the transfer of the required amount of data to the local memory is completed.
Claims 3 and 13 recites, “multiple transfer commands, which transfer a size of data larger than one unit that can be calculated by the calculation processing unit, into multiple transfer commands”, which as best understood by the Examiner in light of the specification should be amended to recite, “multiple transfer commands[[,]] that transfer a size of data larger than one unit that can be calculated by the calculation processing unit, into multiple transfer commands”.
Claim 4 recites, “the transfer of the data being processed from the local memory to the external memory”, which as best understood by the Examiner in light of the specification should be amended to recite, “[[the]] transfer of the data being processed from the local memory to the external memory”.
Claim 8 recites, “The information processing device according to claim 1 comprising multiple data transferring units”, which as best understood by the Examiner in light of the specification should be amended to recite, “The information processing device according to claim 1 further comprising multiple data transferring units”.
Claim 8 further recites, “wherein command list processing unit”, which as best understood by the Examiner in light of the specification should be amended to recite, “wherein the command list processing unit”.
Claims 9 and 14 recite, “of each set of data” and “for each set”, which as best understood by the Examiner in light of the specification should be amended to recite, “of each set of data of the two or more sets of data” and “for each set of data of the two or more sets of data”, respectively.
Claims 9 and 14 also recite, “specifies the amount of data”, which as best understood by the Examiner in light of the specification should be amended to recite, “specifies [[the]]an amount of data”.
Claim 11 recites, “transfers data, which are conditions”, which as best understood by the Examiner in light of the specification should be amended to recite, “transfers data[[,]] that are conditions”.
Claim 13 recites, “processing unit e into multiple transfer commands”, which as best understood by the Examiner in light of the specification should be amended to recite, “processing unit [[e]] into multiple transfer commands”.
Claims 2-10 and 11-15 are objected to for failing to correct the deficiencies of a base claim from which they depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claims 1-15:
"To satisfy the definiteness requirement under 35 U.S.C. 112(b) or 35 U.S.C. 112, second paragraph, the written description must clearly link or associate the corresponding structure, material, or acts to the claimed function. Telcordia Techs., Inc. v. Cisco Systems, Inc., 612 F.3d 1365, 1376, 95 USPQ2d 1673, 1682 (Fed. Cir. 2010). A rejection under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph is appropriate if the written description fails to link or associate the disclosed structure, material, or acts to the claimed function, or if there is no disclosure (or insufficient disclosure) of structure, material, or acts for performing the claimed function. Donaldson, 16 F.3d at 1195, 29 USPQ2d at 1850." [MPEP 2181(III), ¶1]. The claims in the instant application lack a clearly linked structure for performing the claimed functions identified in limitations (d-g, g-l, n, p-q, v-w & y-cc) in the claim interpretation section above and interpreted under 35 U.S.C. §112(f) because the written description does not disclose a sufficient algorithm for performing the claimed function. Accordingly, the claims are indefinite [MPEP 2181(II)(B)-(II)(C)]. "For a computer-implemented 35 U.S.C. 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite under 35 U.S.C. 112(b)." [MPEP 2181(II)(B) - ¶1]. Furthermore, the claims in the instant application lack a clearly linked structure for performing the claimed functions identified in limitations (m & o) according to the interpretation performed in the 35 U.S.C. §112(f) the claim interpretation section above, as they do not disclose a clearly linked structure for performing the claimed function, the claims are indefinite. [MPEP 2181(II)(C)].
Regarding claims 1-10:
Claims 1-10 are additionally rejected because the claims are directed to an apparatus (“An information processing device…”), but the body of the claims are a series of active method steps including: “transfers”, “stores”, “reads”, “executes”, “processing”, etc. that describe operations being performed by the information processing device and its structures rather than structural features or functional capabilities of the claimed information processing device or its structures. As written, these limitations require the information processing device and its structures to actually perform sequential acts rather than merely define the information processing device’s structure or its structure’s operative capabilities.
The grammatical structure therefore blurs the distinction between a system/apparatus and a method of operating that system. It is unclear whether the claim is intended to cover (1) a structural apparatus configured to be capable of performing the recited operations, (2) a method in which the information processing device and its structures actually perform the recited “transfer”, “store”, “read”, “execute”, etc., steps, or (3) a hybrid apparatus-method claim, which is not permitted because it is unclear when infringement occurs (i.e., when the apparatus is produced or only when the apparatus is actually operated) [MPEP 2173.05(p)].
Because the claim recites both structural components and process steps, the scope of the claim is uncertain and the scope of the claim cannot be determined and the claim is indefinite.
The Examiner suggests amending the action step verbs in the claim to instead recite capabilities that the linked structures are “configured to” perform. The following list is a non-exhaustive list of limitations in the claim that should be amended to recite “configured to” limitations (for example, be amended to recite “the data transferring unit is configured to transfer data”, “the local memory is configured to store the data”, or “the calculation processing unit is configured to execute the calculation and process the data”):
In claim 1: transfers, stores, reads, generates, executes, and processing.
In claims 2, 4, 6-8: generates.
In claim 3: rearranges, links, requests, generates.
In claim 5: while the core is executing… another core executes…
In claim 9: specifies, performs the transfer, independently specifies.
Regarding claim 1 and analogous claim 11:
Claims 1 and 11 recite, “the command list processing unit… generates… while transferring the data from the external memory to the local memory”, which appears to indicate that the command list processing unit performs the transferring of the data from the external memory to the local memory. However, the claim previously recites “the data transferring unit transfers data… stored in the external memory to the local memory”, which appears to indicate that the data transferring unit performs the transferring of data from the external memory to the local memory. Accordingly, it is unclear whether (1) both the command list processing unit and the data transferring unit perform the transferring of the data from the external memory to the local memory, or (2) whether “while transferring the data from the external memory to the local memory” was intended to refer to the data transferring unit performing the data transfer and not the command list processing unit. Accordingly, the scope of the claims cannot be determined and the claims are indefinite.
Claims 1 and 11 recite, “while transferring the data from the external memory to the local memory”, but previously recite a steps of (1) reading the list of commands from the local memory (2) generating a command and (3) executing calculation by the calculation processing unit. From the grammatical structure of the claim, it is unclear whether the condition that the action occur “while transferring the data…” applies to the case of (1) and (2) (i.e., “while transferring” is a condition placed on the (1) reading and (2) generating steps), only (2) (i.e., “while transferring” is a condition placed on the (2) generating step), or only (3) (i.e., “while transferring” is a condition placed on the step of the calculation processing unit performing calculation), as all interpretations are plausible. Accordingly, the scope of the claim cannot be determined and the claim is indefinite.
Regarding claims 2, 6-8 and 12:
Claims 2, 6-8 and 12 recite, “the transfer of one [“a” in the case of claim 12] unit of data”. However, there is insufficient antecedent basis for this limitation in the claim. Accordingly, it is unclear whether “the transfer” in claims 2, 6-8 and 12 is supposed to refer back to the limitation in claim 1 [claim 11 in the case of claim 12] of the data transferring unit “transfers data which are conditions of calculation stored in the external memory to the local memory” or not because the limitation in claim 1 [claim 11 in the case of claim 12] does not refer to one unit of data. Accordingly, the scope of the claim cannot be determined and the claim is indefinite.
Regarding claims 3 and analogous claim 13:
Claim 3 recites, “the transfer commands” while previously reciting that “multiple transfer commands” are rearranged and linked into “multiple transfer commands”. Accordingly, it is unclear whether “the transfer commands” refers to one of the pre-rearranged and pre-linked transfer commands or the post-rearranged and post-linked transfer commands and the scope of the claim cannot be determined and the claim is indefinite.
Claim 3 also recites, “the transfer of the required amount of data”. There is insufficient antecedent basis for this limitation in the claim. For example, it is unclear whether “the required amount” refers to a previously specified amount (such as a size of a unit of data that can be calculated by the calculation processing unit) or some other amount of data. Additionally, it is unclear which previously recited transfer, if an, “the transfer…” is meant to refer to and the scope of the claim cannot be determined and the claim is indefinite.
Claim 13 is rejected for reciting limitations analogous to those indicated above for claim 3.
Claims 3 also recites, “the transfer of the data”, however, the antecedent basis for this limitation is unclear. For example, claim 1 previously recites that the data transferring unit “transfer data… stored in the external memory to the local memory”, while claim 3 recites, “multiple transfer commands, which transfer a size of data larger than one unit…”. Accordingly, it is unclear whether “the transfer of the data” recited in claim 3 is meant to refer to the transfer of data by the data transferring unit in claim 1, the transfer of data by the commands in claim 3, or whether the transfer of data by the commands in claim 3 is actually performed by the data transferring unit as recited in claim 1. Accordingly, the scope of the claim cannot be determined and the claim is indefinite.
Claim 13 recites, “the transfer of data by the external bus connecting unit”. There is insufficient antecedent basis for this limitation in the claim. For example, the claims only previously recite transferring data with the data transferring unit or with transfer commands from the command list processing unit. Accordingly, it is unclear whether the external bus connecting unit also performs these transfers or if the limitation in claim 13 is meant to refer to a different data transfer and the scope of the claim cannot be determined and the claim is indefinite.
Regarding claim 8:
Claim 8 recites, “the transfer size monitoring unit”. There is insufficient antecedent basis for this limitation in the claim. Accordingly, the scope of the claim cannot be determined and the claim is indefinite.
Regarding claim 9:
Claim 9 recites, “the transfer of two or more sets of data”. However, there is insufficient antecedent basis for this limitation in the claim. Accordingly, it is unclear whether “the transfer of two or more sets of data” refers to the transfer specified in claim 1, or a new unintroduced transfer of data. Therefore, the scope of the claim cannot be determined and the claim is indefinite.
Regarding claim 10 and analogous claim 15:
Claims 10 and 15 recite, “the data at the source and the data at the destination”. However, There is insufficient antecedent basis for this limitation in the claim. For example, although claims 9 and 14 specify a source and a destination, claims 9 and 14 do not specifically specify that there is data at the source or the destination, or that the transfer of data from the source to the destination actually occurs such that there is any data at the destination. Accordingly, the scope of the claims cannot be determined and the claims are indefinite. The Examiner suggests amending the claims to recite, “[[the]] data the source and [[the]] data at the destination”.
Regarding claims 11-15:
Claims 11-15 are additionally rejected because the claims are directed to a method (“An information processing method…”), but the body of the claims are a series of structures that describe the capabilities of a system. As written, these limitations describe structural features rather than active method steps that are actually performed (i.e., using the gerund form of verbs “-ing”).
The grammatical structure therefore blurs the distinction between a system/apparatus and a method of operating that system. It is unclear whether the claim is intended to cover (1) a structural apparatus configured to be capable of performing the recited operations, (2) a method in which a system and its structures actually perform the recited “transfer”, “store”, “read”, “execute”, etc., steps, or (3) a hybrid apparatus-method claim, which is not permitted because it is unclear when infringement occurs (i.e., when the apparatus is produced or only when the apparatus is actually operated) [MPEP 2173.05(p)].
Because the claim recites both structural components and process steps, the scope of the claim is uncertain and the scope of the claim cannot be determined and the claim is indefinite.
The Examiner suggests amending the action step verbs in the claim to instead recite verbs in the gerund form (“-ing”) and then specify which structures perform that action in the method, rather than defining structures and their capabilities. The following list is a non-exhaustive list of limitations in the claim that should be amended to recite gerund form verbs (“-ing”) (for example, be amended to recite “transferring data by a data transferring unit”, “storing data and a list of commands in the local memory”, “reading the list of commands, using the command list processing unit, from the local memory” “generating a command, using the command list processing unit, to execute calculation…”, “processing the data with the calculation processing unit”, etc.):
In claim 11: connects, transfers, stores, reads, generates, executes, processes.
In claim 12: generates.
In claim 13: rearranges, links, issues, generates.
In claim 14: specifies, performs, independently specifies.
Regarding claims 2-10 and 11-15:
Claims 2-10 and 11-15 are rejected for failing to cure the deficiencies of a rejected base claim from which they depend.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1-15:
Claims 1-15 is rejected for failing to disclose the corresponding structure (including a corresponding algorithm for computer-implemented functions) that performs the entire claimed function for the claim limitations interpreted under 35 USC §112(f) as seen in the claim interpretation section above for limitations (d-e, g-m, n-q, v-w, y-cc). As such, the claims lack adequate written description support because “an indefinite, unbounded functional limitation would cover all ways of performing a function and indicate that the inventor has not provided sufficient disclosure to show possession of the invention” [MPEP 2163.03(VI)]. Additionally, the claims are rejected as being indefinite for failing to disclose the corresponding structure for performing the claimed limitations, and accordingly, the claims lack adequate written description [MPEP 2181(II)(B), last ¶].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 9, 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2023/0132931 A1 (Greathouse) in view of US Patent Application Publication No. US 2019/0347030 A1 (Ueshima).
Regarding claim 1 and analogous claim 11:
Greathouse discloses, an information processing device comprising a data transferring unit (DMA engine (314) (414), which is a DMA controller [0024]), a local memory (DMA buffer (316) (416) and cache memory (310) (410), a command list processing unit (DMA engine (314) (414), which is a DMA controller [0024]) and an external bus connecting unit (the bus-based fabric (104), which includes buses with bridges) for connecting the data transferring unit (DMA engine (314) (414), which is a DMA controller [0024]), the local memory (DMA buffer (316) (416) and cache memory (310) (410), and the command list processing unit (DMA engine (314) (414), which is a DMA controller [0024]) to an external memory (memory module (312) (412), through memory controllers (108) or I/O interfaces (106) [Figs. 1-3] [0013], wherein the data transferring unit transfers data which are conditions of calculation stored in the external memory to the local memory (by disclosing the DMA engine (314) coordinates transfer of data between devices and memory within the system (300) [0024], and include processors to transfer the data between locations in memory and memory within the CPU [0026]. The DMA engine can read and write data, including from the memory modules (312) over the data fabric (306) [0029]. The DMA engine can in this way fetch data into memory of the processor (for example cache (310) (410) for use by the processor [0047]) wherein the local memory stores the data and a list of commands (by disclosing that the DMA buffers (316) may also be referred to as DMA queues and hold DMA transfer commands from the processors (308) [0027], and the cache memory (310) stores data that is loaded for the processors to perform computations on [0009] [0022] [0024] [0036] [0038]) wherein the command list processing unit reads the list of commands from the local memory and there is calculation by a calculation processing unit while transferring the data from the external memory to the local memory, wherein the calculation processing unit executes the calculation and processing the data (by disclosing that the process cores (308) (408) of the multi-chip module processor base die (302) (402) perform computation (calculation by a calculation processing unit, which performs calculation and processing of the data)) while the DMA engine performs DMA transfer of data from a source to a destination, including from the memory (312) (412) to the cache memory (310) (410) (while transferring data from the external memory to the local memory).
Greathouse does not explicitly disclose, but Ueshima teaches to use a command list processing unit to generate a command to execute calculation by a calculation processing unit while transferring data from the external memory to the local memory, wherein the calculation processing unit executes the calculation and processing the data (by teaching the command buffer (301) (i.e., local memory) located on the co-processor (300) that includes a command holding unit (310) that stores commands generated by the processor (100). The commands include commands for DMA processing and CLAC processing [Fig. 3]. In this way, the command buffer (301) controls both the DMA engine (Data Transfer Unit (370) and the arithmetic processing unit (380) (calculation processing unit) based on the state of the processor as controlled by the state machine (320) [Fig. 1] [Fig. 2] [Fig. 3] [0042-0046] [0048-0051] [0053-0059]. This allows the command buffer (301) to efficiently control data transfer and calculation based on which data are transferred for different command columns based on the state machine (310) [see Figs. 12-13 and 16-17] [0155-0159] [0167-0171], which includes performing data transfer commands at the same time as performing calculation commands on data stored in the exclusive (390) (local) memory [Fig. 1]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the DMA buffer storing DMA commands as taught by Greathouse to include being stored in a command buffer storing both DMA and CALC commands for execution by the coprocessor (base die of the MCM processor as taught by Greathouse), where the command buffer selects commands for performance by the data transfer unit (DMA engine as taught by Greathouse) and for performance by the arithmetic processing unit (core of the base die MCM processor as taught by Greathouse) as taught by Ueshima.
One of ordinary skill in the art would have been motivated to make this modification because the command die with the state machine performing selection between DMA commands and CALC commands allows for more efficient execution of data transfer and calculation processing as taught by Ueshima in [0008] [0017] [0018].
Regarding claim 4:
The information processing device according to claim 1 is made obvious by Greathouse in view of Ueshima.
Greathouse does not explicitly disclose, but Ueshima teaches wherein the command list processing unit generates a command to start the transfer of the data being processed from the local memory to the external memory during the calculation by the calculation processing unit (see [Fig. 16] where data is moved from the exclusive memory (390) (local memory) to the shared memory (200) (external memory) in the DMA_U processing 1-1 and 2-1 while CALC processing 1-2 and CALC processing 2-2 is occurring, where the data transfer and calculations are started by commands selected in the command buffer (310) and send to the data transfer unit (370) and the arithmetic processing unit (380) [Figs. 1-2] (generates a command to start the transfer of data being processed from the local memory to the external memory during the calculation by the calculation processing unit) [Fig. 16]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the DMA buffer storing DMA commands as taught by Greathouse to include being stored in a command buffer storing both DMA and CALC commands for execution by the coprocessor (base die of the MCM processor as taught by Greathouse), where the command buffer selects commands for performance by the data transfer unit (DMA engine as taught by Greathouse) and for performance by the arithmetic processing unit (core of the base die MCM processor as taught by Greathouse), such that data download and upload commands (transfer to/from local memory from/to external memory) can be performed during calculation operations as taught by Ueshima.
One of ordinary skill in the art would have been motivated to make this modification because the command die with the state machine performing selection between DMA commands and CALC commands allows for more efficient execution of data transfer and calculation processing as taught by Ueshima in [0008] [0017] [0018].
Regarding claim 9 and analogous claim 14:
The information processing device according to claim 1 is made obvious by Greathouse in view of Ueshima.
Greathouse further discloses, wherein the data transferring unit specifies a source and destination for the transfer of two or more sets of data, performs the transfer of each set of data in divided portions in sequence, and independently specifies the amount of data to be divided for each set (by disclosing that the DMA engine provides requisite control information to read data from a DMA source and writes data to a DMA destination [0001] [0009]. The control information may include a source address, a transfer size, and a destination address to which the data is to be read and written [0025]. In some cases, the data may not be residing in the area of memory (associated with a channel) controlled by a specific DMA engine, and so the single read command may be split into multiple commands (for the transfer of two or more sets of data), and handled by two or more DMA engines making multiple requests for the data. The transfers may therefore happen sequentially, with each transfer specifying an amount of data to transfer (an amount of data to be divided for each set) and then once the multiple transfers are complete the processor may be notified of completion [0042-0047] [Fig. 4])
Claims 2, 5-8, 10, 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Greathouse in view of Ueshima in further view of US Patent Application Publication No. US 2025/0252039 A1 (Yoo).
Regarding claim 2 and analogous claim 12:
The information processing device according to claim 1 is made obvious by Greathouse in view of Ueshima.
Greathouse does not explicitly disclose, but Yoo teaches wherein the data transferring unit includes a transfer size monitoring unit, and the command list processing unit generates a command to execute calculation by the calculation processing unit when the transfer size monitoring unit detects that the transfer of one unit of data, which can be calculated by the calculation processing unit, from the external memory to the local memory is completed (by teaching the HiveSync Monitor (1400) that includes a readiness table of addresses and sets a ready bit corresponding to an address when the corresponding address is written with data in the buffer memory (1500) [0029]. The consumer can then read the readiness table and when the ready bit is set to ‘1’, can read the corresponding memory area of the buffer memory [0030]. The HiveSync monitor, also transit an interrupt to the consumer when the ready bit is converted to logic ‘1’ [0030]. The consumer may be a CPU, GPU, NPU, VPU, ISP, DSP, etc. and may perform a specialized operation on the data [0031]. The hive sync monitor can subdivide all the areas of memory into fine units and can indicate the status of each subdivision with the ready bits [0032]. A job may therefore be synchronized and launched according to the readiness status of each area of memory rather than strictly sequentially [0092-0097]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the DMA engine as taught by Greathouse in view of Ueshima to include a readiness table with readiness bits indicating whether each subdivision of data is loaded in the memory and ready for use by the core/algorithmic processing units (consumers) so that job launching (i.e., by the command buffer with state machine as taught by Ueshima) and data synchronization can be based on the data being ready as taught by Yoo.
One of ordinary skill in the art would have been motivated to make this modification because it increases power efficiency and improves job launching and performance as taught by Yoo in [0097-0098].
Regarding claim 5:
The information processing device according to claim 1 is made obvious by Greathouse in view of Ueshima.
Greathouse further discloses, wherein the calculation processing unit is composed of multiple cores (by teaching that the base die multi-chip module (302) (402) has a plurality of cores (308) (408) that execute computations [see Figs. 3-4])
Greathouse does not explicitly disclose, but Yoo teaches and while one core is executing a part of the calculation for one process, another core executes another part of the calculation for the one process (by teaching that the different consumers (cores) can execute processes at the same time as soon as data becomes available from the previous consumer (core) in the processing of the data based on the readiness table indicating that the data is ready [see Fig. 14] [0098-0102]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the DMA engine as taught by Greathouse in view of Ueshima to include a readiness table with readiness bits indicating whether each subdivision of data is loaded in the memory and ready for use by the core/algorithmic processing units (consumers), including a plurality of processing units (i.e., cores as taught by Greathouse) (consumers) so that job launching (i.e., by the command buffer with state machine as taught by Ueshima) and data synchronization can be based on the data being ready and data can be processed by the different consumers in parallel as taught by Yoo.
One of ordinary skill in the art would have been motivated to make this modification because it increases power efficiency and improves job launching and performance as taught by Yoo in [0097-0098].
Regarding claim 6:
The information processing device according to claim 1 is made obvious by Greathouse in view of Ueshima.
Greathouse in view of Ueshima in further view of Yoo make obvious, wherein the calculation processing unit includes a second local memory, and the command list processing unit includes a second data transferring unit equipped with a second transfer size monitoring unit, which generates a command to execute calculation by the calculation processing unit when it detects that the transfer of one unit of data, which can be computed by the calculation processing unit, from the local memory to the second local memory is completed (through an analogous analysis applied to that performed to claim 2 (i.e., with the additional teachings of Ueshima and Yoo as applied to a processor multi-chip module base die in claim 2) applied to the disclosure in Greathouse of the plurality of processors (102) (the plurality interpreted as the calculation processing unit), which as shown in [Figs. 3-4], may each include the plurality of cores (308) (408), DMA engines (314) (414), buffers (316) (416) and caches (310) (410) when they are implemented as the processor multi-chip module base die including the plurality of chiplets (304) (404) [Figs. 3-4]).
Regarding claim 7:
The information processing device according to claim 1.
Greathouse does not explicitly disclose, but Yoo teaches, wherein the local memory includes a mechanism to determine the access range, and the command list processing unit generates a command to execute calculation by the calculation processing unit when the mechanism to determine the access range detects that the transfer of one unit of data, which can be computed by the calculation processing unit, from the external memory to the local memory is completed (by teaching the HiveSync Monitor (1400) that includes a readiness table of addresses and sets a ready bit corresponding to an address when the corresponding address is written with data in the buffer memory (1500) [0029]. The consumer can then read the readiness table and when the ready bit is set to ‘1’, can read the corresponding memory area of the buffer memory [0030]. The HiveSync monitor, also transit an interrupt to the consumer when the ready bit is converted to logic ‘1’ [0030]. The consumer may be a CPU, GPU, NPU, VPU, ISP, DSP, etc. and may perform a specialized operation on the data [0031]. The hive sync monitor can subdivide all the areas of memory into fine units and can indicate the status of each subdivision with the ready bits [0032]. A job may therefore be synchronized and launched according to the readiness status of each area of memory rather than strictly sequentially [0092-0097]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the local memory, such as the cache memory/exclusive memory as taught by Greathouse in view of Ueshima to include a readiness table with readiness bits indicating whether each subdivision of data is loaded in the memory and ready for use by the core/algorithmic processing units (consumers) so that job launching (i.e., by the command buffer with state machine as taught by Ueshima) and data synchronization can be based on the data being ready as taught by Yoo.
One of ordinary skill in the art would have been motivated to make this modification because it increases power efficiency and improves job launching and performance as taught by Yoo in [0097-0098].
Regarding claim 8:
The information processing device according to claim 1 is made obvious by Greathouse in view of Ueshima.
Greathouse in view of Ueshima in further view of Yoo make obvious comprising multiple data transferring units, wherein each of the multiple data transferring units includes the transfer size monitoring unit, wherein command list processing unit generates a command to execute calculation by the calculation processing unit when the transfer size monitoring unit detects that the transfer of a unit of data, which can be calculated by the calculation processing unit, from the external memory to the local memory is complete (through an analogous analysis applied to that performed to claim 2 (i.e., with the additional teachings of Ueshima and Yoo as applied to a processor multi-chip module base die in claim 2) applied to the disclosure in Greathouse of the plurality of processors (102) (the plurality interpreted as the calculation processing unit), which as shown in [Figs. 3-4], may each include the plurality of cores (308) (408), DMA engines (314) (414) (i.e., multiple data transferring units), buffers (316) (416) and caches (310) (410) when they are implemented as the processor multi-chip module base die including the plurality of chiplets (304) (404) [Figs. 3-4]).
Regarding claim 10 and analogous claim 15:
Greathouse teaches the manipulated data may be manipulated by GPU (graphics processing unit), but does not explicitly disclose, however Yoo teaches wherein the data at the source and the data at the destination are image data (by teaching that the data may be for image processing to perform image analysis, which may include processing by a GPU [0080-0083]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the manipulated data, which may be manipulated with computations by a GPU as taught by Greathouse to include image data as taught by Yoo.
One of ordinary skill in the art would have been motivated to make this modification because Greathouse teaches a system that can perform data transfer and computations on data in parallel, but does not teach what the data is, and Yoo teaches that performing transfer and calculations and transfer on image data in parallel and in a pipelined manner is an efficient and useful for tasks such as image classification [0002-0004] [0090] [0097] [0102] such that one of ordinary skill in the art would have been motivated to modify Greathouse to process image data as taught by Yoo..
Subject Matter Free From Prior Art
The subject matter of claims 3 and 13 was searched for in the prior art, but not found. Accordingly, a prior art rejection for claims 3 and 13 has not been made. However, claims 3 and 13 are subject to other 35 USC §112(a) and 35 USC §112(b) rejections and accordingly, are not indicated as allowable.
Reasons for indicating subject matter free from prior art:
The prior art does not teach “wherein the command list processing unit rearranges and links multiple transfer commands, which transfer a size of data larger than one unit that can be calculated by the calculation processing unit, into multiple transfer commands of the same attribute for consecutive addresses inside the local memory, requests the transfer of the data to the external bus connecting unit by issuing the transfer commands, and generates a command to execute calculation by the calculation processing unit when the transfer of the required amount of data to the local memory is completed” as recited in claim 3 and analogously in claim 13 because Ueshima does not teach the command buffer (310) rearranging and linking multiple commands that transfer a size of data larger than one unit that can be calculated by the calculation processing unit, into multiple transfer commands of the same attribute for consecutive addresses inside the local memory, requests the transfer of the data to the external bus connecting unit by issuing the transfer commands, and generates a command to execute calculation by the calculation processing unit when the transfer of the required amount of data to the local memory is completed” because it merely teaches commands in the same command column being issued together, but not linked or rearranged, and it does not teach that the commands are larger than what may be processed by the calculation processing unit. Furthermore, the prior art does not provide motivation why one ordinary skill in the art would modify the prior art to arrive at the claimed invention. Accordingly, the subject matter is not rejected with prior art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The paper titled, “FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling” by Masayuki Shimoda et. al., teaches an overlapping tiling algorithm, where tiles are extracted from an image with overlap to prevent accuracy degradation and improve utilization of BRAMs storing high resolution images to provide power efficiency and speedup of image processing with an FPGA by loading tiles of images rather than entire high resolution images into the BRAMs for processing in tile sized amounts by the FPGA [Abstract] [see Fig. 11] [§Overlapping Tiling Algorithm – pgs. 506].
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/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139
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