CTNF 19/076,203 CTNF 82519 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wang et al. (U.S. Patent 7,791,406, hereafter Wang) . Claim 1: Wang teaches a semiconductor integrated circuit (Figure 6) comprising: a switch (230) connected between a first power supply node (VDD) and a second power supply node (VDDV) that turns off when receiving a first level (logic high) at a control terminal (gate of 230 on 246); a first control circuit (202, 208) having an input node (216) and an output node (246) connected to a control terminal of the switch (230); and a second control circuit (210) having an output node (220) and an input node (218) connected to a control terminal of the switch (via 208), wherein the semiconductor integrated circuit satisfies at least one of a condition that drive strength to the first level (logic high) is greater than drive strength to a second level (logic low) in the first control circuit (column 10 lines 43-52, where logic low turns on the PMOS switch 230 when exiting SLEEP mode in an incremental manner) and another condition that drive strength to the second level (logic low) is greater than drive strength to the first level (logic high) in the second control circuit. Claim 3: Wang further teaches that the semiconductor integrated circuit satisfies a condition that drive strength to the first level (logic high) is greater than drive strength to the second level (logic low) in the first control circuit (column 10 lines 50-52) and does not satisfy another condition that drive strength to the second level is greater than drive strength to the first level in the second control circuit . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Jeon (U.S. Patent 9,496,863) . Claim 11: Wang teaches a semiconductor integrated circuit (Figure 6) comprising: a switch (230) connected between a first power supply node (VDD) and a second power supply node (VDDV) that turns off when receiving a first level (logic high) at a control terminal (gate of 230 connected to 246); a first control circuit (202, 208) having an input node (216) and an output node (246) connected to the control terminal of the switch (230); and a second control circuit (204) having an output node (220) and an input node (218) connected to the control terminal of the switch (via 208). Wang does not specifically teach first or second assist circuits. Jeon teaches a semiconductor integrated circuit (Figure 1) comprising at least one of: a first assist circuit (250 connected to the output of 208 of Wang) that assists, when a second level (logic low) logically inverted from a first level (logic high) is input to an input node of the first control circuit in a state where the switch remains turned off (logic high is at the gate of 230), appearance of the first level (logic high) in an output node of the first control circuit (the output of the power gating circuit will be logic high before changing to logic low due to the inherent delay in the inverters); and a second assist circuit (250 connected to the output of 210 in Wang) that assists, when the first level is input to an input node of the second control circuit in a state where the switch remains turned off, appearance of the second level in an output node of the second control circuit (the output of the power gating circuit will be logic low before changing to logic high due to the inherent delay in the inverters). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the buffer taught by Jeon in the circuit of Wang to reduce the size of the power gating circuit (column 7 lines 28-42). Claim 12: The combined circuit further teaches that the semiconductor integrated circuit includes both the first assist circuit and the second assist circuit (250 of Jeon). Claim 13: The combined circuit further teaches that the semiconductor integrated circuit includes the first assist circuit and does not include the second assist circuit (250 of Jeon coupled to the output of 208 of Wang). Claim 14: The combined circuit further teaches that the semiconductor integrated circuit does not include the first assist circuit and includes the second assist circuit (250 of Jeon coupled to the output of 210 of Wang) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2, 4-10 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2, the prior art does not fairly teach or suggest the semiconductor integrated circuit satisfies both a condition that drive strength to the first level is greater than drive strength to the second level in the first control circuit and another condition that drive strength to the second level is greater than drive strength to the first level in the second control circuit. Regarding claim 4, the prior art does not fairly teach or suggest the semiconductor integrated circuit does not satisfy a condition that drive strength to the first level is greater than drive strength to the second level in the first control circuit and satisfies another condition that drive strength to the second level is greater than drive strength to the first level in the second control circuit. Regarding claim 5, the prior art does not fairly teach or suggest threshold voltage of the first P-type transistor is lower than threshold voltage of the first N-type transistor in combination with the limitations of claim 5. Claim 9 is objected to merely for being dependent on claim 5. Regarding claim 6, the prior art does not fairly teach or suggest wherein the semiconductor integrated circuit satisfies a condition that drive strength to the second level is greater than drive strength to the first level in the second control circuit, and the second control circuit includes a second P-type transistor and a second N-type transistor inverter-connected, wherein threshold voltage of the second N-type transistor is lower than threshold voltage of the second P-type transistor. Claim 10 is objected to merely for being dependent on claim 6. Regarding claim 7, the prior art does not fairly teach or suggest the semiconductor integrated circuit satisfies a condition that drive strength to the first level is greater than drive strength to the second level in the first control circuit, and the first control circuit includes a plurality of first P-type transistors and a plurality of first N-type transistors inverter-connected, wherein the plurality of first P-type transistors is connected in parallel and the plurality of first N-type transistor is connected in series. Regarding claim 8, the prior art does not fairly teach or suggest the semiconductor integrated circuit satisfies a condition that drive strength to the second level is greater than drive strength to the first level in the second control circuit, and the second control circuit includes a plurality of second P-type transistors and a plurality of second N-type transistors inverter-connected, wherein the plurality of second N-type transistors is connected in parallel and the plurality of second P-type transistor is connected in series. Regarding claim 15, the prior art does not fairly teach or suggest the semiconductor integrated circuit includes the first assist circuit, and the first assist circuit includes at least one of a third P-type transistor or a third N-type transistor in which a drain is commonly connected to a control terminal of the switch and a source is commonly connected to power supply potential. Regarding claim 16, the prior art does not fairly teach or suggest the semiconductor integrated circuit includes the second assist circuit, and the second assist circuit includes at least one of a fourth P-type transistor or a fourth N-type transistor in which a drain is commonly connected to a control terminal of the switch and a source is commonly connected to ground potential. Regarding claim 17, the prior art does not fairly teach or suggest the semiconductor integrated circuit includes the first assist circuit, and the first assist circuit includes a first capacitive element having one end connected to a control terminal of the switch and an other end connected to the first power supply node. Claim 19 is objected to merely for being dependent on claim 17. Regarding claim 18, the prior art does not fairly teach or suggest the semiconductor integrated circuit includes the second assist circuit, and the second assist circuit includes a second capacitive element having one end connected to an output node of the second control circuit and an other end connected to a ground potential. Claim 20 is objected to merely for being dependent on claim 18 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : U.S. Patent 7,570,100 Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN J O'TOOLE whose telephone number is (571)270-1273. The examiner can normally be reached Monday - Friday, 9:00 am - 6:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.J.O/Examiner, Art Unit 2836 /RYAN JOHNSON/Primary Examiner, Art Unit 2836 Application/Control Number: 19/076,203 Page 2 Art Unit: 2836 Application/Control Number: 19/076,203 Page 3 Art Unit: 2836 Application/Control Number: 19/076,203 Page 4 Art Unit: 2836 Application/Control Number: 19/076,203 Page 5 Art Unit: 2836 Application/Control Number: 19/076,203 Page 6 Art Unit: 2836 Application/Control Number: 19/076,203 Page 7 Art Unit: 2836 Application/Control Number: 19/076,203 Page 8 Art Unit: 2836 Application/Control Number: 19/076,203 Page 9 Art Unit: 2836
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