Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Application
This Office Action is in response to Applicant’s Application filed on 3/11/2025.
Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 3/11/2025; 6/05/2025; and 4/07/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 9, 11-12, 15, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Fouda (US 2024/0427844), herein referred to as Fouda ‘844, in view of Wang et al. (US 2023/0078569), herein referred to as Wang ‘569.
Referring to claim 1, Fouda ‘844 teaches a memory device (see Fig. 1, compute engine 100 with compute-in-memory (CIM) hardware modules 120), comprising:
a processing-in-memory (PIM) block (see Fig. 1, CIM hardware modules 120 having multiple vector multiplication units (VMUs) 130) configured to perform an operation (see Paragraph 0045, where CIM hardware modules 120 performing multiplication between an element of the activation from the input buffer 110 with weights in storage 140) between a weight value (see Paragraph 0045, where one of the operands for the multiplication is a weight value), which is represented by a weight scale factor and a weight element (see Paragraph 0045, where weight value is in storage 140 and for longer weight lengths, a portion of the weight can be multiplied by an element provide by an input buffer 110 and the products sent to a combiner; see Fig. 2, where VMU 230-0 has weight storage 240-00 with the most significant bits (MSB), and VMU 230-1 has weight storage 240-00L with the least significant bits (LSB), see Paragraphs 0051-0052, i.e. weight value being what is stored in element 140 and MSB and LSB being the scale factor), and an input value (see Paragraph 0045, where one of the operands for the multiplication is an element of the activation from the input buffer 110), which is represented by an input scale factor and an input element (see Paragraph 0050, where input buffer 210 stores activation that has n elements with unit 212 storing the magnitude of the activation and sign units 214 providing the sign of the activation used, see Fig. 2, i.e. magnitude being the element, and sign being a scale factor),
wherein the PIM block (see Fig. 1, CIM hardware modules 120 having multiple vector multiplication units (VMUs) 130) comprises:
a first scale register file (see Fig. 3, input buffer 310, which can also be termed an input register, see Paragraph 0065, where input buffer can comprise of units 212 and sign units 214, see Fig. 2) storing the input scale factor (see Fig. 2; input buffer 210 stores activation that has n elements with sign units 214 providing the sign of the activation used);
a second scale register file (see Fig. 2, where VMUs 230 have a cell / register for storing the weight values, see Paragraph 0070, i.e. a storage for the weight value of MSB to LSB in which a person of ordinary skill in the art would recognize that a memory cell / storage cell can be a register) storing the weight scale factor (see Fig. 2, where VMU 230-0 has weight storage 240-00 with the MSB and VMU 230-1 has weight storage 240-00L with the LSB);
a scalar register file (SRF) (see Fig. 3, input buffer 310, which can also be termed an input register, see Paragraph 0065; see Paragraph 0034, wherein input signal provided by input buffer 110 represents a scalar or a matrix, i.e. the input buffer can be a scalar type memory / register) storing the input element (see Paragraph 0045, where CIM hardware modules 120 performing multiplication between an element of the activation from the input buffer 110 with weights in storage 140);
a plurality of logic units (see Fig. 2, wherein each VMU 230 comprises multipliers 234 and adders 236) configured to, in response to an operation command received from a host (see Paragraph 0095, where GP processor 1110 provides the command to compute engines 1120 and controls data movement to and from compute engines, i.e. providing a command to start an operation using data provided), perform, in parallel (see Paragraph 0098, wherein the compute engines 1120 perform tasks in parallel such as vector-matrix multiplications in parallel; also see Fig. 1, compute engine 100 has multiple inputs from input buffer 110 sent to multiple CIMs 120 to be executed in parallel), a first operation between the input scale factor and the weight scale factor (see Fig. 2, wherein a first operation happens with input S0 and A0 through the multiple VMUs 230) and a second operation between the input element and the weight element (see Fig. 2, wherein a second operation happens with input S1 and A1 through multiple VMUs 230); and
an accumulator (see Fig. 2, accumulator 233 in each VMU 230) configured to accumulate and store an operation result from the first operation and the second operation (see Fig. 2, wherein accumulator 233 adds all resultants from adder tree 232 and sends the results to an output buffer 102, see Fig. 1, for storage).
However, Fouda ‘844 does not specifically teach the plurality of logics units being a plurality of arithmetic logic units. More specifically, multipliers and adders by themselves are not considered ALUs in the art, as an ALU by definition contains hardware circuitry to perform addition, subtraction, multiplication, division, and logical operations like AND, OR, and NOT, so just multipliers and adders would not be considered as a plurality of ALUs
Wang ‘569 teaches a neural network system (see Abstract) implementing a compute-in-memory (CIM) accelerator (See Fig. 1, CIM accelerator 135), that takes input data vectors, applying weights to the data through a multiply and accumulate (MAC) operation, and computing weighted sums, where the processing can be done using arithmetic logic units or additional circuitry (see Paragraph 0007 and Paragraph 0039).
Fouda ‘844 and Wang ‘569 apply as analogous prior art as both pertain to the same field of endeavor of performing multiply-add / multiply-accumulate operations using a compute-in-memory engine / accelerator.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fouda ‘844 system as set forth above to have ALUs or additional circuitry used to perform the multiply-accumulate operations instead of just generic logic units of multipliers and adders, as taught by Wang ‘569, as a person or ordinary skill in the art would recognize that multipliers and adders are just part of ALUs, where ALUs are known in the art to be a foundational digital circuit used in processors to execute all mathematic and comparative operations, thus a person of ordinary skill in the art would be motivated to utilize a plurality of ALUs with the plurality of VMUs in Fouda ‘844 to utilize already well known and used hardware circuits to perform mathematical operations necessary for the multiple-accumulate operations of the CIM.
As to claim 2, Fouda ‘844 teaches the memory device of claim 1, further comprising a control circuit (see Fig. 3, control unit 304) configured to, for the performing of the first operation and the second operation in parallel, in response to the operation command, provide, in parallel, a first operation signal instructing a first ALU among the plurality of ALUs according to the first operation and provide a second operation signal instructing a second ALU among the plurality of ALUs according to the second operation (see Paragraph 0098, wherein the compute engines 1120 perform tasks in parallel such as vector-matrix multiplications in parallel; also see Fig. 1, compute engine 100 has multiple inputs from input buffer 110 sent to multiple CIMs 120 to be executed in parallel).
As to claim 5, Fouda ‘844 teaches the memory device of claim 1, further comprising: an accumulation register file (ARF), wherein the accumulator comprises: a data type converter configured to generate the operation result by merging a first partial result of the first operation and a second partial result of the second operation into a specific data format; and an adder configured to add the generated operation result to a pre-stored value in the ARF (see Fig. 2, wherein each VMU has an accumulator 233, which the output is sent to a combiner 150 and conversion unit 152, see Fig. 1, where the partial outputs of multiple VMUs are combined and converted into a desired format, see Paragraph 0046, before being sent to output buffer 102, where the output may be stored into a vector register file of the GP processor 1110, see Paragraph 0102; Examiner points out that an accumulator by design is hardware that adds results to a pre-stored value).
As to claim 9, Fouda ‘844 teaches the memory device of claim 1, further comprising a memory bank storing the weight scale factor and the weight element, wherein the input scale factor and the input element are received from the host, in response to a command preceding the operation command, and the weight scale factor is loaded from the memory bank, in response to a command preceding the operation command (see Paragraph 0103, where input activations and other data can be loaded into compute engines / tiles and stored in DRAM; see Paragraph 0108, where data is loaded from the GP processor into the compute engines; see Paragraph 0110, where weights are loaded into one or more compute engines, the weight data moved from memory to the CIM hardware modules; Examiner points out that data needs to be loaded / available in order to perform any operation that required the data, so loading the data would be done preceding the execution of an operation command).
Referring to claim 11, Fouda ‘844 teaches an operating method of a memory device (see Fig. 1, compute engine 100 with compute-in-memory (CIM) hardware modules 120), comprising:
receiving an operation command from a host (see Paragraph 0095, where GP processor 1110 provides the command to compute engines 1120 and controls data movement to and from compute engines, i.e. providing a command to start an operation using data provided);
in response to the received operation command, performing, by a plurality of logic units (see Fig. 2, wherein each VMU 230 comprises multipliers 234 and adders 236), a first operation (see Fig. 2, wherein a first operation happens with input S0 and A0 through the multiple VMUs 230) between an input scale factor of an input value (see Paragraph 0050, where input buffer 210 stores activation that has n elements with unit 212 storing the magnitude of the activation and sign units 214 providing the sign of the activation used, see Fig. 2, i.e. magnitude being the element, and sign being a scale factor) and a weight scale factor of a weight value (see Paragraph 0045, where weight value is in storage 140 and for longer weight lengths, a portion of the weight can be multiplied by an element provide by an input buffer 110 and the products sent to a combiner; see Fig. 2, where VMU 230-0 has weight storage 240-00 with the most significant bits (MSB), and VMU 230-1 has weight storage 240-00L with the least significant bits (LSB), see Paragraphs 0051-0052, i.e. weight value being what is stored in element 140 and MSB and LSB being the scale factor) and a second operation (see Fig. 2, wherein a second operation happens with input S1 and A1 through multiple VMUs 230) between an input element of the input value (see Paragraph 0050, where input buffer 210 stores activation that has n elements with unit 212 storing the magnitude of the activation and sign units 214 providing the sign of the activation used, see Fig. 2, i.e. magnitude being the element, and sign being a scale factor) and a weight element of the weight value (see Paragraph 0045, where weight value is in storage 140 and for longer weight lengths, a portion of the weight can be multiplied by an element provide by an input buffer 110 and the products sent to a combiner; see Fig. 2, where VMU 230-0 has weight storage 240-00 with the most significant bits (MSB), and VMU 230-1 has weight storage 240-00L with the least significant bits (LSB), see Paragraphs 0051-0052, i.e. weight value being what is stored in element 140 and MSB and LSB being the scale factor), in parallel (see Paragraph 0098, wherein the compute engines 1120 perform tasks in parallel such as vector-matrix multiplications in parallel; also see Fig. 1, compute engine 100 has multiple inputs from input buffer 110 sent to multiple CIMs 120 to be executed in parallel); and
accumulating an operation result from the first operation and the second operation and storing the accumulated operation result (see Fig. 2, wherein accumulator 233 adds all resultants from adder tree 232 and sends the results to an output buffer 102, see Fig. 1, for storage).
However, Fouda ‘844 does not specifically teach the plurality of logics units being a plurality of arithmetic logic units. More specifically, multipliers and adders by themselves are not considered ALUs in the art, as an ALU by definition contains hardware circuitry to perform addition, subtraction, multiplication, division, and logical operations like AND, OR, and NOT, so just multipliers and adders would not be considered as a plurality of ALUs
Wang ‘569 teaches a neural network system (see Abstract) implementing a compute-in-memory (CIM) accelerator (See Fig. 1, CIM accelerator 135), that takes input data vectors, applying weights to the data through a multiply and accumulate (MAC) operation, and computing weighted sums, where the processing can be done using arithmetic logic units or additional circuitry (see Paragraph 0007 and Paragraph 0039).
Fouda ‘844 and Wang ‘569 apply as analogous prior art as both pertain to the same field of endeavor of performing multiply-add / multiply-accumulate operations using a compute-in-memory engine / accelerator.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fouda ‘844 system as set forth above to have ALUs or additional circuitry used to perform the multiply-accumulate operations instead of just generic logic units of multipliers and adders, as taught by Wang ‘569, as a person or ordinary skill in the art would recognize that multipliers and adders are just part of ALUs, where ALUs are known in the art to be a foundational digital circuit used in processors to execute all mathematic and comparative operations, thus a person of ordinary skill in the art would be motivated to utilize a plurality of ALUs with the plurality of VMUs in Fouda ‘844 to utilize already well known and used hardware circuits to perform mathematical operations necessary for the multiple-accumulate operations of the CIM.
As to claim 12, Fouda ‘844 teaches the operating method of claim 11, wherein the performing of the first operation and the second operation in parallel by the plurality of ALUs comprises: in response to the operation command, providing a first ALU among the plurality of ALUs with a first operation signal indicating the first operation; and providing a second ALU among the plurality of ALUs with a second operation signal indicating the second operation, wherein the providing of the first operation signal and the providing of the second operation signal are performed in parallel by a control circuit (see Fig. 3, control circuit 304; see Paragraph 0098, wherein the compute engines 1120 perform tasks in parallel such as vector-matrix multiplications in parallel; also see Fig. 1, compute engine 100 has multiple inputs from input buffer 110 sent to multiple CIMs 120 to be executed in parallel).
As to claim 15, Fouda ‘844 teaches the operating method of claim 11, wherein the storing of the accumulated computation result comprises: generating the operation result by merging a first partial result of the first operation and a second partial result of the second operation into a specific data format; and adding the generated operation result to a pre-stored value in an accumulation register file (ARF) (see Fig. 2, wherein each VMU has an accumulator 233, which the output is sent to a combiner 150 and conversion unit 152, see Fig. 1, where the partial outputs of multiple VMUs are combined and converted into a desired format, see Paragraph 0046, before being sent to output buffer 102, where the output may be stored into a vector register file of the GP processor 1110, see Paragraph 0102; Examiner points out that an accumulator by design is hardware that adds results to a pre-stored value).
As to claim 19, Fouda ‘844 teaches the operating method of claim 11, wherein the receiving of the operation command comprises: in response to a command preceding the operation command, receiving the input scale factor from the host and storing the received input scale factor in a first scale register file; and in response to a command preceding the operation command, receiving the input element from the host and storing the received input element in a scalar register file (SRF); and in response to a command preceding the operation command, loading the weight scale factor from a memory bank and storing the loaded weight scale factor in a second scale register file (see Paragraph 0103, where input activations and other data can be loaded into compute engines / tiles and stored in DRAM; see Paragraph 0108, where data is loaded from the GP processor into the compute engines; see Paragraph 0110, where weights are loaded into one or more compute engines, the weight data moved from memory to the CIM hardware modules; Examiner points out that data needs to be loaded / available in order to perform any operation that required the data, so loading the data would be done preceding the execution of an operation command).
Referring to claim 20, Fouda ‘844 teaches a processing-in-memory (PIM) device (see Fig. 1, compute engine 100 with compute-in-memory (CIM) hardware modules 120), comprising:
a plurality of logic units (see Fig. 2, wherein each VMU 230 comprises multipliers 234 and adders 236) configured to, for each of a plurality of input elements (see Paragraph 0045, where one of the operands for the multiplication is an element of the activation from the input buffer 110) sharing a same input scale factor (see Fig. 2, wherein an operation happens with input S0 and A0 through the multiple VMUs 230, i.e. sharing the same input scale factor) and each of a plurality of weight elements (see Paragraph 0045, where one of the operands for the multiplication is a weight value) sharing a same weight scale factor (see Fig. 2, weight storage 240 which where the MSB is shared in the first VMU and the LSB is shared in the second VMU of the same weight element; see Paragraph 0045, where weight value is in storage 140 and for longer weight lengths, a portion of the weight can be multiplied by an element provide by an input buffer 110 and the products sent to a combiner), perform:
a first operation (see Fig. 2, wherein a first operation happens with input S0 and A0 through the multiple VMUs 230) between the same input scale factor received from a first scale register file (see Fig. 3, input buffer 310, which can also be termed an input register, see Paragraph 0065, where input buffer can comprise of units 212 and sign units 214, see Fig. 2) and the same weight scale factor received from a second scale register file (see Fig. 2, where VMUs 230 have a cell / register for storing the weight values, see Paragraph 0070, i.e. a storage for the weight value of MSB to LSB in which a person of ordinary skill in the art would recognize that a memory cell / storage cell can be a register); and
a second operation (see Fig. 2, wherein a second operation happens with input S1 and A1 through multiple VMUs 230) between the respective input element received from a scalar register file (SRF) (see Fig. 3, input buffer 310, which can also be termed an input register, see Paragraph 0065, where input buffer can comprise of units 212 and sign units 214, see Fig. 2) and the respective weight element (see Fig. 2, where VMUs 230 have a cell / register for storing the weight values, see Paragraph 0070, i.e. a storage for the weight value of MSB to LSB in which a person of ordinary skill in the art would recognize that a memory cell / storage cell can be a register).
However, Fouda ‘844 does not specifically teach the plurality of logics units being a plurality of arithmetic logic units. More specifically, multipliers and adders by themselves are not considered ALUs in the art, as an ALU by definition contains hardware circuitry to perform addition, subtraction, multiplication, division, and logical operations like AND, OR, and NOT, so just multipliers and adders would not be considered as a plurality of ALUs
Wang ‘569 teaches a neural network system (see Abstract) implementing a compute-in-memory (CIM) accelerator (See Fig. 1, CIM accelerator 135), that takes input data vectors, applying weights to the data through a multiply and accumulate (MAC) operation, and computing weighted sums, where the processing can be done using arithmetic logic units or additional circuitry (see Paragraph 0007 and Paragraph 0039).
Fouda ‘844 and Wang ‘569 apply as analogous prior art as both pertain to the same field of endeavor of performing multiply-add / multiply-accumulate operations using a compute-in-memory engine / accelerator.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fouda ‘844 system as set forth above to have ALUs or additional circuitry used to perform the multiply-accumulate operations instead of just generic logic units of multipliers and adders, as taught by Wang ‘569, as a person or ordinary skill in the art would recognize that multipliers and adders are just part of ALUs, where ALUs are known in the art to be a foundational digital circuit used in processors to execute all mathematic and comparative operations, thus a person of ordinary skill in the art would be motivated to utilize a plurality of ALUs with the plurality of VMUs in Fouda ‘844 to utilize already well known and used hardware circuits to perform mathematical operations necessary for the multiple-accumulate operations of the CIM.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Fouda ‘844, in view of Wang ‘569, and further in view of Kumar et al. (US 2019/0042160), herein referred to as Kumar ‘160.
As to claim 8, Fouda ‘844 and Wang ‘569 do not specifically teach the memory device of claim 1, configured to, in response to receiving, from the host, a plurality of operation commands comprising the operation command, perform a dot product operation between an input vector comprising a plurality of input values and a weight matrix comprising a plurality of weight values.
Kumar ‘160 teaches a CIM system (see Abstract), where a processor can produce outputs for functions that include matrix multiplication, absolute difference computations, dot product multiplication, or other ML operation (see Paragraph 0041), where the dot product of neuron activation and weight matrices are done (see Paragraph 0033).
Fouda ‘844, Wang ‘569, and Kumar ‘160 apply as analogous prior art as all of these arts pertain to the same field of endeavor of performing multiply-add / multiply-accumulate operations using a compute-in-memory engine / accelerator.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Fouda ‘844 and Wang ‘569 system as set forth above to have operations such as a dot product between the input/activation and weight matrices done, as taught by Kumar ‘160, as a person or ordinary skill in the art would be motivated to perform dot products for various deep learning applications performing multiply-accumulate operations within the memory to enable higher throughput dot products of neuron activation and weight matrices while still providing higher performance and lower energy compared to computation by a host processor as claimed (see Paragraph 0033 of Kumar ‘160).
As to claim 18, Fouda ‘844 and Wang ‘569 do not specifically teach the operating method of claim 11, further comprising, in response to receiving, from the host, a plurality of operation commands comprising the operation command, performing a dot product operation between an input vector comprising a plurality of input values and a weight matrix comprising a plurality of weight values.
Kumar ‘160 teaches a CIM system (see Abstract), where a processor can produce outputs for functions that include matrix multiplication, absolute difference computations, dot product multiplication, or other ML operation (see Paragraph 0041), where the dot product of neuron activation and weight matrices are done (see Paragraph 0033).
Fouda ‘844, Wang ‘569, and Kumar ‘160 apply as analogous prior art as all of these arts pertain to the same field of endeavor of performing multiply-add / multiply-accumulate operations using a compute-in-memory engine / accelerator.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Fouda ‘844 and Wang ‘569 system as set forth above to have operations such as a dot product between the input/activation and weight matrices done, as taught by Kumar ‘160, as a person or ordinary skill in the art would be motivated to perform dot products for various deep learning applications performing multiply-accumulate operations within the memory to enable higher throughput dot products of neuron activation and weight matrices while still providing higher performance and lower energy compared to computation by a host processor as claimed (see Paragraph 0033 of Kumar ‘160).
Allowable Subject Matter
Claims 3-4, 6-7, 10, 13-14 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 3 and 13, Examiner finds that prior art does not specifically teach: for the accumulating and storing of the operation result, the control circuit is configured to provide the accumulator with a third operation signal indicating a conversion into the operation result represented in a specific data format from a first partial result of the first operation and a second partial result of the second operation, at a timing after a first specific cycle has elapsed from the first operation signal and the second operation signal. More specifically the conversion representing the specific data format from partial results at a timing after a first specific cycle elapsed from first and second operation signals as claimed.
As to claims 6 and 16, Examiner finds that prior art does not specifically teach the input scale factor comprises an exponent component of the input value, the input element comprises a mantissa component of the input value, the weight scale factor comprises an exponent component of the weight value, and the weight element comprises a mantissa component of the weight value in the context of a PIM / CIM system of the independent claims. More specifically Examiner finds prior arts of neural network / deep learning systems implementing multiply-accumulate operations using floating point numbers where operands can include an exponent field and mantissa field.
As to claim 10, Examiner finds that prior art does not specifically teach the memory device of claim 1, configured to receive, from the host, and process a first plurality of operation commands for data sharing a first scale factor and a second plurality of operation commands for data sharing a second scale factor, without a fence.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yoon et al. (US 11,921,626) teaches a PIM system and memory with registers to store information received from a processor for operations in the PIM.
Lie et al. (US 2020/0380344) teaches a deep learning system with performing multiply-accumulate operations using floating point operands, where operands include an exponent field and a mantissa field for performing the multiply-accumulate operations.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST.
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/MICHAEL SUN/Primary Examiner, Art Unit 2183
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