Prosecution Insights
Last updated: April 19, 2026
Application No. 19/076,402

ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD

Non-Final OA §103§DP
Filed
Mar 11, 2025
Examiner
AYNALEM, NATHNAEL B
Art Unit
2488
Tech Center
2400 — Computer Networks
Assignee
Panasonic Intellectual Property Corporation of America
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
90%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
505 granted / 662 resolved
+18.3% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
32 currently pending
Career history
694
Total Applications
across all art units

Statute-Specific Performance

§101
5.6%
-34.4% vs TC avg
§103
39.5%
-0.5% vs TC avg
§102
22.3%
-17.7% vs TC avg
§112
21.6%
-18.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 662 resolved cases

Office Action

§103 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status This is in response to application no. 19/076,402 filed on 03/11/2025. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 of U.S. Patent No. US 12284376 B2 in view of DESHPANDE et al. (US 20160191926 A1). Regarding claim 1, claim 1 of the cited pat. No. ‘376 teaches all of the limitations of claim 1 except the limitation “wherein the one or more HRD parameters indicate information related to a coded picture buffer (CPB) removal delay of the decoding unit.” However, DESHPANDE teaches wherein the one or more HRD parameters indicate information related to a coded picture buffer (CPB) removal delay of the decoding unit (¶0131-0132: The method also includes determining, when the picture timing SEI message does not comprise the common decoding unit CPB removal delay flag, a separate decoding unit CPB removal delay parameter for each decoding unit in the access unit). Note that the CPB removal delay parameter correspond to HRD parameter, see DESHPANDE ¶0104, 0116-0017. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified encoder in claim 1 of ‘376 to include “wherein the one or more HRD parameters indicate information related to a coded picture buffer (CPB) removal delay of the decoding unit,” as taught by DESHPANDE, in order to specify an amount of sub-picture clock ticks to wait after removal from the CPB of the last decoding unit before removing from the CPB (DESHPANDE ¶0102). Claims 2-4 recite the limitation analogous to claim 1, and are rejected due to the same reason set forth above with respect to claim 1. Table 1 below shows the comparison between the current claims and the claims of pat. No. ‘376. TABLE 1 Current claims Pat. No. US 12284376 B2 claims 1. An encoder comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the circuitry: encodes, for each of decoding units per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters into an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD; and generates a bitstream including the HRD-related SEI message, 1. An encoder comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the circuitry: encodes, for each of decoding units per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters into an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD. 2. A decoder comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the circuitry: decodes, for each of decoding units per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters from an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD, 2. A decoder comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the circuitry: decodes, for each of decoding units per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters from an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD. 3. An encoding method comprising: encoding, for each of decoding units per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters into an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD; and generating a bitstream including the HRD-related SEI message, 3. An encoding method comprising: encoding, for each of decoding units per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters into an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD. 4. A decoding method comprising: decoding, for each of decoding units per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters from an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD, 4. A decoding method comprising: decoding, for each of decoding units per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters from an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over DESHPANDE et al. (US 20160191926 A1) in view of SEO (US 20170201751 A1). Regarding claim 1, DESHPANDE teaches the claim limitation as follows: An encoder comprising: circuitry; and memory coupled to the circuitry (FIGS. 1A: 0229-0230: Electronic device A 102a includes an encoder 104...input picture(s) 106…may be retrieved from memory and/or may be received from another electronic device. See FIGS 6A-6B: an encoder 604 ¶0284-0285: the source 622 may include image sensors, memory…), wherein in operation, the circuitry: encodes, for each of decoding units (¶0108, 0131-0132: The electronic device also determines…a separate decoding unit CPB removal delay parameter for each decoding unit in the access unit), one or more hypothetical reference decoder (HRD) parameters into an HRD-related supplemental enhancement information (SEI) message the one or more HRD parameters being one or more parameters for an HRD (¶0102-0104, 0251: The electronic device may also generate… a picture timing SEI message including a CPB removal delay parameter…¶0133, 0138-0139: In some configurations, the systems and methods disclosed herein may describe signaling sub-picture based Hypothetical Reference Decoder (HRD) parameters. For instance, the systems and methods disclosed herein describe modification to a picture timing Supplemental Enhancement Information (SEI) message). Note that the CPB removal delay parameter correspond to HRD parameter, see also DESHPANDE ¶0116-0117, 0225, the one or more parameters being related to a decoding unit (¶0102-0104, 0131-0132: decoding unit CPB removal delay parameter), the HRD-related SEI message being an SEI message related to the HRD (¶0102-0104, 0133, 0138-0139: The electronic device may also generate… a picture timing SEI message including a CPB removal delay parameter…). Note that the CPB removal delay parameter correspond to HRD parameter, see also DESHPANDE ¶0116-0117, 0225; and generates a bitstream including the HRD-related SEI message (¶0102-0104: The electronic device may also generate… a picture timing SEI message including a CPB removal delay parameter…¶0133, 0138-0139: The systems and methods disclosed herein describe electronic devices for sending a message and buffering a bitstream…In some configurations, the systems and methods disclosed herein may describe signaling sub-picture based Hypothetical Reference Decoder (HRD) parameters. For instance, the systems and methods disclosed herein describe modification to a picture timing Supplemental Enhancement Information (SEI) message), wherein the one or more HRD parameters indicate information related to a coded picture buffer (CPB) removal delay of the decoding unit (¶0102-0104, 0131-0132: i.e., decoding unit CPB removal delay parameter). DESHPANDE does not explicitly disclose encod[ing]…per temporal sub-layer. SEO teaches encod[ing]…per temporal sub-layer (¶0084: The bitstream processor 410 may receive a bitstream encoded by the video encoder 300. ¶0162: the minimum buffer size that a decoder allocates for decoding a particular bitstream may be signaled by a parameter, which may be set for each temporal sub-layer in the sequence parameter set). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify DESHPANDE’s image encoder by incorporating the teaching of SEO as noted above, in order to reduce the picture buffer size as taught by SEO (¶0169). Regarding claim 2, DESHPANDE teaches the claim limitation as follows: A decoder comprising: circuitry; and memory coupled to the circuitry (FIGS. 1A, 7A-7B: ¶0241, 0300-0302: a decoder 712 comprising Coded Picture Buffer (CPB) 120, 720) , wherein in operation, the circuitry: decodes, for each of decoding units one or more hypothetical reference decoder (HRD) parameters from an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD (¶0132, 0239-0240: The decoder 112 may receive a message (e.g., picture timing SEI message or other message)…the decoder 112 may determine a separate decoding unit CPB removal delay parameter for each decoding unit in the access unit…¶0133, 0138-0139: In some configurations, the systems and methods disclosed herein may describe signaling sub-picture based Hypothetical Reference Decoder (HRD) parameters. For instance, the systems and methods disclosed herein describe modification to a picture timing Supplemental Enhancement Information (SEI) message). Note that the CPB removal delay parameter correspond to HRD parameter, see also DESHPANDE ¶0116-0017, 0225, the one or more parameters being related to a decoding unit (¶0131-0132, 0239: decoding unit CPB removal delay parameter), the HRD-related SEI message being an SEI message related to the HRD (¶0132, 0239-0240: The decoder 112 may receive a message (e.g., picture timing SEI message or other message)…the decoder 112 may determine a separate decoding unit CPB removal delay parameter for each decoding unit in the access unit…¶0133, 0138-0139: In some configurations, the systems and methods disclosed herein may describe signaling sub-picture based Hypothetical Reference Decoder (HRD) parameters. For instance, the systems and methods disclosed herein describe modification to a picture timing Supplemental Enhancement Information (SEI) message). Note that the CPB removal delay parameter correspond to HRD parameter, see also DESHPANDE ¶0116-0117, 0225, wherein the one or more HRD parameters indicate information related to a coded picture buffer (CPB) removal delay of the decoding unit (¶0102-0104, 0131-0132: i.e., decoding unit CPB removal delay parameter). DESHPANDE does not explicitly disclose decod[ing]…per temporal sub-layer. However, SEO teaches decod[ing]…per temporal sub-layer (¶0084: The bitstream processor 410 may receive a bitstream encoded by the video encoder 300. ¶0162: the minimum buffer size that a decoder allocates for decoding a particular bitstream may be signaled by a parameter, which may be set for each temporal sub-layer in the sequence parameter set). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify DESHPANDE’s image decoder by incorporating the teaching of SEO as noted above, in order to reduce the picture buffer size as taught by SEO (¶0169). Regarding claim 3, the claim is drawn to an encoding method claim and recites the limitation analogous to claim 1, and is rejected due to the same reason set forth above with respect to claim 1. Regarding claim 4, the claim is drawn to an encoding method claim and recites the limitation analogous to claim 2, and is rejected due to the same reason set forth above with respect to claim 2. The following are the prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ramasubramonian et al. (US 20150103884 A1) describes “SIGNALING FOR SUB-DECODED PICTURE BUFFER (SUB-DPB) BASED DPB OPERATIONS IN VIDEO CODING” Title Wang (US 20150373373 A1) describes “SIGNALING HRD PARAMETERS FOR BITSTREAM PARTITIONS” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHNAEL AYNALEM whose telephone number is (571)270-1482. The examiner can normally be reached M-F 9AM-5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SATH PERUNGAVOOR can be reached at 571-272-7455. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHNAEL AYNALEM/Primary Examiner, Art Unit 2488
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Prosecution Timeline

Mar 11, 2025
Application Filed
Mar 06, 2026
Non-Final Rejection — §103, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
90%
With Interview (+13.9%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 662 resolved cases by this examiner. Grant probability derived from career allow rate.

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