Updated DETAILED ACTION
This office action is in response to applicant’s remarks filed on May 27, 2026 in application 19/077,227.
Claims 1, 3 are presented for examination. Claims 2, 4 are cancelled. Claim 1 is amended.
IDS submitted on March 12, 2025 was acknowledged.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed May 27, 2026 have been fully considered but they are not persuasive.
In regard to the 35 USC 101 rejections, applicant stated that the amended limitation of “without conducting another neutron irradiation test, by using the statistical analysis model” recites an improvement over conventional systems in that it calculates soft error rate without conducting another neutron irradiation test.
Examiner disagreed. Using an analysis model is well known in the art for determining without conducting another test.
In regard to the 35 USC 102 rejection, applicant stated that Sika does not disclose the amended limitations of “wherein the first feature amount and the second feature amount include at least the number of executions of each instruction, which is a feature amount corresponding to the soft error rate for each functional block include in the logic semiconductor device, and an in memory data residence time.”
Examiner disagreed. Based on the broadest interpretation of one of ordinary skill in the art of the claimed limitation “wherein the first feature amount and the second feature amount include at least the number of executions of each instruction” where the extracted feature amount at the time of execution of an evaluation program include at least a number of executions where one execution of an evaluation program instructions is included in the extracted feature would read on the claimed limitation. Furthermore, Sika executing the determining a radiation susceptibility metric for each selected particle strike model and determining a radiation susceptibility metric for the circuit piece (fig. 8A) is equated to the claimed evaluation program and the evaluation target program.
For these reasons, the rejections are maintained.
Claim Rejections - 35 U.S.C. § 101
35 U.S.C. § 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to an abstract idea without significantly more.
As to claim 1:
Step 1 Analysis: Is the claim to a process, machine, manufacture or composition of matter? See MPEP § 2106.03.
Yes, the claim is to a machine.
Step 2A Prong One Analysis: Does the claim recite an abstract idea, law of nature, or natural phenomenon? See MPEP § 2106.04(II)(A)(1).
“(b) a statistical analysis modeling procedure of performing statistical analysis modeling from the first feature amount of each of the plurality of irradiation evaluation programs and a soft error rate for each of the plurality of irradiation evaluation programs obtained in a neutron irradiation test conducted in advance, to generate a statistical analysis model; and (d) a soft error rate calculation procedure of calculating a soft error rate of the evaluation target program from the second feature amount of the evaluation target program, without conducting another neutron irradiation test, by using the statistical analysis model.”
Yes, the limitation “a statistical analysis modeling procedure” is the abstract idea of a mathematical relationship. See MPEP § 2106.04(a)(2)(I)(A).
Yes, the limitation “a soft error rate calculation procedure” is the abstract idea of a mathematical calculation. See MPEP § 2106.04(a)(2)(I)(C).
Step 2A Prong Two Analysis: Does the claim recite additional elements that integrate the judicial exception into a practical application? See MPEP § 2106.04(d).
“a hardware circuit configured to execute (a) a procedure of extracting a first feature amount at the time of execution of each of a plurality of irradiation evaluation programs from the plurality of irradiation evaluation programs and their program input conditions; and (c) a procedure of extracting a second feature amount at the time of execution of an evaluation target program from the evaluation target program and its program input conditions; wherein the first feature amount and the second feature amount include at least the number of executions of each instruction, which is a feature amount corresponding to the soft error rate for each functional block included in the logic semiconductor device, and an in-memory data residence time”
No, the limitation “a procedure of extracting a first feature and a procedure of extracting a second feature, wherein the first feature amount and the second feature amount include at least the number of executions of each instruction, which is a feature amount corresponding to the soft error rate for each functional block included in the logic semiconductor device, and an in-memory data residence time” is an additional element that amounts to adding insignificant extra-solution activity to the judicial exception. See MPEP §§ 2106.04(d), 2106.05(g).
No, the limitation “a hardware circuit configured to execute” is an additional element that amounts to adding the words “apply it” (or an equivalent) with the judicial exception or merely uses a computer in its ordinary capacity as a tool to perform an existing process. See MPEP §§ 2106.04(d), 2106.05(f)(2).
Step 2B Analysis: Does the claim recite additional elements that amount to significantly more than the judicial exception? See MPEP § 2106.05.
“a hardware circuit configured to execute (a) a procedure of extracting a first feature amount at the time of execution of each of a plurality of irradiation evaluation programs from the plurality of irradiation evaluation programs and their program input conditions; and (c) a procedure of extracting a second feature amount at the time of execution of an evaluation target program from the evaluation target program and its program input conditions;”
No, the limitation “a procedure of extracting a first feature and a procedure of extracting a second feature, wherein the first feature amount and the second feature amount include at least the number of executions of each instruction, which is a feature amount corresponding to the soft error rate for each functional block included in the logic semiconductor device, and an in-memory data residence time” is an additional element that generally links the use of the judicial exception to a particular technological environment or field of use. See MPEP § 2106.05(h).
No, the limitation “a hardware circuit configured to execute” is an additional element that amounts to adding the words “apply it” (or an equivalent) with the judicial exception or merely uses a computer in its ordinary capacity as a tool to perform an existing process. See MPEP § 2106.05(f)(2).
As to claim 3:
Step 1 Analysis: Is the claim to a process, machine, manufacture or composition of matter? See MPEP § 2106.03.
Yes, the claim is to a machine.
Step 2A Prong One Analysis: Does the claim recite an abstract idea, law of nature, or natural phenomenon? See MPEP § 2106.04(II)(A)(1).
The analysis of the parent claim is incorporated.
Step 2A Prong Two Analysis: Does the claim recite additional elements that integrate the judicial exception into a practical application? See MPEP § 2106.04(d).
The analysis of the parent claim is incorporated.
Step 2B Analysis: Does the claim recite additional elements that amount to significantly more than the judicial exception? See MPEP § 2106.05.
The analysis of the parent claim is incorporated.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 is/are rejected under 35 U.S.C. 102(S)(1) as being anticipated by Sika (US 2023/0152367)
In regard to claim 1, Sika teaches a soft error rate evaluation system evaluating the radiation resistance of electronic equipment which adopts a logic semiconductor device, comprising:
(a) a procedure of extracting a first feature amount at the time of execution of each of a plurality of irradiation evaluation programs from the plurality of irradiation evaluation programs and their program input conditions (semiconductor Design Evaluation module, fig. 10 1016, para. 161, using a semiconductor design functional simulator to determine expected output values for the circuit piece by simulating functionality of the layout information of the circuit piece with the determined stimuli data for the circuit piece, para. 144);
(b) a statistical analysis modeling procedure of performing statistical analysis modeling from the first feature amount of each of the plurality of irradiation evaluation programs and a soft error rate for each of the plurality of irradiation evaluation programs obtained in a neutron irradiation test conducted in advance, to generate a statistical analysis model (for each selected particle strike model of a circuit piece, determine a radiation susceptibility metric, fig. 8A, S803, by comparing functional results generated by functional simulation of the particle strike model with functional results generated by functional simulation of the circuit piece, para. 81);
(c) a procedure of extracting a second feature amount at the time of execution of an evaluation target program from the evaluation target program and its program input conditions (analog circuit particle strike models, fig. 10 1015, para. 161); and
(d) a soft error rate calculation procedure of calculating a soft error rate of the evaluation target program (determines a Soft Error Rate (SER) value and a Failure in Time (FIT) value from the overall radiation-susceptibility metric for the first semiconductor circuit, para. 152-153) from the second feature amount of the evaluation target program by using the statistical analysis model (for each circuit piece, determining a radiation susceptibility metric for the circuit piece based on the radiation susceptibility metrics generated for each selected particle strike model of the circuit piece, para. 81);
wherein the first feature amount and the second feature amount include at least the number of executions of each instruction, which is a feature amount corresponding to the soft error rate for each functional block included in the logic semiconductor device, and an in-memory data residence time (the RSAP method begins with a Decomposition Process component separating a placed and routed instance of a candidate semiconductor circuit design into constituent smaller pieces called tiles, fig. 6, para. 66-73, for each selected particle strike model of a circuit piece, determining a radiation susceptibility model and for each circuit piece, determining a radiation susceptibility metric for the circuit piece, fig. 8A, S803, S804, para. 81).
In regard to claim 3, Sika teaches the soft error rate evaluation system according to claim 1, wherein the statistical analysis model is a first-order polynomial multiple regression analysis model (strike model library, Soft Error Rates (SER) and Failure In Time (FIT) figures are derived from these design radiation-susceptibility metrics using Bayesian model and analysis, para. 66-73).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Kim et al. (US 2024/0337689) evaluating radiation of a semiconductor device
Soeda (US 11,054,460) soft error inspection due to radiation
Nakagawa et al. (US 10,686,080) changes mode with regard to soft errors
Uezono et al. (US 10,401,424) evaluating and calculating incidence of soft errors
Nakagawa et al. (US 2019/0229216) reference value set by the amount of received radiation and the number of soft errors caused in an inspection memory circuit
Friend et al. (US 6,909,159) detect radiation via soft error rate, fig. 6
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Khan et al. (US 2024/0036993) (Cisco) statistical learning and/or statistical models for SER protection
Mishra et al. (US 2023/0185648) predict SER relative to expected SER
Sika (US 2021/0148967) (LUCID) SER for radiation-susceptibility analysis
Sika (US 2019/0302177) (LUCID) SER for radiation-susceptibility analysis
OTA et al. (US 2020/0081757) (Renesas Electronics) SER caused by radiation analysis
Lamb (US 2011/0145771) (IBM) comparing the expected result with actual error log for SER estimation
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LOAN TRUONG whose telephone number is 408-918-7552. The examiner can normally be reached on 10AM-6PM PST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached on 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Loan L.T. Truong/Primary Examiner, Art Unit 2114 Loan.truong@uspto.gov
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