Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 4, 13 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, it is unclear to the examiner how “a first processing for modifying a bit in the intersection without inverting the bit” is possible. The examiner interprets a bit to be a binary piece of information, only able to store one of two states: a 1 or a 0. With this in mind, the question arises “how is it possible to “modify a bit… without inverting the bit.” In the examiner’s view, the only possible modification to a bit is inversion. While this limitation is supported in the specification (para. 83), it is not explained what the modification is, if not an inversion. In fact, any other references to “modify”, “modifying” or “modification” in the specification point directly to inversion of bits, and nothing else. (see para. 47: “the modification unit 104 performs modification processing for modifying the selected bits. For example, the modification processing is inverting the selected bits.” Also see para. 51: “the process of modifying (inverting) the selected bits…”) Appropriate clarification/and or correction is required.
Claim 13 corresponds to claim 3, and is rejected accordingly.
Regarding claim 4, it is not clear what exactly is meant by “a maximum value J for a number of bits to be inverted satisfies J >= max(floor(I/2) – t, 0), where I is a size of the intersection and t is a correction ability of the first error correction code.” This limitation does not appear to be limiting the performance of the claimed invention. If J is a maximum number of bits to be inverted, in other words, a number of bits to be inverted must be less than or equal to J- and J is only constrained by the equation J >= max(floor(I/2) – t, 0), then there is no real constraint on the actual number of bits to be inverted. J could be infinity, therefore always fulfilling its single constraint. Then, because J is the maximum value of bits to be inverted, there is no constraint on the actual number of bits to be inverted, because that number will always be less than infinity. Appropriate clarification and/or correction is required.
Claim 14 corresponds to claim 4, and is rejected accordingly.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 10-17, and 20 are rejected under 35 U.S.C. 102a1 as being anticipated by Avi (US Patent No. 10628255).
Regarding claim 1, Avi teaches:
A memory system comprising:
a nonvolatile memory that stores a concatenated code including a first error correction code and a second error correction code, the first error correction code being generated with data to be stored, the second error correction code being generated with the first error correction code and being an N- dimensional error correction code in which at least one of symbols constituting the code is protected by N component code groups, N being an integer greater than 1; (see fig. 5, CRC 50(2) considered to be the first error correction code generated with data to be stored, inner and outer codes considered to be second error correction code. Also see fig. 7, depicting the generation of 4 dimensions (D0-D3) of the second code, generated with CRC bits from CRC compute 71. And see col. 2, lines 57-66: According to an embodiment of the present invention there may be provided a flash memory controller that may include a memory and a processor, wherein the memory may be configured to store a multi-dimensional encoded codeword that may include a payload and a redundancy section; wherein the payload may include data and an error detection process signature; wherein the processor may be configured to evaluate, during a multi-dimensional decoding process of the multi-dimensional encoded codeword, an hypothesis regarding a content of the payload.)
and a memory controller configured to: read information from the nonvolatile memory; perform, for the information, a second decoding processing with the second error correction code; (see fig. 9: outers 130 (outers decoding) is considered to be a second decoding processing with the second error correction code on read information.)
in a case that a decoding in the second decoding processing fails, perform, for the information which reflects a correction result of the second decoding processing, a first decoding processing with the first error correction code; (whether or not the outer decoding 130 fails, CRC update 132 and CRC match 134 follow, performing a first decoding process with the first error correction code, by updating the CRC and checking to see if the CRC signature matches a CRC value calculated by processing the decoded payload. It is obvious that the first decoding process is performed on a correction result of the outers decoding 130, because if there was no correction from outers decoding 130, the CRC would not need to be updated in step 132.)
in a case that a decoding in the first decoding processing fails, identify an intersection of component codes that are in two or more respective different dimensions and each include an error; and perform a modification processing for modifying a symbol in the intersection and further perform the first decoding processing. (See fig. 9: The first decoding process fails when a match is not found between the CRC signature and the CRC value calculated by processing the decoded payload, represented in CRC match 134 -> No. In this case, intersections decoding is performed in step 140. Also see col. 12, lines 10-17: According to another embodiment of the invention, the intersections’ decoding may include multiple joint intersections, namely a plurality of unsolved codes in each dimension, for which the decoder enumerates over the intersecting bits, and attempts to decode component codes during enumeration. The decoder checks the CRC match for all bit flips.) The bit flips here are considered to be modification processing for modifying a symbol in the intersection, and further checking the CRC match is a further performance of the first decoding processing. Additionally, unsolved codes are considered to be component codes including an error.
Regarding claim 2, Avi teaches the memory system of claim 1. Avi further teaches:
wherein in a case that the memory controller identifies intersections fewer than or equal to a threshold number, the memory controller is further configured to modify a symbol in an intersection and further perform the first decoding processing. (see col. 12, lines 10-17: According to another embodiment of the invention, the intersections’ decoding may include multiple joint intersections, namely a plurality of unsolved codes in each dimension, for which the decoder enumerates over the intersecting bits, and attempts to decode component codes during enumeration. The decoder checks the CRC match for all bit flips.) The threshold could be considered to be infinity, any time the decoder detects any intersections less than infinity it modifies a symbol before further performing the first decoding processing (CRC update/match check). The threshold could further be considered to be any arbitrary number, and the modification processing and further first decoding processing are performed when the intersections are less than or equal to the threshold, and when the intersections are greater than the threshold. (Also see col. 14, lines 17-30: According to another embodiment of this invention, with only a few unsolved packets in each dimension [a few considered to be intersections under a threshold], the soft decoder performs CRC assisted decoding on intersections. When a few packets are not solved in every dimension, the soft decoder may decide not to perform the usual soft decoding per packet, and instead perform enumeration over the intersecting bits of the unsolved packet [i.e., performing intersection decoding]. The enumeration over the intersecting bits of unsolved packets includes enumeration of single bit hypotheses, then two bit hypotheses, up to N-bit hypotheses. For every hypothesis, no decoder solving is required, only a CRC signature update is required. If a CRC match is found during this enumeration, the decoding success test is done, and possible successful decoder termination is possible.) CRC signature update and match check is considered to be the first decoding process. The enumeration over hypotheses is considered to include a modification process because the CRC is updated, meaning a correction has been made.
Regarding claim 3, Avi teaches the memory system of claim 1. Avi further teaches:
wherein the symbols are bits, and the modification processing comprises a first processing for modifying a bit in the intersection without inverting the bit, and a second processing for modifying a bit in the intersection after inverting the bit. (Also see col. 12, lines 10-17: According to another embodiment of the invention, the intersections’ decoding may include multiple joint intersections, namely a plurality of unsolved codes in each dimension, for which the decoder enumerates over the intersecting bits, and attempts to decode component codes during enumeration. The decoder checks the CRC match for all bit flips.) As discussed in the 112B rejection of this claim, it is unclear how a bit can be modified without inversion. Therefore, this limitation is interpreted (until the 112B issues can be resolved) as: “the modification processing comprises a first processing for modifying a bit in the intersection by inverting the bit.” An art rejection is supplied here for the sake of completeness, but will be subject to revision upon resolution of the 112B issues.
Regarding claim 4, Avi teaches the memory system of claim 3. Avi further teaches:
wherein a maximum value J of a number of bits to be inverted satisfies J >= max (floor (T/2) - t, 0), where I is a size of the intersection and t is a correction ability of the first error correction code. (Also see col. 12, lines 10-17: According to another embodiment of the invention, the intersections’ decoding may include multiple joint intersections, namely a plurality of unsolved codes in each dimension, for which the decoder enumerates over the intersecting bits, and attempts to decode component codes during enumeration. The decoder checks the CRC match for all bit flips.) As discussed in the 112B rejection of this claim, it is unclear how a maximum value of bits to be inverted would be constrained at all by requiring the maximum possible number of bits to be inverted to be greater than or equal to any number. It is obvious to assume that at the most basic level, the maximum bits that are allowed to be inverted is I (the size of the intersection), so J=I, and J will always be >= max(floor(T/2) – t, 0), because I >= 0 and I >= max(floor(T/2) – t, 0). An art rejection is supplied here for the sake of completeness, but will be subject to revision upon resolution of the 112B issues.
Regarding claim 5, Avi teaches the memory system of claim 1. Avi further teaches:
wherein the memory controller identifies the intersection using feature information indicating a correctness of a correction made with the second error correction code. (See col. 8, lines 48-50: The main steps of intersections decoding include: (I) Mapping of bit-sets which are obtained by intersections of non-solved packets on different dimensions; Also see col. 11, lines 23-32: If step 134 finds that there is no CRC match then step 134 is followed by step 140 of intersections decoding where a CRC match may be tested for every bit flip hypothesis (which precedes the solver decoding per code component). This may be done in order to resolve scenarios of multiple redundancy errors, which cannot be solved by the code component decoder and by enumeration over the intersected bits (with other unsolved component codes) with a CRC match test, the remaining errors within the intersection may be resolved.) Whether or not a component code (or packet) is solved is considered to be the feature information. A solved component code indicates that a correction made with the second error correction code was correct or that a correction was unnecessary, and an unsolved component code indicates that a correction attempted with the second error correction code was unsuccessful.
Regarding claim 6, Avi teaches the memory system of claim 5. Avi further teaches:
wherein the feature information includes information indicating syndromes of component codes in the N component code groups. (See col. 8, lines 48-50: The main steps of intersections decoding include: (I) Mapping of bit-sets which are obtained by intersections of non-solved packets on different dimensions; Also see col. 11, lines 23-32: If step 134 finds that there is no CRC match then step 134 is followed by step 140 of intersections decoding where a CRC match may be tested for every bit flip hypothesis (which precedes the solver decoding per code component). This may be done in order to resolve scenarios of multiple redundancy errors, which cannot be solved by the code component decoder and by enumeration over the intersected bits (with other unsolved component codes) with a CRC match test, the remaining errors within the intersection may be resolved. Also see col. 16, line 66- col. 17, line 3: To have a reliable decoding (sufficiently low miss-detection) when CRC is cleared, the decoder checks whether there are enough solved packets (component codes)—the indication for solved component codes is a zero-syndrome per packet.)
Regarding claim 7, Avi teaches the memory system of claim 5. Avi further teaches: wherein the feature information includes reliability information indicating degrees of correctness of results of correction made with component codes in the N component code groups. (See col. 8, lines 48-50: The main steps of intersections decoding include: (I) Mapping of bit-sets which are obtained by intersections of non-solved packets on different dimensions; Also see col. 11, lines 23-32: If step 134 finds that there is no CRC match then step 134 is followed by step 140 of intersections decoding where a CRC match may be tested for every bit flip hypothesis (which precedes the solver decoding per code component). This may be done in order to resolve scenarios of multiple redundancy errors, which cannot be solved by the code component decoder and by enumeration over the intersected bits (with other unsolved component codes) with a CRC match test, the remaining errors within the intersection may be resolved. Also see col. 16, line 66- col. 17, line 3: To have a reliable decoding (sufficiently low miss-detection) when CRC is cleared, the decoder checks whether there are enough solved packets (component codes)—the indication for solved component codes is a zero-syndrome per packet.) The syndromes of the component codes are considered to represent degrees of correctness, and they result from corrections made with component codes in the second decoding process (prior to the intersection decoding). The syndromes are used to determine which component codes are solved, which is used to determine which intersections to use for intersection decoding.
Regarding claim 10, Avi teaches the memory system of claim 1. Avi further teaches wherein:
in a case that the decoding the second decoding processing succeeds, the memory controller is further configured to output a notification of successful decoding, and in a case that the decoding the first decoding processing succeeds, the memory controller is further configured to output the notification of successful decoding. (see fig. 9: When the first and second decoding process succeeds, the decoding is considered to be successful and can be terminated (outers 130 -> crc update 132 -> crc match 134 -> yes -> decoding done -> Yes -> decoder termination 160). Also see col. 11, lines 51-67: According to another embodiment of this invention, when a CRC match is found, a decoding success is likely. To provide a reliable indication of decoding success (during step 150), it is possible to combine the CRC match indication with a comparison of a zero syndrome counter to a threshold: TH.sub.S≤|{x∈D.sub.1,D.sub.2,D.sub.3,s.t. S(x)=0}| If the number of solved code components (packets) on all code dimensions D1,D2,D3 (or per a certain dimension) in this example is greater than THs, then if a CRC match was found a highly reliable decoder success indication may be provided. As said, in systematic codes it is not always required to succeed detecting and correcting all errors, it may be enough to provide only the decoded information bits (required for output) with sufficiently low miss-detection probability.) At least the decoder success indication or the output decoded information bits are considered to be an output of successful decoding, and is only output when a CRC match is found (first decoding success), and enough component codes are solved to provide a highly reliable output (second decoding success).
Claims 11-17 and 20 correspond to claims 1-7 and 1 (respectively), and are rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8, 9, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Avi in view of Keays (US Publication No. 20050268203).
Regarding claim 8, Avi teaches the memory system of claim 5. Avi further teaches:
The memory system of claim 1, wherein the first error correction code [is a CRC code] and component codes in the N component code groups are each a Bose- Chaudhuri-Hocquenghem (BCH) code. (see col. 3, lines 20-23 and fig. 5: FIG. 5 illustrates a prior art three dimensional folded BCH encoding wherein a K-bit payload includes a single CRC signature;)
However, Avi does not explicitly teach:
The first error correction code [is]… a Bose-Chaudhuri-Hocquenghem (BCH) code.
Various error correcting and detecting code types are considered to be well known in the art to be obvious alternatives to each other. To further support this point, Keays is presented.
Keays teaches:
BCH codes and CRC codes are both well known in the art to be ECC codes and therefore are obvious alternatives (see para. 6: In memory and memory systems, ECC's allow errors in the data stored in the memory to be detected and in many cases corrected. ECC codes include block codes, that are associated with a block of stored data (such as a memory data segment, a memory data block, or a memory data sector), and stream codes, that are typically utilized with streams of transmitted data. ECC codes include, but are not limited to, Hamming codes, Reed-Solomon (R-S) codes, Bose-Chaudhuri-Hochquenghem (BCH) codes, circular redundancy check codes (CRC-32), Golay codes, Reed-Muller codes, Goppa codes, and Denniston codes.)
One of ordinary skill in the art would readily recognize that replacing the CRC signature in Avi’s memory system as a BCH code would be an well-known and obvious alternate implementation.
Regarding claim 9, Avi teaches the memory system of claim 5. Avi further teaches:
The memory system of claim 1, wherein the first error correction code [is a CRC code] and component codes in the N component code groups are each a [Bose- Chaudhuri-Hocquenghem (BCH) code]. (see col. 3, lines 20-23 and fig. 5: FIG. 5 illustrates a prior art three dimensional folded BCH encoding wherein a K-bit payload includes a single CRC signature;)
However, Avi does not explicitly teach:
The first error correction code and component codes in the N component code groups are each a Reed-Solomon (RS) code.
Various error correcting and detecting code types are considered to be well known in the art to be obvious alternatives to each other. To further support this point, Keays is presented.
Keays teaches:
BCH codes, CRC codes, and RS codes are all well known in the art to be ECC codes and therefore are obvious alternatives (see para. 6: In memory and memory systems, ECC's allow errors in the data stored in the memory to be detected and in many cases corrected. ECC codes include block codes, that are associated with a block of stored data (such as a memory data segment, a memory data block, or a memory data sector), and stream codes, that are typically utilized with streams of transmitted data. ECC codes include, but are not limited to, Hamming codes, Reed-Solomon (R-S) codes, Bose-Chaudhuri-Hochquenghem (BCH) codes, circular redundancy check codes (CRC-32), Golay codes, Reed-Muller codes, Goppa codes, and Denniston codes.)
One of ordinary skill in the art would readily recognize that replacing the CRC signature in Avi’s memory system as a RS code, and the BCH component codes as RS component codes would be a well-known and obvious alternate implementation.
Claims 18 and 19 correspond to claims 8 and 9 (respectively), and are rejected accordingly.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
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/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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