DETAILED ACTION
This is in response to the application filed on March 12, 2025 in which claims 1 – 20 are presented for examination.
Status of Claims
Claims 1 – 20 are pending, of which claims 1, 13, and 20 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/6/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: Applicant’s specification refers to both ‘tap’ and ‘TAP’ throughout the disclosure. The examiner recommends amending the specification to choose either ‘tap’ or ‘TAP’ but not both, for consistency and clarity.
Appropriate correction is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 4, 7, 9, 11 – 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Querbach et al., U.S. Patent Application 2006/0265161 (hereinafter referred to as Querbach) (from Applicant’s IDS) in view of Brown, U.S. Patent Application 2022/0043760 (hereinafter referred to as Brown) (from Applicant’s IDS), further in view of Srivastava et al., U.S. Patent Application 2019/0189226 (hereinafter referred to as Srivastava).
Referring to claim 1, Querbach discloses “A method for training a” memory interface (Fig. 1 memory hub 14 with I/O circuit 20b), “the method comprising:” “triggering training of the” bus ([0014] training modes include [0022] initial link training mode and [0025] active link training mode. [0041] the initial training mode is indicated by the assertion of a signal called "INIT_TRAIN," and the active training link mode is indicated by the assertion of a signal called "ACT_TRAIN."), and “performing an iterative training operation to train the” bus “for respective” “clock delay values of a plurality of” “clock delay values for” a “clock delay, the training operation including: adjusting, for a respective” “clock delay value of the plurality of” “clock delay values, the” “clock delay of the” bus ([0019] the I/O circuit 20 applies a strobe delay that falls within a range 90 of possible strobe delays. [0021] The goal of the link training described herein is to define the middle of the pass region 102, or the midpoint of the delays, for purposes of centering the timing edges of the data strobe signal in the data eyes of the data bit signal. [0022] “a technique 120 that is used by the I/O circuit 20 includes testing (block 122) all of the delays over the range 90 (see FIG. 2) of delays for purposes of generating a test vector”); “comparing the” received “data with a reference value” ([0022] if the data that is captured matches the test pattern of data); “and storing, based on the comparing, a pass/fail status of the” “data” ([0022] if the captured data matches the test pattern of data), then the I/O circuit uses a flag, such as "0" to designate the tested delay as passing. Conversely, if the captured data does not match the test pattern, then the I/O circuit 20 uses another flag, such as a binary value of "1", to designate the failure. The result of this technique is the generation of test vector, a string of binary "1" and "0"s); “determining, based on a plurality of stored pass/fail statuses obtained from the training operation, a selected” “clock delay value for the” “clock delay of the” bus; “and setting the” “clock delay of the” bus “to the selected” “clock delay value” ([0022] “the I/O circuit 20 tests each delay of the range 90; and a binary value is assigned indicating the result of the test.” [0037] – [0038] clock delay circuit evaluates and applies the appropriate delay to the clock signal for the purposes of optimizing the delay that is applied to the clock signal).
Querbach does not appear to explicitly disclose “training a serial peripheral interface (SPI) monitor for high-frequency operation” including triggering training “of the SPI monitor.” Thus, it follows that Querbach does not appear to explicitly disclose “performing an iterative training operation to train the SPI monitor for respective SPI clock delay values of a plurality of SPI clock delay values for an SPI clock delay, the training operation including: adjusting, for a respective SPI clock delay value of the plurality of SPI clock delay values, the SPI clock delay of the SPI monitor; reading, via the AP, data from an external SPI flash memory; comparing the read data with a reference value; and storing, based on the comparing, a pass/fail status of the read data; determining, based on a plurality of stored pass/fail statuses obtained from the training operation, a selected SPI clock delay value for the SPI clock delay of the SPI monitor; and setting the SPI clock delay of the SPI monitor to the selected SPI clock delay value.”
However, Brown discloses “training a serial peripheral interface (SPI) monitor” including triggering training “of the SPI monitor” ([0003] determining parameters for SPI that is usable by the processor to read successfully from the flash memory). Further, Brown discloses “respective SPI clock delay values of a plurality of SPI clock delay values for an SPI clock delay” ([0047] read transactions from the DDR flash memory 120 are performed with the SPI 110 set to different values of TX delay and RD cycle). Brown also discloses “adjusting, for a respective SPI clock delay value of the plurality of SPI clock delay values, the SPI clock delay of the SPI monitor; reading, via the AP, data from an external SPI flash memory” ([0043] performing a plurality of test read transactions with the DDR flash memory 120 at each of the first and second values of RD cycle and comparing the results of the plurality of test read transactions), “comparing the read data with a reference value” ([0032] and [0042] A read is characterized as successful when the data read from the DDR flash memory 120 is an exact match for data previously written to the DDR flash memory 120). Brown further discloses “based on the comparing, a pass/fail status of the read data” ([0032] and [0042] A read is characterized as successful when the data read from the DDR flash memory 120 is an exact match for data previously written to the DDR flash memory 120) and “determining” “a selected SPI clock delay value for the SPI clock delay of the SPI monitor; and setting the SPI clock delay of the SPI monitor to the selected SPI clock delay value” ([0050] passing read transactions, successful tuning points, and selecting. Fig. 9 and [0056] program the SPI 110 to a tuning point having that RD cycle value and values of TX and RX between the BL and TR tuning points).
Querbach and Brown are analogous art because they are from the same field of endeavor, which is tuning/training of a communication bus by using delays.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Querbach and Brown before him or her, to modify the teachings of Querbach to include the teachings of Brown so that the bus is an SPI bus and the bus is between a processor and a memory.
The motivation for doing so would have been to allow the SPI to reliably program and read data to/from the DDR flash device (as stated by Brown at [0018]).
Neither Querbach nor Brown appears to explicitly disclose training a memory interface “for high-frequency operation,” “storing a training address in a non-volatile memory; comparing an address accessed by an application processor (AP) with the training address; providing a reset signal or an interrupt signal to the AP in response to an address match between the address and the training address, the providing triggering training of the SPI monitor.”
However, Srivastava discloses another link training method that adjusts delay ([0036]) “for high-frequency operation” ([0001] flash memory devices at high speed and [0012]) including “storing a training address in a non-volatile memory; comparing an address accessed by an application processor (AP) with the training address; providing a reset signal or an interrupt signal to the AP in response to an address match between the address and the training address, the providing triggering training” ([0041] a write to a LUN address provides indication that the host wants to initiate link training. Figs. 5 and 7 show iterative training. [0078] link training after a reset of the host 102 and/or the component 104, and/or at any appropriate time. [0079] component 104 associated with a memory 2160, [0088] memory 2160 can be nonvolatile).
Querbach, Brown, and Srivastava are analogous art because they are from the same field of endeavor, which is tuning/training of a communication bus by using delays.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Querbach, Brown, and Srivastava before him or her, to modify the teachings of Querbach and Brown to include the teachings of Srivastava so that a signal is provided to the AP in response to an address match between the access address and a stored training address, the providing of the signal triggering training.
The motivation for doing so would have been to provide a means for entering training mode without needing to add another instruction/command to the instruction set.
Therefore, it would have been obvious to combine Srivastava with Querbach and Brown to obtain the invention as specified in the instant claim.
As per claim 2, Querbach discloses the adjusting comprises setting the respective” “delay value in a tap control register” (Fig. 9 delay adjustment circuit 410 middle register 494 holds delay value).
As above, Querbach does not appear to explicitly disclose “the respective SPI clock delay value in a tap control register of the SPI monitor.”
However, Brown discloses “the respective SPI clock delay value” and “the SPI monitor” ([0003] determining parameters for SPI that is usable by the processor to read successfully from the flash memory. [0043] performing a plurality of test read transactions with the DDR flash memory 120 at each of the first and second values of RD cycle and comparing the results of the plurality of test read transactions. [0050] passing read transactions, successful tuning points, and selecting. Fig. 9 and [0056] program the SPI 110 to a tuning point having that RD cycle value and values of TX and RX between the BL and TR tuning points).
As per claim 3, Brown discloses “the reference value is obtained from a previously stored data value and the comparing determines if the read data aligns with an expected outcome” ([0032] and [0042] A read is characterized as successful when the data read from the DDR flash memory 120 is an exact match for data previously written to the DDR flash memory 120) “based on the respective SPI clock delay value of a current iteration of the training operation” ([0047] read transactions from the DDR flash memory 120 are performed with the SPI 110 set to different values of TX delay and RD cycle).
As per claim 4, Querbach discloses “the plurality of stored pass/fail statuses” ([0022] if the captured data matches the test pattern of data), then the I/O circuit uses a flag, such as "0" to designate the tested delay as passing. Conversely, if the captured data does not match the test pattern, then the I/O circuit 20 uses another flag, such as a binary value of "1", to designate the failure. The result of this technique is the generation of test vector, a string of binary "1" and "0"s).
While neither Querbach nor Brown nor Srivastava appears to explicitly disclose the pass/fail statuses “are stored in a static random-access memory (SRAM),” it would have been obvious to one of ordinary skill in the art to store the statuses in any type of memory. Specifically, regarding SRAM, this memory type provides for fast access times and low latency.
As per claim 7, Brown discloses “the non-volatile memory is a flash memory” ([0047] read transactions from the DDR flash memory 120 are performed with the SPI 110 set to different values of TX delay and RD cycle).
As per claim 9, Brown discloses “the data read from the external SPI flash memory are a predefined set of bytes of data” ([0032] and [0042] A read is characterized as successful when the data read from the DDR flash memory 120 is an exact match for data previously written to the DDR flash memory 120).
As per claims 11 and 12, Querbach discloses “the determining of the selected” “clock delay value includes: identifying, from the stored pass/fail status” ([0022] if the captured data matches the test pattern of data), then the I/O circuit uses a flag, such as "0" to designate the tested delay as passing. Conversely, if the captured data does not match the test pattern, then the I/O circuit 20 uses another flag, such as a binary value of "1", to designate the failure. The result of this technique is the generation of test vector, a string of binary "1" and "0"s), “a lowest indexed” “clock delay value that passed the comparing by matching the read data with the reference value; identifying, from the stored pass/fail status, a highest indexed” “clock delay value that passed the comparing by matching the read data with the reference value; and ascertaining an average value of the lowest indexed” “clock delay value and the highest indexed” “clock delay value” and “the selected” “clock delay value is the average value” ([0019] a pass region aligns with the data eye, a fail region in a beginning of the range of delays, and a fail region at the end of the range of delays. [0020] locating the midpoint of the pass region by determining the average of the left and right boundaries).
As above, Querbach does not appear to explicitly disclose “SPI clock delay value.”
However, Brown discloses “SPI clock delay value” ([0047] read transactions from the DDR flash memory 120 are performed with the SPI 110 set to different values of TX delay and RD cycle).
It would have been obvious to combine Brown with Querbach so that “the determining of the selected SPI clock delay value includes: identifying, from the stored pass/fail status, a lowest indexed SPI clock delay value that passed the comparing by matching the read data with the reference value; identifying, from the stored pass/fail status, a highest indexed SPI clock delay value that passed the comparing by matching the read data with the reference value; and ascertaining an average value of the lowest indexed SPI clock delay value and the highest indexed SPI clock delay value” and “the selected SPI clock delay value is the average value.”
Referring to claim 13, claim 1 recites the corresponding limitations as that of claim 13. Therefore, the rejection of claim 1 applies to claim 13. Further, Querbach includes “a comparator” to compare a received address with a training address ([0022] if the data that is captured matches the test pattern of data).
Also, Srivastava teaches “trigger circuitry” to send a reset/interrupt to the processor ([0041] a write to a LUN address provides indication that the host wants to initiate link training. [0078] link training after a reset of the host 102 and/or the component 104, and/or at any appropriate time).
Finally, Querbach teaches “training control circuitry” to carry out the training (Figs. 8 and 9 show circuitries for delaying clock signals, creating pass/fail test vectors, etc.).
As per claims 14 and 15, Srivastava teaches “the trigger circuitry comprises a communication interface to send the reset signal or the interrupt signal to the AP” and “the communication interface is one of a general purpose input output (GPIO), a secure inter-integrated circuit (I2C), an improved inter-integrated circuit (I3C), and an interrupt” ([0041] a write to a LUN address provides indication that the host wants to initiate link training. [0078] link training after a reset of the host 102 and/or the component 104, and/or at any appropriate time).
Note, claim 16 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 16.
Also, Querbach discloses “tap controller to set the respective” “delay value in a tap control register” (Fig. 9 delay adjustment circuit 410 middle register 494 holds delay value).
Note, claim 17 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 3 applies to claim 17.
Also, Querbach teaches “training control circuitry” to carry out the training (Figs. 8 and 9 show circuitries for delaying clock signals, creating pass/fail test vectors, etc.).
Note, claim 18 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 18.
Also, Querbach teaches “training control circuitry” to carry out the training (Figs. 8 and 9 show circuitries for delaying clock signals, creating pass/fail test vectors, etc.).
Referring to claim 20, claim 1 recites the corresponding limitations as that of claim 20. Therefore, the rejection of claim 1 applies to claim 20.
Further, Querbach discloses “A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to” carry out the method of claim 1 ([0052] In order to establish the delays for these registers 510, in accordance with some embodiments of the invention, the processor 502 executes a program 526 that is stored in a system memory 524 for purposes of implementing one or more of the techniques 120 (FIG. 3), 150 (FIG. 4) and 180 (FIG. 5) that are discussed above).
Also, Brown discloses “A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to” carry out the method of claim 1 ([0023] instructions 105 that, when executed by the core processor 102, cause the core processor 102 to perform the various functionalities described herein. The memory 104 is one example of a non-transitory, computer-readable medium).
Allowable Subject Matter
Claims 5, 6, 8, 10, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent 7480360 is the granted patent to Querbach.
U.S. Patent 11935613 is the granted patent to Brown.
U.S. Patent 10347347 is the granted patent to Srivastava.
U.S. Patent Application 20180293196 teaches link training with programming a clock.
U.S. Patent Application 20200110716 teaches bus training with delay times.
U.S. Patent Application 20190034365 and Patent 10621121 teach bus training with sweeping over a range of delays.
U.S. Patent Applications 20170110165, 20170110169 and Patents 9959918, 9754650 teach bus training and an adjustable delay of a chip select signal.
U.S. Patent Application 20220114131 teaches bus training and stalling a reset of a host until after training is complete.
U.S. Patent Application 20180095806 and Patent 10216550 teach bus training and resetting the processor in response to a training signal.
Maria George, ‘Memory Interfaces Data Capture Using Direct Clocking Technique’ Xilinx Application Note teaches a 64-tap delay line for a memory interface clock and finding a midpoint of the data eye.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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