Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 03/12/2025 and the preliminary amendment filed on 04/22/2025.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/12/2025, 08/26/2025, and 01/30/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
FIG. 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated, the description identifying FIG. 1 as “a schematic diagram of an internal circuit configuration of a conventional power supply” (see page 4, lines 1-2). See MPEP § 608.02(g).
The drawings are objected to under 37 CFR 1.84(a)(1), 37 CFR 1.84(l), and 37 CFR 1.84(m) because FIG. 5A, FIG. 5B, FIG. 6A, FIG. 6B, FIG. 7A to FIG. 7H, FIG. 8A to FIG. 8H, the sub-diagram (b) of FIG. 10A, FIG. 13A, FIG. 13B, FIG. 13C, and FIG. 15 are grayscale halftone reproductions containing continuous-tone shading and extensive solid black areas, and are not made with black solid lines. Every line, number, and letter of a drawing must be durable, clean, black, sufficiently dense and dark, and uniformly thick and well-defined, and solid black shading areas are not permitted.
The drawings are objected to under 37 CFR 1.84(p)(4) because the same part of the invention is designated by different reference characters in different views: Regarding FIG. 3A, FIG. 3B, and FIG. 3C, “SP-1” appears that it should read as “SP_1”, because the primary-side switch bridge arm is designated “SP_1” in FIG. 4A, FIG. 4C, and FIG. 4D and throughout the description.
Regarding FIG. 14A and FIG. 14B, “SR_1” appears that it should read as “SR1” and “SR_2” appears that it should read as “SR2”, because the first switch and the second switch are designated “SR1” and “SR2” in FIG. 3A to FIG. 3C, FIG. 4A, FIG. 4B, and FIG. 4D and throughout the description.
Regarding FIG. 7C, “Tl” appears that it should read as “Tl-1”, because the inductor wiring of the first circuit board is designated “Tl-1” in FIG. 7F.
The drawings are objected to under 37 CFR 1.84(p)(5) because they do not include the following reference characters mentioned in the description: “Pac”, designating the AC power source received by the power supply unit PSU (see page 7, line 11); “Paux”, designating the auxiliary power supply converted by the auxiliary power circuit AUX (see page 7, line 17); “F_D1” and “F_D2”, designating the first direction magnetic flux and the second direction magnetic flux (see page 24, line 26 through page 25, line 3); and “CB”, designating a single circuit board (see page 10, line 18 and page 17, line 23).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed to, i.e. including a planar transformer disposed on a first circuit board and a second circuit board and a conductive column disposed between the first circuit board and the second circuit board.
The disclosure is objected to because of the following informalities: On page 4, in line 16, “Fig. 14D” appears that it should read as “Fig. 4D”.
On page 10, lines 15-16, FIG. 4A is described as being “according to the first embodiment of the present disclosure”, whereas the Brief Description of Drawings on page 4, lines 11-12 designates FIG. 4A as being according to a second embodiment.
On page 14, line 23, “the second through hole H1” appears that it should read as “the second through hole H2”, because of a typographical error.
On page 23, lines 22-23, “FIG. 6A to FIG. 6H” appears that it should read as “FIG. 7A to FIG. 7H”, because FIG. 6 includes only sub-figures FIG. 6A and FIG. 6B. The same informality appears on page 26, line 10.
On page 28, line 14, “between 25 degrees and 30 degrees” appears that it should read as “between 25 degrees and 35 degrees”, because FIG. 10D shows the range RS_1 as extending from 25 degrees to 35 degrees.
On page 30, line 10, “FIG. 10A” appears that it should read as “FIG. 12A”, because area A5 is shown in FIG. 12A.
On page 30, lines 23-26, the sub-diagram (a) of FIG. 12C is described as having ten relatively wider wirings and the sub-diagram (b) of FIG. 12C is described as having eighteen relatively narrower wirings, whereas FIG. 12C designates the sub-diagram (a) as “T_1~T_18” and the sub-diagram (b) as “T_1~T_10”. The same informality appears on page 31, lines 12-13.
On page 31, line 3, “T_1 to T_8” appears that it should read as “T_1 to T_18”, because of a typographical error.
On page 31, line 21, “of 16 to 18” appears that it should read as “of 16 to 20”, because FIG. 12D shows the range RS_2 as extending from 16 wirings to 20 wirings.
On page 32, line 18, “FIG. 3B” appears that it should read as “FIG. 13B”, because the perspective plan view of the wiring structure of the planar transformer is designated FIG. 13B in the Brief Description of Drawings.
On page 33, line 5, “FIG. 6A to FIG. 6B, FIG. 6G to FIG. 6H” appears that it should read as “FIG. 7A to FIG. 7B, FIG. 7G to FIG. 7H”; on page 33, lines 6-7, “FIG. 11B” appears that it should read as “FIG. 13B”; on page 33, lines 9 and 13, “FIG. 6C to FIG. 6F” appears that it should read as “FIG. 7C to FIG. 7F”; and on page 33, line 21, “FIG. 6F” appears that it should read as “FIG. 7F”.
On page 37, line 6, “Ts11-_(n)” appears that it should read as “Ts1-1_(n)”, because of a typographical error.
The reference character for the inductor wiring is used inconsistently throughout the disclosure as “T1-1” and “Tl-1” (see page 20, lines 8 and 17), and correspondingly as “T1-2” and “Tl-2”.
Appropriate correction is required.
Claim Objections
Claims 1-4, 6, 8, 9, 13, 14, and 15 are objected to because of the following informalities: Regarding claim 1, in line 7, “the secondary-side circuits” appears that it should read as “the two secondary-side circuits”, because of antecedent basis;
in line 19-20, “the winding of the first circuit board and the second circuit board” appears that it should read as “the winding of the planar transformer”, because of antecedent basis.
Regarding claim 2, in line 6, “the wirings on the same layer” appears that it should read as “the wirings on the same sub-layer board”, because of antecedent basis.
Regarding claim 3, in line 3-4, “a fourth hole” appears that it should read as “a fourth through hole”, because of antecedent basis for “the fourth through hole” recited in lines 7 and 8-9;in line 4-5, “the first core column penetrating the first through hole” appears that it should read as “the first core column penetrates the first through hole”.
Regarding claim 4, in line 3, “two secondary-side circuits” appears that it should read as “the two secondary-side circuits”, because of antecedent basis.
Regarding claim 6, in line 6-7, “two secondary-side circuits” appears that it should read as “the two secondary-side circuits”, because of antecedent basis. Regarding claim 8, in line 4, “a first terminal of the first switch and the second switch” appears that it should read as “a first terminal of the first switch and a first terminal of the second switch”, because of grammar; in line 12-13, “first switches, second switches, and output capacitors” appears that it should read as “the first switches, the second switches, and the output capacitors”, because of antecedent basis.
Regarding claim 9, in line 5-6, “the iron core further comprises a second core column penetrating the second through hole and the fourth through hole;” appears that it should be deleted, because it is a verbatim duplicate of the recitation in lines 4-5.
Regarding claim 13, in line 9, “a periphery of the main body” appears that it should read as “a periphery of the main body of the one of the two covers”, because of antecedent basis, each of the two covers comprising a main body.
Regarding claim 14, in line 5-6, “a periphery of the main body” appears that it should read as “a periphery of the respective main body”, because of antecedent basis, each of the two covers comprising a main body. Regarding claim 15, in line 1, “The resonant converter as claimed in claim 1” appears that it should read as “The resonant converter as claimed in claim 2”, because of antecedent basis for “the vias” recited in line 2, claim 1 not reciting any vias; in line 1-2, “the wirings on different layers” appears that it should read as “the wirings on different sub-layer boards”, because of antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Afsharian et al. (US Patent Application Publication US 2022/0230797 A1, hereinafter “Afsharian”).’
Regarding claim 1, the embodiment of Fig. 8 and Fig. 13 of Afsharian discloses (see Fig. 8 and Fig. 13) a resonant converter (the half-bridge DC-DC converter of Fig. 12) (see [0065] of Afsharian, “using an LLC series resonant circuit with a stacked transformer”) comprising: a first circuit board (winding PCB 1) and a second circuit board (winding PCB 2), two secondary-side circuits (the rectifier circuit of synchronous rectifiers Q3T, Q4B, Q3B, Q4T and output capacitors Co associated with Core 1; the rectifier circuit of synchronous rectifiers Q3T', Q4B', Q3B', Q4T' and output capacitors Co associated with Core 2) respectively disposed on the first circuit board and the second circuit board (see [0064] of Afsharian, “located in the top and bottom surfaces of the winding PCBs 1, 2”), and a planar transformer (stacked matrix transformer 80) disposed on the first circuit board and the second circuit board, and electrically connected to the primary-side circuit and the secondary-side circuits (see Fig. 12, transformer TX connected to switches Q1, Q2 and to the synchronous rectifiers), and the planar transformer comprising: a first circuit board through hole (one of the two holes of the first PCB) penetrating the first circuit board, a second circuit board through hole (one of the two holes of the second PCB) penetrating the second circuit board, an iron core (two-piece core 1310) comprising a first core column (one of the two legs) penetrating the first circuit board through hole and the second circuit board through hole (see [0028] of Afsharian, “extend through the two holes in the first PCB and the two holes in the second PCB”), a plurality of wirings (the turns of the primary winding on the four middle layers and the turns of the secondary winding on layer LAYER 1 and layer BOTTOM) respectively formed around the first circuit board through hole and the second circuit board through hole (see Fig. 11), and a first conductive column (power pin PIN) disposed between the first circuit board and the second circuit board, and electrically connected to a wiring arranged around the first circuit board through hole and a wiring arranged around the second circuit board through hole to form a winding (the primary winding) of the planar transformer (see [0061] of Afsharian, “electrically connected to each other by a power pin PIN located in through holes”), wherein the iron core is configured to sleeve the winding of the first circuit board and the second circuit board to form the planar transformer (see [0068] of Afsharian, “the transformer 130 can include only a two-piece core 1310”).
The embodiment of Fig. 8 and Fig. 13 does not disclose a primary-side circuit disposed on the first circuit board.
However, the embodiment of Fig. 24 of Afsharian teaches (see Fig. 24) a primary-side circuit (the components for a primary side full-bridge or half-bridge converter) disposed on the first circuit board (PCB 2410) (see [0082] of Afsharian, “components for a primary side full-bridge or half-bridge converter”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the resonant converter of the embodiment of Fig. 8 and Fig. 13 of Afsharian to include a primary-side circuit disposed on the first circuit board, as taught by the embodiment of Fig. 24 of Afsharian, because it can help achieve a compact converter structure that is simple to assemble (see [0078] of Afsharian, “resulting in a very compact design with simple assembly”).
Claims 2-4, 6, 7, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Afsharian in view of Yu et al. (R. Yu, T. Chen, P. Liu, and A. Q. Huang, “A 3-D Winding Structure for Planar Transformers and Its Applications to LLC Resonant Converters,” IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 9, no. 5, pp. 6232-6247, October 2021, hereinafter “Yu”).
Regarding claim 2, Afsharian discloses (see Fig. 8 and Fig. 11) wherein the planar transformer further comprises: a plurality of vias (embedded vias) configured to electrically connect a first sub-layer board (layer LAYER 2) and a second sub-layer board (layer LAYER 3) of the first circuit board and the second circuit board respectively (see [0064] of Afsharian, “connected in series by embedded vias”).
Afsharian does not disclose wherein the plurality of wirings interleavingly extend to the first sub-layer board and the second sub-layer board through the plurality of vias, and the wirings on the same layer are arranged in parallel.
However, Yu teaches (see Fig. 2) wherein the plurality of wirings (traces 1 to 6) interleavingly extend to the first sub-layer board (Layer 1) and the second sub-layer board (Layer 2) through the plurality of vias (the 1st Group of Vias and the 2nd Group of Vias) (see p. 6234 of Yu, “each trace does not repeat its position during vertical transposition”), and the wirings on the same layer are arranged in parallel (traces 1a and 1b arranged side by side on Layer 1 in Fig. 2(c)) (see p. 6234 of Yu, “the interleaved one-turn windings must be in parallel”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the planar transformer of Afsharian to include wherein the plurality of wirings interleavingly extend to the first sub-layer board and the second sub-layer board through the plurality of vias, and the wirings on the same layer are arranged in parallel, as taught by Yu, because it can help balance the current among the parallel wirings and reduce the ac resistance of the winding (see p. 6242 of Yu, “current balancing in planar-Litz can effectively reduce the ac resistance”).
Regarding claim 3, Afsharian discloses (see Fig. 11 and Fig. 13) wherein the first circuit board through hole comprises a first through hole and a second through hole penetrating the first circuit board (the two holes of the first PCB); wherein the second circuit board through hole comprises a third through hole and a fourth hole penetrating the second circuit board (the two holes of the second PCB), and the first core column penetrating the first through hole and the third through hole (one of the two legs), wherein the iron core further comprises a second core column (the other of the two legs) penetrating the second through hole and the fourth through hole (see [0028] of Afsharian, “two legs that connect the first core and the second core”), and the plurality of wirings are respectively formed around the first through hole, the second through hole, the third through hole, and the fourth through hole (see Fig. 11, the turns of layer LAYER 1 to layer LAYER 5 and layer BOTTOM formed around each of the two openings of each winding PCB).
Regarding claim 4, Afsharian discloses (see Fig. 8 and Fig. 11) wherein the plurality of wirings are a plurality of secondary-side wirings (the turns of the secondary winding on layer LAYER 1 and layer BOTTOM of winding PCB 1 and of winding PCB 2), and used as two secondary-side windings electrically connected to two secondary-side circuits (see [0063] of Afsharian, “top and bottom layers including the secondary winding, the SRs, and the filter capacitors”), and the planar transformer further comprises: two primary-side wirings (the one turn of the primary winding on layer LAYER 3 of winding PCB 1 and the one turn of the primary winding on layer LAYER 3 of winding PCB 2) respectively formed on a third sub-layer board (layer LAYER 3) of the first circuit board and the second circuit board, and a second conductive column (power pin PIN) disposed between the first circuit board and the second circuit board, and electrically connected to the two primary-side wirings to form a primary-side winding of the planar transformer (see [0064] of Afsharian, “are also connected in series by power pin PIN”).
Examiner's Note: For the purpose of the rejection of claim 4 only, the first conductive column of claim 1 is read on the +12 V bus bar and the return bus bar RTN of Afsharian, which electrically connect the secondary windings of winding PCB 1 and of winding PCB 2 (see [0064] of Afsharian), and the second conductive column is read on the power pin PIN. In the rejection of claim 1 above and in the rejections of the remaining claims, the first conductive column is read on the power pin PIN. Also for the purpose of the rejection of claim 4 only, the first sub-layer board and the second sub-layer board of claim 2 are read on layer LAYER 1 and layer BOTTOM of each winding PCB.
Regarding claim 6, Afsharian discloses (see Fig. 8 and Fig. 11) wherein the plurality of wirings are a plurality of primary-side wirings (the turns of the primary winding on the four middle layers of winding PCB 1 and of winding PCB 2), and electrically connected through the first conductive column and used as a primary-side winding electrically connected to the primary-side circuit (see [0064] of Afsharian, “are also connected in series by power pin PIN”), and the planar transformer further comprises: two secondary-side wirings (the turns of the secondary winding on layer LAYER 1 and layer BOTTOM of winding PCB 1 and of winding PCB 2) respectively formed on the first circuit board and the second circuit board, and used as two secondary-side windings electrically connected to two secondary-side circuits (see [0064] of Afsharian, “The secondary windings and the SRs are connected in parallel”).
Regarding claim 7, Afsharian does not disclose wherein the plurality of wirings are formed in a wiring area of the first circuit board and the second circuit board, and the plurality of vias are formed at a periphery of the wiring area, a periphery of the first circuit board through hole, and a periphery of the second circuit board through hole.
However, Yu teaches (see Fig. 2) wherein the plurality of wirings (traces 1 to 6) are formed in a wiring area (the region of each of Layer 1 to Layer 6 occupied by the traces) of a circuit board (the six-layer PCB of Fig. 2(c)), and the plurality of vias (the via pads of the 1st Group of Vias and of the 2nd Group of Vias) are formed at a periphery of the wiring area and at a periphery of a circuit board through hole (the core-leg opening at the center of each of Layer 1 to Layer 6) (see p. 6234 of Yu, “the minimal number of PCB vias can be achieved”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the planar transformer of Afsharian to include wherein the plurality of wirings are formed in a wiring area of the first circuit board and the second circuit board, and the plurality of vias are formed at a periphery of the wiring area, a periphery of the first circuit board through hole, and a periphery of the second circuit board through hole, as taught by Yu, because it can help minimize the number of vias in the winding and thereby reduce the high-frequency loss caused by the vias (see p. 6234 of Yu, “due to the high-frequency loss of PCB vias”).
Regarding claim 14, the embodiment of Fig. 8 and Fig. 13 of Afsharian discloses (see Fig. 8 and Fig. 13) wherein the iron core further comprises: two covers (the split top and bottom U-shaped core U CORE), and each cover comprising a main body (the plate portion of each U-shaped core) and a plurality of side portions (the legs of each U-shaped core), wherein the side portions of the two covers are correspondingly protruded at a periphery of the main body (see Fig. 13, the legs of the upper piece and of the lower piece of the two-piece core 1310 protruding toward each other) (see [0061] of Afsharian, “stacked between a split top and bottom U-shaped core U CORE”).
The embodiment of Fig. 8 and Fig. 13 of Afsharian does not disclose one of the two covers forming the first core column.
However, the embodiment of Fig. 22 of Afsharian teaches (see Fig. 22) one of the two covers (second plate 2230) forming the first core column (the legs extending from the second plate 2230 through the through holes 2270 of the PCB 2210) (see [0078] of Afsharian, “FIG. 22 shows that the legs extend from the second plate 2230”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the iron core of the embodiment of Fig. 8 and Fig. 13 of Afsharian so that one of the two covers forms the first core column, as taught by the embodiment of Fig. 22 of Afsharian, because it can help reduce the number of core pieces and thereby shrink the size and footprint of the transformer (see [0017] of Afsharian, “A reduced number of cores to shrink the size and footprint of the transformer”).
The embodiment of Fig. 8 and Fig. 13 of Afsharian does not disclose wherein one of the side portions located at an outer side of the first circuit board and the second circuit board forms an air gap.
However, Yu teaches (see Fig. 3) wherein one of the side portions (the outer leg of the ferrite core) located at an outer side of the circuit board forms an air gap (the air gap between the upper core part and the lower core part at the outer leg) (see p. 6240 of Yu, “0.1-mm gaps in the two sides and center of the Ferrite core”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the iron core of the embodiment of Fig. 8 and Fig. 13 of Afsharian so that one of the side portions located at an outer side of the first circuit board and the second circuit board forms an air gap, as taught by Yu, because it can help lower the magnetizing inductance of the planar transformer (see p. 6235 of Yu, “since gaps are added, the magnetizing inductance will be much lower”).
Allowable Subject Matter
Claims 5, 8-13, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 5, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “two third vias respectively formed on the first side, and the two third vias configured to electrically connect the first sub-layer board and the fourth sub-layer board, and two fourth vias respectively formed on the second side, and the two fourth vias configured to electrically connect the second sub-layer board and the fifth sub-layer board”. The closest prior art, Yu, discloses parallel traces that are transposed among six printed circuit board layers through two groups of vias (see Fig. 2(a) of Yu), but Yu does not form separate first, second, third and fourth pairs of vias on two opposite sides of a through hole and therefore fails to disclose or teach the above limitation.
Regarding claim 8, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “the first direction and the second direction are in opposite directions along the first through hole, and the first direction and the second direction are in opposite directions along the third through hole”. The closest prior art, Yu, discloses that the secondary one-turn traces are paralleled by the transposition structure (see p. 6242 of Yu), but Yu does not route a first secondary-side wiring and a second secondary-side wiring in opposite directions around a through hole to respective pairs of vias and therefore fails to disclose or teach the above limitation. Claims 9-12 are objected to due to their dependency on claim 8.
Regarding claim 13, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “an inductor iron core comprising two covers, each cover comprising a main body, and one of the two covers comprising two side portions” and “one of the two side portions penetrates through the first inductor through hole and the second inductor through hole”. The closest prior art, Afsharian, discloses a two-piece core having legs that extend through holes in a first printed circuit board and in a second printed circuit board (see [0028] of Afsharian), but Afsharian does not disclose a separate inductor iron core having a side portion that penetrates an inductor through hole of each of the two circuit boards and therefore fails to disclose or teach the above limitation.
Regarding claim 15, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “the wirings on different layers form an acute angle with the vias as the center, and the acute angle is between 25 degrees and 35 degrees”. The closest prior art, Yu, discloses parallel traces that are transposed among printed circuit board layers through vias (see Fig. 2(a) of Yu), but Yu does not specify any angle formed between the wirings on different layers and therefore fails to disclose or teach the above limitation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 6,307,458 B1 discloses an inductor core having first, second and third legs inserted through corresponding openings that extend through the layers of a printed circuit board assembly, with a split inductor winding integrated into the printed circuit board layers.
US 2018/0342953 A1 discloses a planar transformer having a first core and a second core that are spaced apart to form a gap between the middle foots and a gap between the outer foots, with inductor winding parts wound around the outer foots of the first core to provide the resonance inductor of an LLC resonant converter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
Prosecution Insights