Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-11 and 14 is/are rejected under 35 U.S.C. 102(a)(1)as being anticip
ated by Cho et al (PGPUB 2021/0225282 A1).
As to claim 1, Cho (Figs. 2, 3) teaches, a display panel (display device, Fig. 1, ¶ 62), comprising:
a light emitting element (organic light emitting diode OLED)(¶ 63);
a driving transistor (driving transistor TR1) configured to provide a driving current (current) to the light emitting element based on a driving voltage (first power voltage ELVDD)(¶ 77, 78);
a second switching transistor (second transistor TR2) connecting the driving transistor and a data line (data line DL\m)(¶ 66);
a third switching transistor (fifth transistor TR5) connecting the driving transistor and a driving voltage line (i.e. line for ELVDD)(¶ 70);
a fourth switching transistor (sixth transistor TR6) connecting the driving transistor and the light emitting element (i.e. connects to node N3 and N4)(¶ 71);
a fifth switching transistor (eighth transistor TR8) connecting the driving transistor (i.e. via node N2) and a bias voltage line (reference voltage VEH)(¶ 73);
wherein the driving transistor is configured to receive a bias voltage (VEH) during
a first period (reset period P1)(¶ 93, Fig. 3), and the driving voltage during a second period (i.e. period P4 via TR5 being turned on rom EM in low state) different from the first period (i.e. P4 is after reset period P1 as shown in Fig. 3), and
wherein the bias voltage is greater than the driving voltage (¶ 58: i.e. reference VEH may be higher level voltage than the first power voltage ELVDD).
As to claim 5, Cho (Fig. 2) teaches, a first switching transistor (third transistor TR3) connecting a gate electrode (i.e. gate of TR1 via node N1) of the driving transistor and the fourth switching transistor (i.e. upper terminal of TR6 via node N3)(Fig. 2); and
a sixth switching transistor (seventh transistor TR7) connecting the light emitting element (i.e. via node N4) and a reset voltage line (second initialization voltage Vint2)(¶ 72, Fig. 2).
As to claim 6, Cho (Fig. 2) teaches, wherein the second switching transistor having a gate electrode (i.e. gate of TR2) to which a second scan signal (first input signal GW[n]) is applied (¶ 81), a drain electrode (i.e. left terminal as shown in Fig. 2) to which a data voltage (data voltage Vdat) is applied (¶ 66, 85), and a source electrode (i.e. right terminal of TR2) connected to a drain electrode (i.e. upper terminal of TR1) of the driving transistor (Fig. 2).
As to claim 7, Cho (Fig. 2) teaches, wherein the third switching transistor having a gate electrode (i.e. gate of TR5) to which a first emission signal (light emission signal EM[n]) is applied (¶ 70), a drain electrode (i.e. upper terminal of TR5 as shown in Fig. 2) to which the driving voltage is applied, and a source electrode (i.e. lower terminal) connected to the drain electrode of the driving transistor (Fig. 2).
As to claim 8, Cho (Fig. 2) teaches, wherein the fourth switching transistor having a gate electrode (i.e. gate of TR6) to which a second emission signal (light emission signal EM[n]) is applied, a drain electrode (i.e. upper terminal of TR6 as shown in Fig. 2) connected to a source electrode (i.e. lower terminal of TR1) of the driving transistor, and a source electrode (i.e. lower terminal of TR6) connected to the light emitting element (Fig. 2).
As to claim 9, Cho (Fig. 2) teaches, wherein the fifth switching transistor having a gate electrode (i.e. gate of TR8) to which a third scan signal (fourth gate signal GB[n])is applied, a drain electrode (i.e. right terminal as shown in Fig. 2) to which the bias voltage is supplied (¶ 73, Fig. 2).
As to claim 10, Cho (Fig. 2) teaches, wherein the first switching transistor having a gate electrode (i.e. gate of TR3) to which a first scan signal (third gate signal GC[n]) is applied, a drain electrode (i.e. left terminal of TR3 as shown in Fig. 2) connected to a gate electrode (i.e. gate of TR1) of the driving transistor, and a source electrode (i.e. right terminal of TR3) connected to a source electrode (i.e. lower terminal of TR1) of the driving transistor (Fig. 2).
As to claim 11, Cho (Fig. 2) teaches, wherein the sixth switching transistor having a gate electrode (i.e. gate of TR7) to which a fourth scan signal (first gate signal GB[n]) is applied, a drain electrode (i.e. left terminal as shown in Fig. 2) to which a reset voltage second initialization voltage Vint2) is supplied, and a source electrode (i.e. right terminal) connected to the light emitting element (¶ 72, Fig. 2).
As to claim 14, Cho (Figs. 2, 3) teaches, a display device (display device, Fig. 1, ¶ 62), comprising:
a display panel (display device, Fig. 1, ¶ 62) including:
a light emitting element (organic light emitting diode OLED)(¶ 63);
a driving transistor (driving transistor TR1) configured to provide a driving current (current) to the light emitting element based on a driving voltage (first power voltage ELVDD)(¶ 77, 78);
a plurality of emission signal lines (emission control lines EL1 – ELn)(¶ 54);
an emission driving circuit (light emission control driver 400) configured to supply a plurality of emission signals (light emission control signal CONT3) to the display panel through the plurality of emission signal lines (¶ 57); and
wherein the driving transistor is configured to receive a bias voltage (reference voltage VEH) during a first period (reset period P1)(¶ 93, Fig. 3), and the driving voltage during a second period (i.e. period P4) different from the first period (i.e. P4 is after reset period P1 as shown in Fig. 3), and
wherein the bias voltage is greater than the driving voltage (¶ 58: i.e. reference VEH may be higher level voltage than the first power voltage ELVDD).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Park et al (PGPUB 2021/0256908 A1).
As to claim 2, Cho teaches the display device of claim 1, but does not teach a third period after the second period.
Park (Figs. 2, 3) teaches, wherein, the light emitting element is configured to emit light during a third period (fifth period P5) after the second period (third period P3, which supplies driving voltage VDD to T1)(¶ 91, 101, Fig. 3).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Park’s display pixel structure and driving method into Cho’s display, so as to improve image quality by compensating the threshold voltage of the driving transistor (¶ 29).
As to claim 3, Cho teaches the display device of claim 2, but does not specifically teach the second period is a time section in which the third switching transistor is turned on during a state in which the fourth switching transistor is turned off.
Park (Fig. 3) teaches, the second period is a time section (time period P3) in which the third switching transistor (fifth transistor T5) is turned on during a state in which the fourth switching transistor (sixth transistor T6) is turned off (i.e. during P3, EL[i] is low to turn on T5 and EL[i-k] is high to turn off T6).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Park’s display pixel structure and driving method into Cho’s display, so as to improve image quality by compensating the threshold voltage of the driving transistor (¶ 29).
As to claim 4, Cho teaches the display panel of claim 2, but does not specifically teach the third period.
Park (Figs. 2, 3) teaches, the third period is a time section in which the fourth switching transistor (T6) is turned on during a state in which the third switching transistor (T5) is turned on (Fig. 3: i.e. T5 and T6 are both turned on during P5).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Park’s display pixel structure and driving method into Cho’s display, so as to improve image quality by compensating the threshold voltage of the driving transistor (¶ 29).
As to claim 15, Cho teaches the display device of claim 14, but does not teach a third period after the second period.
Park (Figs. 2, 3) teaches, wherein, the light emitting element emits light during a third period (fifth period P5) after the second period (third period P3, which supplies driving voltage VDD to T1)(¶ 91, 101, Fig. 3).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Park’s display pixel structure and driving method into Cho’s display, so as to improve image quality by compensating the threshold voltage of the driving transistor (¶ 29).
Claim(s) 12, 13, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Na (PGPUB 2021/0366397 A1).
As to claims 12 and 16, Cho teaches the display panel of claim 1 but does not specifically teach low speed mode.
Na (Fig. 2) teaches, wherein the display panel is operated in a low speed
mode (i.e. any driving frequencies lower than the maximum frequency of 240Hz. The lower frequencies include 120Hz, 80Hz, 60Hz, 48Hz) operating at a low driving frequency (¶ 55).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Na’s pixel structure and driving mode into Cho’s display device, so as to reduce flicker (¶ 65, 78).
As to claims 13 and 17, The display panel of claim 1, in a mode in which the display panel is operated at a low driving frequency (120Hz, 80hz, 60Hz and 48Hz), wherein the mode includes:
a refresh frame period (display scan) in which a data voltage (data signal) for driving the light emitting element is applied (Fig. 3: i.e. during sdisplay scan data signal is applied)(¶ 54); and
a skip frame period (self scan) in which the data voltage is not applied (Fig. 3: i.e. no data signal is applied during self scan period)(¶ 54).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Na’s pixel structure and driving mode into Cho’s display device, so as to reduce flicker (¶ 65, 78).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623