Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 10 and 12-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cooper(US 2021/0208663).
Regarding claim 1, Cooper discloses a method of controlling power consumption of a processor in a processing system, comprising: monitoring performance data of the processing system(Paragraphs 26-27 , current utilization of the processing unit is determined from the architectural counters or otherwise. At block 412 filtering of the current utilization values may be performed by averaging over different sampling periods to improve accuracy. A number of different performance parameters may be used to monitor performance of a processing unit) and system information of the processing system(Paragraphs 21, The sensors 112,123 may provide measurements of, for example, battery charge levels, battery current values, adapter current values, temperature, operating voltage, operating current, operating power, inter-core communication activity, operating frequency or any other parameter relevant to power or thermal management of the processing platform 100), determining a utilization scaling based on a current state associated with the system information and based on the performance data of the processing system; and applying the utilization scaling to control a frequency of the processor in the processing system(Paragraphs 108-110, use of one or more observables such as a currently observed utilization and a current scalability determined using architectural counters and to use a scalability function such as the one specified by equation 3 above to determine which new frequency is most likely to result in achieving the desired new target quantified power expenditure given knowledge of the current utilization. In a parameter space representing an operating point of a processing unit, the parameters of frequency utilization and power are all relevant. The new frequency is what is to be selected and the new power expenditure is a target value driving the particular new frequency selection for power-aware governance distributed amongst multiple PUs. The utilization and frequency are inherently linked, but the scalability is a further factor that may be taken into account to improve control over the power expenditure resulting from the frequency change that is implemented. The use of a power profile, a target power expenditure and a scalability measurement and scalability function allow the power expenditure of the processing unit to be more predictable in the frequency updating process according to the present technique. Once the new operating frequency has been selected at element 550, the process proceeds to element 560 where control is exercised to implement the selected new frequency).
Regarding claim 2, Cooper discloses the method of claim 1, wherein determining the current state is a transient state based on the system information; wherein the transient state comprises an abrupt increase in a Million Cycles Per Second (MCPS) and/or a Million Instructions Per Second (MIPS) of the processing system; and boosting the utilization scaling(Paragraphs 75-85, Check PU utilization (architectural counters); The averaging allows coarse and fine granularity of workloads to be observed to distinguish between more and less “bursty” workloads for example. The alpha window may provide a trend in utilization whereas the tau window allows spikes(This is considered an increase MIPS/MCPS) in utilization to be observed. Compute system utilization (across all PU cores), which may be achieved via a priori mathematical derivation based on individual CPU utilization, just as with scaled power. The utilization for each thread may be measured using the architectural performance counters such as APERF and MPERF. The utilization may be calculated using a sum of utilizations of a plurality of cores, such as by calculating a weighted average across a plurality of cores. Check current scalability Sc [ Using the above described scaled power and system utilization, estimate the scaled utilization and resultant power. If current scalability S.sub.C is above a certain (programmable) threshold, then a higher frequency choice is more likely to be selected from range of target frequencies available If current scalability S.sub.C is below the threshold, the algorithm may be more conservative in allowing higher frequency selections because the extra power expenditure associated with the higher frequency is less likely to result in and increase in useful work due to the higher proportion of stalls characterizing the workload. For a given scaled power and system utilization, select an optimal (or at least best known) frequency).
Regarding claim 3, Cooper discloses the method of claim 1, wherein determining the utilization scaling comprises: determining the current state is not a transient state based on the system information, wherein the transient state comprises an abrupt increase in a MCPS and/or a MIPS of the processing system; and preprocessing the performance data(Paragraphs 75-85, Check PU utilization (architectural counters); The averaging allows coarse and fine granularity of workloads to be observed to distinguish between more and less “bursty” workloads for example. The alpha window may provide a trend in utilization whereas the tau window allows spikes(This is considered an increase MIPS/MCPS) in utilization to be observed. Compute system utilization (across all PU cores), which may be achieved via a priori mathematical derivation based on individual CPU utilization, just as with scaled power. The utilization for each thread may be measured using the architectural performance counters such as APERF and MPERF. The utilization may be calculated using a sum of utilizations of a plurality of cores, such as by calculating a weighted average across a plurality of cores. Check current scalability Sc [ Using the above described scaled power and system utilization, estimate the scaled utilization and resultant power. If current scalability S.sub.C is above a certain (programmable) threshold, then a higher frequency choice is more likely to be selected from range of target frequencies available If current scalability S.sub.C is below the threshold, the algorithm may be more conservative in allowing higher frequency selections because the extra power expenditure associated with the higher frequency is less likely to result in and increase in useful work due to the higher proportion of stalls characterizing the workload. For a given scaled power and system utilization, select an optimal (or at least best known) frequency).
Regarding claim 4, Cooper discloses the method of claim 3, wherein determining the utilization scaling further comprises: if the preprocessed performance data falls below a predetermined threshold, increasing the utilization scaling(Paragraphs 75-85, Check PU utilization (architectural counters); The averaging allows coarse and fine granularity of workloads to be observed to distinguish between more and less “bursty” workloads for example. The alpha window may provide a trend in utilization whereas the tau window allows spikes(This is considered an increase MIPS/MCPS) in utilization to be observed. Compute system utilization (across all PU cores), which may be achieved via a priori mathematical derivation based on individual CPU utilization, just as with scaled power. The utilization for each thread may be measured using the architectural performance counters such as APERF and MPERF. The utilization may be calculated using a sum of utilizations of a plurality of cores, such as by calculating a weighted average across a plurality of cores. Check current scalability Sc [ Using the above described scaled power and system utilization, estimate the scaled utilization and resultant power. If current scalability S.sub.C is above a certain (programmable) threshold, then a higher frequency choice is more likely to be selected from range of target frequencies available If current scalability S.sub.C is below the threshold, the algorithm may be more conservative in allowing higher frequency selections because the extra power expenditure associated with the higher frequency is less likely to result in and increase in useful work due to the higher proportion of stalls characterizing the workload. For a given scaled power and system utilization, select an optimal (or at least best known) frequency).
Regarding claim 5, Cooper discloses the method of claim 3, wherein determining the utilization scaling comprises: if the preprocessed performance data exceeds a predetermined threshold, decreasing the utilization scaling(Paragraphs 75-85, Check PU utilization (architectural counters); The averaging allows coarse and fine granularity of workloads to be observed to distinguish between more and less “bursty” workloads for example. The alpha window may provide a trend in utilization whereas the tau window allows spikes(This is considered an increase MIPS/MCPS) in utilization to be observed. Compute system utilization (across all PU cores), which may be achieved via a priori mathematical derivation based on individual CPU utilization, just as with scaled power. The utilization for each thread may be measured using the architectural performance counters such as APERF and MPERF. The utilization may be calculated using a sum of utilizations of a plurality of cores, such as by calculating a weighted average across a plurality of cores. Check current scalability Sc [ Using the above described scaled power and system utilization, estimate the scaled utilization and resultant power. If current scalability S.sub.C is above a certain (programmable) threshold, then a higher frequency choice is more likely to be selected from range of target frequencies available If current scalability S.sub.C is below the threshold, the algorithm may be more conservative in allowing higher frequency selections because the extra power expenditure associated with the higher frequency is less likely to result in and increase in useful work due to the higher proportion of stalls characterizing the workload. For a given scaled power and system utilization, select an optimal (or at least best known) frequency).
Regarding claim 10, Cooper discloses the method of claim 1, wherein the system information comprises at least one of: an idle time of the processor, a MCPS of the processor and a MIPS of the processor(Paragraph 52, the utilization does take into account the scalability and the effect or stalls in processing. This can be understood by considering that utilization is “work” done, which means, that the CPU was in an active state doing some “work”, rather than in an idle or a sleep state or another low power state, for example).
Claims 12-16 recite similar limitations as claims 1-5 and thus taught by Cooper as explained above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-8, 11 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts and Cooper and Muckle (US 2016/0026507).
Regarding claim 6, Cooper does not specifically disclose tracking per-entity load for each task of a plurality of tasks in a queue of the processor; and determine a utilization value for the each task according to the per-entity load of each task. However, Muckle discloses the per-task processor demand information (also referred to as CPU demand) includes information about the demand exerted by a task, and this information may be used to place the task on one of the processors 116. This information may be provided by a per-entity load tracking (PELT) scheme present in LINUX kernel. Alternatively, a window-based load tracking scheme may be utilized to obtain information about the processor demand exerted by tasks(Paragraph 27). Thus, it would have been obvious to one of ordinary skill in the art and before the effective filing date to combine the teachings of Cooper and Muckle to track per-entity load for each task of a plurality of tasks in a queue of the processor; and determine a utilization value for the each task according to the per-entity load of each task. The motivation to do so would to be have more accurate information.
Regarding claim 7, Cooper and Muckle discloses the method of claim 6, wherein applying the utilization scaling further comprises: summing the utilization value for the each task of the plurality of tasks to obtain a total utilization value; and multiplying the total utilization value by the utilization scaling to obtain a scaled utilization value, wherein the frequency of the processor is controlled based on the scaled utilization value(Muckle: Paragraph 27, per-task processor demand information (also referred to as CPU demand) includes information about the demand exerted by a task, and this information may be used to place the task on one of the processors 116. This information may be provided by a per-entity load tracking (PELT) scheme present in LINUX kernel. Alternatively, a window-based load tracking scheme may be utilized to obtain information about the processor demand exerted by tasks(Paragraph 27).
Regarding claim 8, Cooper does not specifically disclose applying the utilization scaling comprises: tracking CPU utilization within a predetermined time window for a plurality of tasks in a queue of the processor; and determining an aggregate utilization value for the predetermined time window according to a total CPU utilization of the plurality of tasks within the predetermined time window. However, Muckle discloses the per-task processor demand information (also referred to as CPU demand) includes information about the demand exerted by a task, and this information may be used to place the task on one of the processors 116. This information may be provided by a per-entity load tracking (PELT) scheme present in LINUX kernel. Alternatively, a window-based load tracking scheme may be utilized to obtain information about the processor demand exerted by tasks(Paragraph 27). Thus, it would have been obvious to one of ordinary skill in the art and before the effective filing date to combine the teachings of Cooper and Muckle to apply the utilization scaling comprises: tracking CPU utilization within a predetermined time window for a plurality of tasks in a queue of the processor; and determining an aggregate utilization value for the predetermined time window according to a total CPU utilization of the plurality of tasks within the predetermined time window. The motivation to do so would to be have more accurate information.
Regarding claim 11, Cooper does not specifically disclose processing system comprises a Linux based processing system or Energy Aware Scheduling (EAS). Muckle disclose using linux(Paragraph 25). Thus, it would have been obvious to one of ordinary skill in the art and before the effective filing date to combine the teachings of Cooper and Muckle to have a Linux based processing system or Energy Aware Scheduling (EAS). The motivation to do so increase application flexibility.
Claims 17-19 recite similar limitations as claims 6-8 and thus taught by Cooper as explained above.
Claims 9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts and Cooper and Lee(US 2016/0328882).
Regarding claims 9 and 20 Cooper does not specifically disclose the performance data comprise at least one of: a latency between an image sensor capture and a display output; and a jitter across a plurality of concurrent threads associated with the processor. However, Lee discloses significant latency between image capture and image display that often is perceptible to a user(Paragraph 16). Thus, it would have been obvious to one of ordinary skill in the art and before the effective filing date to combine the teachings of Cooper and Lee to have the performance data comprise at least one of: a latency between an image sensor capture and a display output; and a jitter across a plurality of concurrent threads associated with the processor. The motivation to do so would be to factor the latency between an image sensor capture and a display output for accurate selection.
Conclusion
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/NIMESH G PATEL/ Primary Examiner, Art Unit 2185
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