Prosecution Insights
Last updated: October 02, 2026
Application No. 19/078,333

Analog-to-digital conversion circuit and time-interleaved analog-to-digital conversion circuit

Non-Final OA §102
Filed
Mar 13, 2025
Priority
Mar 22, 2024 — TW 113110909
Examiner
JEAN PIERRE, PEGUY
Art Unit
Tech Center
Assignee
Realtek Semiconductor Corporation
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
990 granted / 1050 resolved
+34.3% vs TC avg
Minimal -1% lift
Without
With
+-0.8%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
16 currently pending
Career history
1058
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
40.5%
+0.5% vs TC avg
§102
37.9%
-2.1% vs TC avg
§112
10.1%
-29.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1050 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 3/13/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weng et al. (US 10,965,300). With regard to claim 1 Weng discloses: An analog-to-digital conversion circuit configured to convert an input signal into a digital signal, comprising: a buffer circuit (1100 Fig. 1) configured to receive the input signal (input Fig. 1) and generate an intermediate voltage; a switch (1200 Fig. 1) coupled to the buffer circuit and configured to sample the intermediate voltage according to an operating clock (CLK5 Fig. 1) to generate a voltage (Vin Fig. 1) ;an analog-to-digital converter (ADC) (1300 Fig. 1) coupled to the switch and configured to convert the voltage into the digital signal according to the operating clock and generate an indication signal; and a control circuit (1500 Fig. 1) coupled to the switch and the ADC and configured to adjust a duty cycle of the operating clock (adjust duty cycle for each bit: Figs. 2 and 4; col. 5 lines 54-60) according to the indication signal and a reference clock; wherein the indication signal indicates that the ADC has completed an analog-to-digital conversion operation (col. 7, lines 32-38). Allowable Subject Matter Claims 2-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 14-19 are allowed. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kurahashi et al. (US 20190081635), Kull et al. (US 9,614,540), Schuber (US 20130335049) disclose analog to digital converter that improve performance in converting the analog signal to accurate digital signal. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105. /PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Mar 13, 2025
Application Filed
Sep 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12750065
SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
1y 9m to grant Granted Sep 29, 2026
Patent 12738951
INTEGRATED CIRCUIT COMPRISING A DIGITAL-TO-ANALOG CONVERTER
2y 9m to grant Granted Sep 15, 2026
Patent 12736991
Controller for an electronically controlled resistor
2y 10m to grant Granted Sep 15, 2026
Patent 12738958
ENCODING METHOD, DECODING METHOD, APPARATUS, DEVICE, SYSTEM, AND READABLE STORAGE MEDIUM
2y 2m to grant Granted Sep 15, 2026
Patent 12732765
SYSTEM AND METHOD FOR DETECTING ANALOG SIGNALS ON AN AMPLIFIER INPUT AND GATING THE SAME
3y 9m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
94%
With Interview (-0.8%)
1y 8m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1050 resolved cases by this examiner. Grant probability derived from career allowance rate.

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