Prosecution Insights
Last updated: October 23, 2026
Application No. 19/078,538

MULTILAYER ELECTRONIC COMPONENT

Non-Final OA §103
Filed
Mar 13, 2025
Priority
May 10, 2024 — RE 10-2024-0062080
Examiner
RAMASWAMY, ARUN
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
694 granted / 818 resolved
+16.8% vs TC avg
Moderate +12% lift
Without
With
+12.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
34 currently pending
Career history
867
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
59.7%
+19.7% vs TC avg
§102
29.7%
-10.3% vs TC avg
§112
5.9%
-34.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 818 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 14 is objected to because of the following informalities: “NEW CLAIMS” precedes Claim 14. All claims require a proper status identifier. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 5-10, and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Publication 2014/0301013) in view of Noda et al. (US Publication 2017/0076870). In re claim 1, Kim discloses a multilayer electronic component comprising: a multilayer portion (110 – Figure 1, ¶39) including a dielectric layer (112 – Figure 4, ¶49), an internal electrode (121, 122 – Figure 4, ¶39) disposed alternately with the dielectric layer in a first direction (Figure 1), first and second surfaces (5, 6 – Figure 1), opposing each other in the first direction (‘T’ direction – Figure 1), third and fourth surfaces (3, 4 – Figure 1, ¶40) opposing each other in a second direction (‘L’ direction – Figure 1), perpendicular to the first direction, the third and the fourth surfaces connected to at least a portion of the internal electrode (121, 122 – Figure 4), and fifth and sixth surfaces (left and right surfaces of 111 – Figure 2, ¶49) opposing each other in a third direction (‘W’ direction – Figure 1, Figure 2), perpendicular to the first and the second directions (Figure 1, Figure 2); margin portions (113, 114 – Figure 2, ¶49) that are disposed on the fifth and sixth surfaces (Figure 2), wherein the dielectric layer (112 – Figure 4) includes a first dielectric grain (Ga – Figure 3, ¶79), and the margin portions include a second dielectric grain (Gw – Figure 3, ¶79), and an average size of the second dielectric grain is less than an average size of the first dielectric grain (¶79). Kim does not disclose a protective portion disposed on the third and the fourth surfaces; and an external electrode disposed on the multilayer portion and the protective portion, the external electrode connected to the internal electrode, wherein the dielectric layer includes a first dielectric grain, and the protective portion includes a second dielectric grain, and an average size of the second dielectric grain is less than an average size of the first dielectric grain. Noda discloses a protective portion made of ceramic (¶84) that is an extension (16a – Figure 2B, ¶74) from a margin portion (16 – Figure 2B, ¶74) that is disposed on the third and the fourth surfaces (surfaces of 2 facing in the ‘Y’ direction – Figure 1, Figure 2B, ¶55); and an external electrode (6, 8 -Figure 1, Figure 2B, ¶55) disposed on the multilayer portion and the protective portion (Figure 2B), the external electrode connected to the internal electrode (12 – Figure 1, ¶66). The combination of Kim and Noda discloses wherein the dielectric layer includes a first dielectric grain, and the protective portion includes a second dielectric grain, and an average size of the second dielectric grain is less than an average size of the first dielectric grain. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the protective portion of Noda to improve the moisture reliability of the electronic component (¶87: Noda). In re claim 5, Kim in view of Noda discloses the multilayer electronic component of claim 1, as explained above. Kim further discloses wherein a ratio of an average size of the second dielectric grain (Gw – Figure 3) to an average size of the first dielectric grain (Ga – Figure 3) is between 0.10 and 0.8, inclusive (Table 2: Sample 8). In re claim 6, Kim in view of Noda discloses the multilayer electronic component of claim 1, as explained above. Kim does not disclose wherein a ratio of a maximum size of the protective portion in the second direction to a maximum size of the external electrode in the second direction is between 0.18 and 1.00. Noda discloses that adjusting the maximum size of the protection portion is a balance between plating material infiltration and proper electrical connection (¶101-103). It would have been obvious to one having ordinary skill in the art at the time the invention was made to adjust the dimensions of the protective portion to achieve a device having a desired balance between moisture and plating infiltration and variation of electrostatic capacity, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). In re claim 7, Kim in view of Noda discloses the multilayer electronic component of claim 1, as explained above. Kim does not disclose wherein a ratio of a maximum size of the protective portion in the second direction to a maximum size of the external electrode in the second direction is between 0.25 and 0.75, inclusive. Noda discloses that adjusting the maximum size of the protection portion is a balance between plating material infiltration and proper electrical connection (¶101-103). It would have been obvious to one having ordinary skill in the art at the time the invention was made to adjust the dimensions of the protective portion to achieve a device having a desired balance between moisture and plating infiltration and variation of electrostatic capacity, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). In re claim 8, Kim in view of Noda discloses the multilayer electronic component of claim 1, as explained above. Kim further discloses wherein both ends of the internal electrode (121, 122 – Figure 4, Figure 5) in the third direction (‘W’ direction – Figure 1, Figure 2, Figure 3, Figure 5) are disposed to be spaced apart from the fifth surface and the sixth surface (Figure 5; Note that the Examiner is taking the outer ends of the margin portions to be the fifth and sixth surfaces.). In re claim 9, Kim in view of Noda discloses the multilayer electronic component of claim 1, as explained above. Kim further discloses wherein the internal electrode (121, 122 – Figure 4) has a rectangular shape in a cross-section of the multilayer portion in the second and the third directions (Figure 5). In re claim 10, Kim in view of Noda discloses the multilayer electronic component of claim 1, as explained above. Kim does not disclose wherein a size of the internal electrode in the third direction is substantially equal to its size in the second direction. However, it is well-known in the art that adjusting the dimensions of the internal electrodes and overlap area of the internal electrodes is directly correlated to overall capacitance. It would have been an obvious matter of design choice to adjust the dimensions of the internal electrode in the second and third direction to be equal to achieve a device having desired capacitance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). In re claim 12, Kim in view of Noda discloses the multilayer electronic component of claim 1, as explained above. Kim further discloses wherein the multilayer portion includes a capacitance formation portion (portion of 110 where 121, 122, 112 exist – Figure 2, Figure 4) in which the internal electrode and the dielectric layer are alternately disposed to form capacitance (Figure 2, Figure 4), and a margin portion (113, 114 – Figure 2) disposed on each of both side surfaces of the capacitance formation portion in the third direction (‘W’ direction – Figure 1, Figure 2), and an average size of the margin portion in the third direction is 0.25 times or less than a maximum size of the multilayer electronic component in the third direction (¶36, ¶149). In re claim 13, Kim in view of Noda discloses the multilayer electronic component of claim 1, as explained above. Kim does not disclose wherein an area of a region of the third and the fourth surfaces, not covered by the protective portion, is greater than an area of a region of the third and the fourth surfaces, covered by the protective portion. Noda discloses wherein an area of a region of the third and the fourth surfaces (surfaces of 2 facing in the ‘Y’ direction – Figure 1, Figure 2), not covered by the protective portion (16a – Figure 1, Figure 2, Figure 3), is greater than an area of a region of the third and the fourth surfaces, covered by the protective portion (Figure 2, Figure 3) (¶101-103). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the protective portion of Noda to improve the moisture reliability of the electronic component (¶87: Noda). Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Publication 2014/0301013) in view of Noda et al. (US Publication 2017/0076870) and in further view of Hoshino et al. (US Publication 2022/0262570). In re claim 11, Kim in view of Noda discloses the multilayer electronic component of claim 1, as explained above. Kim further discloses wherein the multilayer portion includes a capacitance formation portion (portion of 110 where 121, 122, 112 exist – Figure 2, Figure 4) in which the internal electrode and the dielectric layer are alternately disposed to form capacitance (Figure 2, Figure 4), and a cover portion (C – Figure 2, Figure 3, ¶76) disposed on each of both side surfaces of the capacitance formation portion in the first direction (Figure 2, Figure 3). Kim does not disclose an average size of the cover portion in the first direction is 0.25 times or less than a maximum size of the multilayer electronic component in the first direction. Hoshino discloses an average size of the cover portion (5a, 5b – Figure 2, ¶64) in the first direction is 0.25 times or less than a maximum size of the multilayer electronic component in the first direction (¶64, ¶78). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the cover layer and component dimensions of Hoshino to achieve a device having desired mechanical strength and miniaturization characteristics per user specifications, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (US Publication 2019/0180936) in view of Nishisaka et al. (US Publication 2018/0096791). In re claim 14, Cha discloses a multilayer electronic component comprising: a multilayer portion (110 – Figure 1, ¶26) including: a dielectric layer (112 – Figure 3, ¶37), internal electrodes (121, 122 – Figure 3, ¶26) alternately disposed with the dielectric layer in a first direction (Figure 3), first and second surfaces (5, 6 – Figure 1, ¶27) opposing each other in the first direction (‘T’ direction – Figure 1), third and fourth surfaces (3, 4 – Figure 1, ¶27) opposing each other in a second direction (‘L’ direction – Figure 1) perpendicular to the first direction, and fifth and sixth surfaces (left and right surfaces of 111 – Figure 2, ¶37) opposing each other in a third direction (‘W’ direction – Figure 1) perpendicular to the first and second directions (Figure 1); external electrodes (131, 132 – Figure 1, ¶33) disposed on the multilayer portion (110 – Figure 1), the external electrodes being electrically connected to the internal electrodes (121, 122 – Figure 2, Figure 3); and margin portions (113, 114 – Figure 2, ¶34) disposed on the fifth and sixth surfaces (Figure 2), wherein the average thickness of each of the margin portions is 0.25 times or less than a maximum size of the multilayer electronic component in the third direction (¶36, ¶149). Cha does not disclose a protective portion disposed on the third and the fourth surfaces and external electrodes disposed on the multilayer portion and the protective portion. Nishisaka discloses a protective portion (142a, 142b – Figure 4, ¶44) disposed on the third and the fourth surfaces (15a, 15b – Figure 2, ¶23) and external electrodes (143a, 143b – Figure 2, ¶44) disposed on the multilayer portion (11 – Figure 2, ¶24) and the protective portion (Figure 2). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the protective portion of Nishisaka to prevent the entry of moisture into the electronic component (¶59: Nishisaka). In re claim 15, Cha in view of Nishisaka discloses the multilayer electronic component of claim 14, wherein the margin portions have a composition different from that of the dielectric layer. Cha further discloses the margin portions have a composition different from that of the dielectric layer (¶86). Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (US Publication 2019/0180936) in view of Nishisaka et al. (US Publication 2018/0096791) and in further view of Kim (US Publication 2014/0301013). In re claim 16, Cha in view of Nishisaka discloses the multilayer electronic component of claim 14, as explained above. Cha does not disclose wherein the margin portions comprise a dielectric material with an average grain size smaller than that of the dielectric layer. Kim discloses the margin portions (113, 114 – Figure 2, Figure 3, ¶46) comprise a dielectric material (¶79) with an average grain size smaller than that of the dielectric layer (¶79). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the grain size characteristics of Kim to provide for a component in improved moisture characteristics and reliability. Allowable Subject Matter Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) wherein one end of the internal electrode in the second direction, connected to the third surface or the fourth surface, is referred to as an end portion of the internal electrode, and a region between an uppermost end and a lowermost end of the end portion of the internal electrode in the first direction and a region between both line segments connecting a distal end of the end portion of the internal electrode in the third direction are referred to as an end surface of the internal electrode, the protective portion covers a region of the third surface and the fourth surface, excluding the end surface of the internal electrode. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al. (US Publication 2015/0043125) Figure 5 Park et al. (US Publication 2021/0005382) [¶93] Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ARUN RAMASWAMY/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Mar 13, 2025
Application Filed
Sep 29, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
97%
With Interview (+12.3%)
2y 6m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 818 resolved cases by this examiner. Grant probability derived from career allowance rate.

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