DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
On Page 1, “SUMMSRY” should be replaced with --SUMMARY--.
Appropriate correction is required.
Claim Objections
Claims 1-5 are objected to because of the following informalities:
CLAIM 1:
In line 7, delete “that”.
In line 8, replace “indicates” with --indicating--.
CLAIM 2:
In line 5, delete “that” and replace “indicates” with --indicating--.
CLAIM 3:
In line 6, replace “a” with --the--.
In line 7, replace “a” before “first” with --the--.
In line 8, replace “an” with --the--.
In line 9, delete “that” and replace “occurs” with --occurring--.
CLAIM 4:
In line 3, replace “an” with --the--.
In line 5, delete “that” and replace “is” with --being--.
CLAIM 5:
In line 3, delete “that” and replace “is” with --being--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horiguchi et al (20180115310).
In re Claim 1, Horiguchi teaches a short-circuit protection circuit for a SiC MOS transistor (100, paragraphs 38, and 68-77) comprising: a state detection unit (8) connected (indirectly) to a drain of the SiC MOS transistor and a power supply (not shown), and configured to generate an indication signal for indicating whether a short-circuit occurs in the power supply (paragraphs 59-60); a driving unit (2a, 2b, 2c, and 24), a first input end of the driving unit being connected to a first output end of the state detection unit (where S2 connects with 24), and an output end of the driving unit being connected to a gate of the SiC MOS transistor, to drive the SiC MOS transistor to be turned off in response to the indication signal indicating that a short-circuit occurs in the power supply (paragraphs 80-82); and a power supply voltage conversion unit (3 and 10), a first end of the power supply voltage conversion unit being connected to the state detection unit (where S2 connects with 10), to switch between a first on position for turning on a first power supply (19) and a second on position for turning on a second power supply (20) based on the indication signal (paragraphs 43-45), a second end of the power supply voltage conversion unit (downstream terminal of switch 21) being connected to a power supply end of the driving unit (input of 2a), to provide a first power supply voltage of the first power supply (voltage at 19) or a second power supply voltage of the second power supply to the driving unit, voltage magnitudes of the first power supply voltage and the second power supply voltage being different (paragraph 42), the driving unit being configured to provide a first driving voltage to the SiC MOS transistor in response to receiving the first power supply voltage, the driving unit being configured to provide a second driving voltage to the SiC MOS transistor in response to receiving the second power supply voltage, voltage magnitudes of the first driving voltage and the first power supply voltage being the same, and voltage magnitudes of the second driving voltage and the second power supply voltage being the same (paragraphs 42-45).
In re Claim 2, Horiguchi teaches a control unit (10), an input end of the control unit is connected to a second output end of the state detection unit (where S2 connects with 10), and an output end of the control unit is connected to a second input end of the driving unit (indirectly connected to input of 2b), the control unit is configured to receive the indication signal and generating a turn-on control signal in response to the indication signal indicating that a short-circuit does not occur in the power supply, so that the driving unit drives the SiC MOS transistor to be turned on under control of the turn-on control signal (paragraphs 43, 44, and 80-83).
In re Claim 6, Horiguchi teaches that the source of 100 is connected to a load (implicit) (paragraph 38).
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In re Claim 3, Horiguchi fails to teach that the state detection unit comprises a resistor and a signal generation unit, the resistor is connected between the drain of the SiC MOS transistor and the power supply, a first input end of the signal generation unit is connected to a node between the resistor and the power supply, a second input end of the signal generation unit is connected to a node between the resistor and the drain of the SiC MOS transistor, a first output end of the signal generation unit is connected to the first input end of the driving unit and the first end of the power supply voltage conversion unit, a second output end of the signal generation unit is connected to the input end of the control unit, and the signal generation unit is configured to generate the indication signal in response to a short-circuit occurring in the power supply.
Claims 4 and 5 are dependent on claim 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER JAY CLARK whose telephone number is (571)270-1427. The examiner can normally be reached Monday - Friday, 10:00am - 6:00pm EST.
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/CHRISTOPHER J CLARK/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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