DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 12-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Number 10,452,117 to Becker (“Becker”).
In reference to Claim 1, Becker discloses a processor cluster (See Figures 1 and 3 Numbers 102a, 104a, and 106a-106b), comprising: a plurality of processing circuits (See Figures 1 and 3 Numbers 106a-106b), comprising: at least one first type processing circuit (See Column 9 Lines 28-41); and at least one second type processing circuit (See Column 9 Lines 28-41); and a cluster energy management circuit (See Figures 1 and 3 Number 102a and 104a) configured to: receive first cluster energy credits (See Column 6 Lines 31-43 and Column 7 Lines 24-47 [portion of total budget allocated to cluster]); and generate first processor energy credits for the plurality of processing circuits (See Column 7 Lines 24-49 and Column 8 Lines 4-25), wherein the first processor energy credits generated for each processing circuit of the plurality of processing circuits is based on: a weight corresponding to the processing circuit and applied to the first cluster energy credits (See Column 8 Lines 4-25 [priority allocation]); and a plurality of signals configured to suspend providing the first processor energy credits to a first processing circuit of the plurality of processing circuits (See Column 9 Lines 49-58 [zero energy credits are provided]).
In reference to Claim 2, Becker discloses the limitations as applied to Claim 1 above. Becker further discloses that the cluster energy management circuit is further configured to provide the first processor energy credits to the plurality of processing circuits to control activity in the plurality of processing circuits (See Column 8 Line 61 – Column 9 Line 27).
In reference to Claim 3, Becker discloses the limitations as applied to Claim 1 above. Becker further discloses that the at least one second type processing circuit is configured to provide a different processing function than the at least one first type processing circuit (See Column 9 Lines 28-40).
In reference to Claim 4, Becker discloses the limitations as applied to Claim 1 above. Becker further discloses that the cluster energy management circuit is further configured to receive the weight for each processing circuit of the plurality of processing circuits from a respective programmable storage circuit (See Column 2 Lines 47-55, Column 7 Lines 27-32, and Column 8 Lines 4-25 [a priority allocation scheme must necessarily store the priorities/weights]).
In reference to Claim 5, Becker discloses the limitations as applied to Claim 1 above. Becker further discloses that the at least one second type processing circuit is configured to provide a same processing function as the at least one first type processing circuit (See Column 9 Lines 40-41).
In reference to Claim 6, Becker discloses the limitations as applied to Claim 1 above. Becker further discloses that each processing circuit of the plurality of processing circuits is configured to activate a first signal of the plurality of signals to indicate a request for suspension of the first processor energy credits to the processing circuit (See Column 9 Lines 45-55); and the cluster energy management circuit is further configured to, in response to the first signal from a first processing circuit of the plurality of processing circuits, suspend the first processor energy credits to the first processing circuit (See Column 9 Lines 49-50 and 55-56).
In reference to Claim 7, Becker discloses the limitations as applied to Claim 6 above. Becker further discloses that the cluster energy management circuit is further configured to provide the first processor energy credits having a value of zero to the first processing circuit (See Column 9 Lines 49-50 and 55-56).
In reference to Claim 8, Becker discloses the limitations as applied to Claim 6 above. Becker further discloses that the cluster energy management circuit is further configured to, in response to the first signal from the first processing circuit of the plurality of processing circuits, reallocate the first processor energy credits suspended from the first processing circuit to one or more other processing circuits in the plurality of processing circuits (See Column 9 Lines 42-56 and Column 10 Lines 30-50).
In reference to Claim 9, Becker discloses the limitations as applied to Claim 6 above. Becker further discloses that the cluster energy management circuit is further configured to, in response to the first signal from the first processing circuit of the plurality of processing circuits, reallocate the first processor energy credits suspended from the first processing circuit according to a selected algorithm selected from among a plurality of algorithms (See Column 8 Lines 15-19).
In reference to Claim 12, Becker discloses the limitations as applied to Claim 1 above. Becker further discloses that the cluster energy management circuit is further configured to: in response to the first cluster energy credits exceeding a cluster threshold energy credit, generate the first processor energy credits for each processing circuit of the plurality of processing circuits based on the cluster threshold energy credit (See Column 4 Lines 21-48 and Column 6 Lines 31-43).
In reference to Claim 13, Becker discloses the limitations as applied to Claim 1 above. Becker further discloses that the cluster energy management circuit is further configured to: in response to the first processor energy credits for a first processing circuit of the plurality of processing circuits exceeding a processor threshold energy credit, generate the first processor energy credits for the first processing circuit based on the processor threshold energy credit (See Column 9 Lines 42-56).
In reference to Claim 14, Becker discloses the limitations as applied to Claim 1 above. Becker further discloses that the cluster energy management circuit is further configured to: in response to an override signal, generate the first processor energy credits for each processing circuit of the plurality of processing circuits based on a programmed energy credit (See Column 7 Lines 45-47).
In reference to Claim 15, Becker discloses the limitations as applied to Claim 1 above. Becker further discloses that the weight for a first one of the at least one first type processing circuit and a second one of the at least one first type processing circuit are different (See Column 8 Lines 4-25 [priority allocation requires the use of different priorities])
In reference to Claim 16, Becker discloses the limitations as applied to Claim 1 above. Becker further discloses the processor cluster integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device (See Column 14 Line 1); a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer (See Column 13 Lines 52-55); a portable computer (See Column 13 Lines 62-63); a mobile computing device (See Column 13 Lines 62-63); a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor (See Column 14 Line 2); a computer monitor (See Column 14 Line 2); a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.
Claims 17 and 20 recite limitations which are substantially equivalent to those of Claim 1 and is rejected under similar reasoning. Becker further discloses an integrated circuit (See Column 15 Lines 20-31) and a chip energy management circuit configured to generate the first cluster energy credits (See Column 6 Lines 31-43 and Column 7 Lines 24-47).
Claim 18 recites limitations which are substantially equivalent to those of Claim 2 and is rejected under similar reasoning.
In reference to Claim 19, Becker discloses the limitations as applied to Claim 17 above. Becker further discloses suspending the first processor energy credits to the first processing circuit (See Column 9 Lines 49-50 and 55-56).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication Number 2015/0067356 to Trichy Ravi et al. (“Trichy Ravi”) and US Patent Application Publication Number 2011/0188507 to Watts (“Watts”).
In reference to Claim 1, Trichy Ravi discloses a processor cluster (See Figure 1 Number 180), comprising: a plurality of processing circuits (See Figure 1 Numbers 102, 104, and 186), comprising: at least one first type processing circuit (See Figure 1 Number 182 [CPU]); and at least one second type processing circuit (See Figure 1 Number 186 [GPU] or, alternatively, Number 184 and Paragraph 4 [CPU core having different computational power, runtime environment, or hardware]); and a cluster energy management circuit (See Figure 1 Number 150) configured to: receive first cluster energy credits (See Paragraph 22 [initial power budget allocated to node]); and generate first processor energy credits for the plurality of processing circuits (See Paragraph 22), wherein the first processor energy credits generated for each processing circuit of the plurality of processing circuits is based on: a plurality of signals configured to suspend providing the first processor energy credits to a first processing circuit of the plurality of processing circuits (See Paragraph 22 [signal that a thread on a core has reached a barrier]). However, Trichy Ravi does not explicitly disclose that the first processor energy credits generated for each processing circuit of the plurality of processing circuits is based on a weight corresponding to the processing circuit and applied to the first cluster energy credits. Watts discloses generating credits for resource allocation for consumer circuits based on a weight corresponding to the consumer circuits (See Paragraphs 5, 15, 18, and 26-27).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Trichy Ravi using the credits based on weights of Watts, resulting in the invention of Claim 1, in order to yield the predictable result of providing enhanced fairness and ensuring that greedy power consumers are regulated (See Paragraph 27 of Watts).
In reference to Claim 2, Trichy Ravi and Watts disclose the limitations as applied to Claim 1 above. Trichy Ravi further discloses that the cluster energy management circuit is further configured to provide the first processor energy credits to the plurality of processing circuits to control activity in the plurality of processing circuits (See Paragraphs 22 and 24).
In reference to Claim 3, Trichy Ravi and Watts disclose the limitations as applied to Claim 1 above. Trichy Ravi further discloses that the at least one second type processing circuit is configured to provide a different processing function than the at least one first type processing circuit (See Figure 1 Numbers 182 and 186 and Paragraphs 16 and 32 [CPU vs. GPU]).
In reference to Claim 4, Trichy Ravi and Watts disclose the limitations as applied to Claim 1 above. Watts further discloses that the cluster energy management circuit is further configured to receive the weight for each processing circuit of the plurality of processing circuits from a respective programmable storage circuit (See Paragraphs 18, 76, and 78-79).
In reference to Claim 5, Trichy Ravi and Watts disclose the limitations as applied to Claim 1 above. Trichy Ravi further discloses that the at least one second type processing circuit is configured to provide a same processing function as the at least one first type processing circuit (See Figure 1 Numbers 182 and 184 and Paragraphs 16 and 32 [CPU function]).
In reference to Claim 6, Trichy Ravi and Watts disclose the limitations as applied to Claim 1 above. Trichy Ravi further discloses that each processing circuit of the plurality of processing circuits is configured to activate a first signal of the plurality of signals to indicate a request for suspension of the first processor energy credits to the processing circuit (See Paragraph 22); and the cluster energy management circuit is further configured to, in response to the first signal from a first processing circuit of the plurality of processing circuits, suspend the first processor energy credits to the first processing circuit (See Paragraphs 22-23).
In reference to Claim 7, Trichy Ravi and Watts disclose the limitations as applied to Claim 6 above. Becker further discloses that the cluster energy management circuit is further configured to provide the first processor energy credits having a value of zero to the first processing circuit (See Paragraphs 22-23).
In reference to Claim 8, Trichy Ravi and Watts disclose the limitations as applied to Claim 6 above. Trichy Ravi further discloses that the cluster energy management circuit is further configured to, in response to the first signal from the first processing circuit of the plurality of processing circuits, reallocate the first processor energy credits suspended from the first processing circuit to one or more other processing circuits in the plurality of processing circuits (See Paragraph 22).
In reference to Claim 9, Trichy Ravi and Watts disclose the limitations as applied to Claim 6 above. Trichy Ravi further discloses that the cluster energy management circuit is further configured to, in response to the first signal from the first processing circuit of the plurality of processing circuits, reallocate the first processor energy credits suspended from the first processing circuit according to a selected algorithm selected from among a plurality of algorithms (See Paragraph 22 [redistribute to some active processors vs. redistribute to all active processors]).
In reference to Claim 14, Trichy Ravi and Watts disclose the limitations as applied to Claim 1 above. Trichy Ravi further discloses that the cluster energy management circuit is further configured to: in response to an override signal, generate the first processor energy credits for each processing circuit of the plurality of processing circuits based on a programmed energy credit (See Paragraph 22 [user defined power budget]).
In reference to Claim 15, Trichy Ravi and Watts disclose the limitations as applied to Claim 1 above. Watts further discloses that the weight for a first one of the at least one first type processing circuit and a second one of the at least one first type processing circuit are different (See Paragraphs 5, 15 18, and 26-27)
In reference to Claim 16, Trichy Ravi and Watts disclose the limitations as applied to Claim 1 above. Trichy Ravi further discloses the processor cluster integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device (See Paragraph 3); a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer (See Paragraphs 2 and 30); a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.
Claims 17 and 20 recite limitations which are substantially equivalent to those of Claim 1 and is rejected under similar reasoning. Trichy Ravi further discloses an integrated circuit (See Paragraphs 31-32) and a chip energy management circuit configured to generate the first cluster energy credits (See Figure 1 Number 130 and Paragraph 22).
Claim 18 recites limitations which are substantially equivalent to those of Claim 2 and is rejected under similar reasoning.
In reference to Claim 19, Trichy Ravi and Watts disclose the limitations as applied to Claim 17 above. Trichy Ravi further discloses suspending the first processor energy credits to the first processing circuit (See Paragraphs 22-23).
Allowable Subject Matter
Claim(s) 10-11 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The claims are allowable because the prior art fails to disclose, either alone or in combination, all of the claim limitations in the combinations as claimed. The most relevant prior art references are Trichy Ravi and Watts as applied to Claim 1 above. However, Trichy Ravi and Watts do not explicitly disclose that the cluster energy management circuit is farther configured to: in a first period: receive the first cluster energy credits comprising a first integer number of energy credits and a first fractional number of an energy credit; and generate the first processor energy credits of the plurality of processing circuits based on the first integer number of energy credits; and in a second period following the first period: receive second cluster energy credits comprising a second integer number of energy credits and a second fractional number of an energy credit; and generate adjusted second cluster energy credits based on a sum of the first fractional number of an energy credit and the second cluster energy credits, as in Claim 10. Trichy Ravi and Watts further do not explicitly disclose that the cluster energy management circuit is further configured to: in a first period: generate the first processor energy credits for a first processing circuit of the plurality of processing circuits comprising a third integer number of energy credits and a third fractional number of an energy credit; store the third fractional number of an energy credit; and provide the third integer number of energy credits to the first processing circuit; Andin a second period following the first period: increase the first processor energy credits generated for the first processing circuit by the third fractional number of an energy credit to generate a fourth integer number of energy credits and a fourth fractional number of an energy credit; store the fourth fractional number of an energy credit; and provide the fourth integer number of energy credits to the first processing circuit, as in Claim 11. Furthermore, although the use of fractional energy credits is generally known in the art, as disclosed by US Patent Application Publication Number 2015/0089254 to Burns et al. (See Paragraphs 28-30), such usage simply allows the use of different “speed bins” which allow the processors to operate at different speeds instead of simply being set to the maximum power. Such fractional energy credits usage of Burns does not make obvious the aforementioned specific usage of the fractional energy credits as claimed. Furthermore, such claimed features would not have been obvious to one of ordinary skill in the art at the time the invention was filed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 25 August 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Conclusion
The art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J CLEARY whose telephone number is (571)272-3624. The examiner can normally be reached Monday-Friday 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS J. CLEARY/ Primary Examiner, Art Unit 2175
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