DETAILED ACTION
This is in response to the application filed on March 13, 2025 in which claims 1 – 20 are presented for examination.
Status of Claims
Claims 1 – 20 are pending, of which claims 1 and 13 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 3/13/2025 and 8/11/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 – 4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the high priority degree master signal" in lines 2 and 4 of the claim. There is insufficient antecedent basis for these limitation in the claims because claim 1 refers to “at least one of high priority degree master signals.” Since claim 1 refers to at least one of these signals, there is no antecedent basis for referring later to “the” signal. The examiner recommends amending claim 2 to state:
2. The auxiliary bus master circuit according to claim 1, further comprising a logic circuit that latches a high priority degree master signal acquired from the high priority degree master circuit,
wherein the control circuit controls a timing for latching the high priority degree master signal and a timing for outputting, to the bus, the acquired high priority degree master signal as the access request signal.
Claims 3 – 4 inherit this rejection based on their dependencies.
Claim Objections
Claim 4 is objected to because of the following informalities: claim 4 details outputting a certain signal to a certain bus. The claim then ends with the phrase “among the buses,” which appears redundant and unnecessary.
The examiner recommends amending claim 4 to state:
4. The auxiliary bus master circuit according to claim 3, wherein the control circuit performs control in such a way as to output the access request signal to at least one of a bus in which the high priority degree master address bus signal is exchanged and a bus in which the high priority degree master writing data bus signal is exchanged
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 12, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Clark, U.S. Patent Application 2006/0288143 (hereinafter referred to as Clark) (from Applicant’s IDS) in view of Kojina, U.S. Patent Application 2012/0246510 (hereinafter referred to as Kojina).
Referring to claim 1, Clark discloses a “circuit that is connected or connectable to a bus in a system in which a high priority degree master circuit having a bus access right having a high degree of priority and a low priority degree master circuit having a bus access right having a lower degree of priority than the high priority degree master circuit are connected to one bus” (Figs. 1 and 4 along with [0026] a plurality of masters 12 connected to an AHB bus 19. [0028] “the arbiter may employ a highest priority first arbitration algorithm. For this scheme, the masters may be assigned priority rankings and the requests of the masters may be arbitrated based on their relative priorities”), “the” “circuit comprising a control circuit that outputs an access request signal for requesting an access right from the bus, based on a timing for outputting at least one of high priority degree master signals being signals exchanged by the high priority degree master circuit through the bus” (Fig. 4 and [0032] arbiter outputs signal 22 to grant bus ownership to a master. [0028] arbiter uses master priority to arbitrate master requests, highest priority first. [0029] master sends request HBUSREQ1, arbiter grants access to the bus via HGRANT1. Fig. 5 shows the timing of receiving bus requests (HBUSREQ) and HTRANS from masters and the HGRANT signal from the arbiter. [0037] When submitting the request, master 312 will be ready to receive activation 432' of a bus grant from arbiter 380 by the next bus cycle 414).
Clark does not appear to explicitly disclose “An auxiliary bus master circuit” the “control circuit that outputs an access request signal.”
However, Kojina discloses another multiple-master connection system wherein “An auxiliary bus master circuit” is connected to a bus in a system of multiple masters, the auxiliary bus master circuit comprising a control circuit that outputs an access request signal” (Fig. 1 masters include a control unit 30 with an access request unit 31b, MUX 20 selects which master connects to the bus. Fig. 7-8 masters including operating master and standby master, the standby master includes a sequence control unit connecting 32B to a MUX 20B. Fig. 12 shows the masters both trying to connect to a same slave. Fig. 14 details the MUX connecting the master to a slave, the MUX within the master).
Clark and Kojina are analogous art because they are from the same field of endeavor, which is multiple masters connecting to a same bus.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Clark and Kojina before him or her, to modify the teachings of Clark to include the teachings of Kojina so that an auxiliary bus master circuit is connected to a bus in a system of multiple masters, the auxiliary bus master circuit comprising a control circuit that outputs an access request signal.
The motivation for doing so would have been to provide a means for adding redundancy to the bus system of Clark, as well as utilizing the processing power of a standby master. This leads to better performance with less idle time of standby processors.
Therefore, it would have been obvious to combine Kojina with Clark to obtain the invention as specified in the instant claim.
As per claim 6, Clark discloses “a transfer mode signal indicating a single transfer mode is output as an output of a signal of a transfer mode indicating whether a transfer mode is a single transfer mode or a burst transfer mode, regardless of a transfer mode of the high priority degree master circuit” (Figs. 5 and 6 HBURST includes ‘SINGLE’ signals along with [0039] arbiter receives burst type control signal and determines a number of single bus cycles).
As per claim 12, the rejection of claim 1 applies to claim 12 as well since claim 12 references the auxiliary bus master circuit according to claim 1.
Further, Clark/Kojina discloses “An electronic device comprising: the auxiliary bus master circuit according to claim 1; and the high priority degree master circuit” (Kojina Fig. 1 shows a device 9 including multiple master devices, Kojina Fig. 3 shows one of the masters being a standby master 2B. Clark teaches the circuit connected to “the high priority degree master circuit” at Figs. 1 and 4 along with [0026] a plurality of masters 12 connected to an AHB bus 19. [0028] “the arbiter may employ a highest priority first arbitration algorithm. For this scheme, the masters may be assigned priority rankings and the requests of the masters may be arbitrated based on their relative priorities”).
Referring to claim 13, claim 1 recites the corresponding limitations as that of claim 13. Therefore, the rejection of claim 1 applies to claim 13.
Note, claim 15 recites the corresponding limitations of claim 6. Therefore, the rejection of claim 6 applies to claim 15.
Claims 2 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over Clark in view of Kojina, as applied to claims above, further in view of Worrell et al., U.S. Patent Application 2007/0136503 (hereinafter referred to as Worrell).
As per claim 2, neither Clark nor Kojina appears to explicitly disclose “a logic circuit that latches the high priority degree master signal acquired from the high priority degree master circuit, wherein the control circuit controls a timing for latching the high priority degree master signal and a timing for outputting, to the bus, the acquired high priority degree master signal as the access request signal.”
However, Worrell discloses another multi-master AHB system including “a logic circuit that latches the high priority degree master signal acquired from the high priority degree master circuit, wherein the control circuit controls a timing for latching the high priority degree master signal and a timing for outputting, to the bus, the acquired high priority degree master signal as the access request signal” (Fig. 3 master ports connecting to priority encoder 204. Fig. 12 and [0141] receiving write data H_WDATA and latching the signal at register 272. [0141] “The register 272 may present a signal (e.g., WDR) containing the latched write data at the end of each transfer” and utilizing clock cycles for timing).
Clark, Kojina, and Worrell are analogous art because they are from the same field of endeavor, which is multiple masters connecting to a same bus.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Clark, Kojina, and Worrell before him or her, to modify the teachings of Clark and Kojina to include the teachings of Worrell so that a logic circuit that latches the high priority degree master signal and controls a timing for outputting the acquired signal.
The motivation for doing so would have been to provide a means for taking into account any chip to chip clock skew (as stated by Worrell at [0141]).
Therefore, it would have been obvious to combine Worrell with Clark and Kojina to obtain the invention as specified in the instant claim.
As per claim 3, neither Clark nor Kojina appears to explicitly disclose “the high priority degree master signal latched in the logic circuit is at least one of a high priority degree master address bus signal and a high priority degree writing data bus signal.”
However, Worrell discloses “the high priority degree master signal latched in the logic circuit is at least one of a high priority degree master address bus signal and a high priority degree writing data bus signal” (Fig. 3 master ports connecting to priority encoder 204. Fig. 12 and [0141] receiving write data H_WDATA and latching the signal at register 272. [0141] “The register 272 may present a signal (e.g., WDR) containing the latched write data at the end of each transfer” and utilizing clock cycles for timing).
Clark, Kojina, and Worrell are analogous art because they are from the same field of endeavor, which is multiple masters connecting to a same bus.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Clark, Kojina, and Worrell before him or her, to modify the teachings of Clark and Kojina to include the teachings of Worrell so that a logic circuit that latches the high priority degree master signal and controls a timing for outputting the acquired signal.
The motivation for doing so would have been to provide a means for taking into account any chip to chip clock skew (as stated by Worrell at [0141]).
Therefore, it would have been obvious to combine Worrell with Clark and Kojina to obtain the invention as specified in the instant claim.
As per claim 4, neither Clark nor Kojina appears to explicitly disclose “the control circuit performs control in such a way as to output the access request signal to at least one of a bus in which the high priority degree master address bus signal is exchanged and a bus in which the high priority degree master writing data bus signal is exchanged among the buses.”
However, Worrell discloses “the control circuit performs control in such a way as to output the access request signal to at least one of a bus in which the high priority degree master address bus signal is exchanged and a bus in which the high priority degree master writing data bus signal is exchanged among the buses” (Fig. 3 master ports connecting to priority encoder 204. Fig. 12 and [0141] receiving write data H_WDATA and latching the signal at register 272. [0141] “The register 272 may present a signal (e.g., WDR) containing the latched write data at the end of each transfer” and utilizing clock cycles for timing).
Clark, Kojina, and Worrell are analogous art because they are from the same field of endeavor, which is multiple masters connecting to a same bus.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Clark, Kojina, and Worrell before him or her, to modify the teachings of Clark and Kojina to include the teachings of Worrell so that a logic circuit that latches the high priority degree master signal and controls a timing for outputting the acquired signal.
The motivation for doing so would have been to provide a means for taking into account any chip to chip clock skew (as stated by Worrell at [0141]).
Therefore, it would have been obvious to combine Worrell with Clark and Kojina to obtain the invention as specified in the instant claim.
Claims 9 – 10 and 18 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Clark in view of Kojina, as applied to claims above, further in view of Walmsley, U.S. Patent Application 2006/0294312 (hereinafter referred to as Walmsley).
As per claim 9, neither Clark nor Kojina appears to explicitly disclose “an operation mode signal is acquired, and whether to output the access request signal is switched based on the acquired operation mode signal.”
However, Walmsley discloses another arbitration method of multiple masters ([0736]) including “an operation mode signal is acquired, and whether to output the access request signal is switched based on the acquired operation mode signal” (Table 9 on page 23 MMU limits access to certain memory address areas in CPU user mode. [1139] signals indicate address space being accessed, determine if mode allows the access to be granted).
Clark, Kojina, and Walmsley are analogous art because they are from the same field of endeavor, which is multiple masters connecting to a same bus.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Clark, Kojina, and Walmsley before him or her, to modify the teachings of Clark and Kojina to include the teachings of Walmsley so that an operation mode signal is used to determine whether to output the access request signal.
The motivation for doing so would have been to provide a level of security, not allowing access to certain memory locations (as described by Walmsley at the Background section and [0509], [1139]).
Therefore, it would have been obvious to combine Walmsley with Clark and Kojina to obtain the invention as specified in the instant claim.
As per claim 10, neither Clark nor Kojina appears to explicitly disclose “the operation mode signal includes information about a threshold value address and information about a threshold value condition, and whether to output the access request signal is switched according to whether an address value indicated by a high priority degree master address signal being a signal of an address bus among the high priority degree master signals satisfies the threshold value address and the threshold value address condition.”
However, Walmsley discloses another arbitration method of multiple masters ([0736]) including “the operation mode signal includes information about a threshold value address and information about a threshold value condition, and whether to output the access request signal is switched according to whether an address value indicated by a high priority degree master address signal being a signal of an address bus among the high priority degree master signals satisfies the threshold value address and the threshold value address condition” (Table 9 on page 23 MMU limits access to certain memory address areas in CPU user mode. [1139] signals indicate address space being accessed, determine if mode allows the access to be granted).
Clark, Kojina, and Walmsley are analogous art because they are from the same field of endeavor, which is multiple masters connecting to a same bus.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Clark, Kojina, and Walmsley before him or her, to modify the teachings of Clark and Kojina to include the teachings of Walmsley so that an operation mode signal is used to determine whether to output the access request signal.
The motivation for doing so would have been to provide a level of security, not allowing access to certain memory locations (as described by Walmsley at the Background section and [0509], [1139]).
Therefore, it would have been obvious to combine Walmsley with Clark and Kojina to obtain the invention as specified in the instant claim.
Note, claim 18 recites the corresponding limitations of claim 9. Therefore, the rejection of claim 9 applies to claim 18.
Note, claim 19 recites the corresponding limitations of claim 10. Therefore, the rejection of claim 10 applies to claim 19.
Allowable Subject Matter
Claims 5, 7, 8, 11, 14, 16, 17, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Applications 20050204084, 20090144480 and Patent 7412550 teach an AMBA multi-master system with arbiter.
U.S. Patent Applications 20050066097 and 20080195782 teach multi-master systems with bus controllers.
U.S. Patent 8799708 is the granted patent to Kojina.
U.S. Patent Applications 20100325319, 20100321972 and Patents 7797467, 7966431, 8046505 are also to Worrell, with similar teachings.
U.S. Patent Application 20040205267 and Patent 6981088 teach an AMBA multi-master system with arbiter.
Machine Translation of Japanese Patent Application JP 2007219968 A teaches an AMBA multi-master system with arbiter.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
Prosecution Insights