Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Basto(US 2010/0271084) and Koob(US 2013/0039133).
Regarding claim 1, Basto discloses a source synchronous interface circuit, comprising: a first circuit, located on a master voltage domain side(Figure 5, circuit 510 is in master voltage domain) and configured to: obtain, in response to a transmission request, valid data, and convert a source clock signal into a source synchronous clock signal corresponding to the valid data(Paragraph 38, one transaction transferring 4 elements of n bits from source block 510 to destination block 520. In device 500, source block 510 includes a source-synchronous clock generator 512 to provide a source clock to source-synchronous clock line 557, and destination block 520 includes buffer 522 for storing data received via source-synchronous data link 555. With the source-synchronous data link 555, only one data element crosses the clock/power domains at a time, together with source clock via source-synchronous clock line 557. Source clock of clock domain A is sent via source-synchronous clock line 557 to destination block 520 in clock domain B and it is used to write the data elements into storage buffer 522); a level conversion circuit, configured to: perform level conversion on the valid data and the source synchronous clock signal outputted by the first circuit to a slave voltage domain range of a second circuit(Paragraph 47, Each source-synchronous data link 755/765 includes a total of n+1 lines, where n is the number of bits (e.g., 8) for each data element. Also, each source-synchronous data link 755/765 includes a level shifter for each of the n+1 lines), and output the valid data and the source synchronous clock signal after level conversion to the second circuit(Paragraph 43, first bus adaptor component 630a provides a source clock (e.g., the core clock 615) to source-synchronous clock line 657, and the destination end includes a buffer for storing data received via source-synchronous data link 655 and clocked in via the source clock on source-synchronous clock line 657 ); and the second circuit, located on a slave voltage domain side and configured to: receive the valid data and the source synchronous clock signal after level conversion, and store the valid data into an data storage queue based on the source synchronous clock signal(Paragraph 43, first bus adaptor component 630a provides a source clock (e.g., the core clock 615) to source-synchronous clock line 657, and the destination end includes a buffer for storing data received via source-synchronous data link 655 and clocked in via the source clock on source-synchronous clock line 657).
Basto does not specifically disclose the data storage queue is asynchronous. However, Koob teaches an asynchronous data storage queue(Paragraph 4, A data storage device, such as an asynchronous first-in first-out (FIFO) buffer, that accepts input data at a data input from a first voltage domain and outputs data at a second domain uses a level shifter at the data input) and those of skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, processor-executable instructions, or combinations of both(Paragraph 52). It would have been obvious to one of ordinary skill in the art and before the effective filing date to combine the teachings of Basto and Koob to use an asynchronous data storage queue. The motivation to do so would be that asynchronous data storage queue, are well known and routinely used in the art so that data can be read/stored using different clocks.
Regarding claim 2, Basto and Koob disclose the source synchronous interface circuit according to claim 1, wherein the first circuit comprises: a counter, configured to record a number of idle positions in the asynchronous data storage queue of the second circuit and output a count value; and a first source synchronous interface unit, configured to: determine whether the count value meets a condition; and convert, when determining that the count value meets the condition, the source clock signal into the source synchronous clock signal corresponding to the valid data, and output the source synchronous clock signal to the level conversion circuit(Koob: Paragraph 37, A FIFO depth signal 227 may be generated based on the write counter value and the read counter value. The FIFO depth signal 227 may indicate a "depth" (e.g., available storage) of the data storage device 128. To generate the FIFO depth signal 227, the write counter value may be converted from a Gray code representation to a binary representation by the first GTB circuit 229. Similarly, the read counter value may be converted from a Gray code representation to a binary representation by the second GTB circuit 233. The outputs from the first GTB circuit 229 and from the second GTB circuit 233 are input to an arithmetic logic unit 230 that generates the FIFO depth signal 227).
Regarding claim 3, Basto and Koob disclose the source synchronous interface circuit according to claim 2, wherein the counter is configured to decrease the count value when the first source synchronous interface unit outputs the source synchronous clock signal(Koob: Paragraph 29, a write counter value stored at the write counter 203 may be incremented. For example, the write counter value may be incremented from "000" to "001" to indicate that data has been written to the data storage device 128 and is available to be read from the data storage device 128).
Regarding claim 4, Basto and Koob disclose the source synchronous interface circuit according to claim 1, wherein the first circuit converts the source clock signal into the source synchronous clock signal corresponding to the valid data by: determining a timing corresponding to the valid data and a timing difference that meets a condition between the valid data and the source synchronous clock signal, and determining the source synchronous clock signal corresponding to the valid data based on the timing corresponding to the valid data and the timing difference that meets the condition(Basto: Paragraph 39, Another important difference between asynchronous data link 255 and source-synchronous data link 555 is the timing closure constraints. For the asynchronous link 255, data crossing domains should be treated as multiple cycle paths with respect to destination-end clock "B" 215. For the source-synchronous link, only the relative skew between the data on source-synchronous data link 555 and the source clock on source-synchronous clock line 557 crossing domains needs to be constrained).
Regarding claim 5, Basto and Koob disclose the source synchronous interface circuit according to claim 2, wherein the second circuit comprises: a second asynchronous interface unit, comprising the asynchronous data storage queue, wherein the second asynchronous interface unit is capable of storing the valid data into the asynchronous data storage queue based on the source synchronous clock signal and outputting data from the asynchronous data storage queue to a bus on the slave voltage domain side; and a second source synchronous interface unit, configured to receive a ready clock signal outputted by the bus on the slave voltage domain side and convert the ready clock signal into a source synchronous handshake signal for transmission to the level conversion circuit, wherein the source synchronous handshake signal is configured to indicate that the asynchronous data storage queue has data output, so that the counter in the first circuit increases the count value based on the source synchronous handshake signal(Koob: Paragraph 37, A FIFO depth signal 227 may be generated based on the write counter value and the read counter value. The FIFO depth signal 227 may indicate a "depth" (e.g., available storage) of the data storage device 128. To generate the FIFO depth signal 227, the write counter value may be converted from a Gray code representation to a binary representation by the first GTB circuit 229. Similarly, the read counter value may be converted from a Gray code representation to a binary representation by the second GTB circuit 233. The outputs from the first GTB circuit 229 and from the second GTB circuit 233 are input to an arithmetic logic unit 230 that generates the FIFO depth signal 227).
Regarding claim 6, Basto and Koob disclose the source synchronous interface circuit according to claim 5, wherein the first circuit further comprises: a first asynchronous interface unit, configured to: obtain the source synchronous handshake signal outputted by the second source synchronous interface unit via the level conversion circuit; generate a bus synchronous handshake signal of the first circuit based on the source synchronous handshake signal; and output the bus synchronous handshake signal to a bus on the master voltage domain side, so that the bus on the master voltage domain side is able to transmit data to the slave voltage domain side based on the bus synchronous handshake signal, wherein the counter is capable of updating the count value based on the bus synchronous handshake signal(Koob: Paragraph 37, A FIFO depth signal 227 may be generated based on the write counter value and the read counter value. The FIFO depth signal 227 may indicate a "depth" (e.g., available storage) of the data storage device 128. To generate the FIFO depth signal 227, the write counter value may be converted from a Gray code representation to a binary representation by the first GTB circuit 229. Similarly, the read counter value may be converted from a Gray code representation to a binary representation by the second GTB circuit 233. The outputs from the first GTB circuit 229 and from the second GTB circuit 233 are input to an arithmetic logic unit 230 that generates the FIFO depth signal 227).
Regarding claim 7, Basto and Koob disclose the source synchronous interface circuit according to claim 5, wherein the level conversion circuit at least comprises: a first level conversion unit, configured to perform level conversion on the valid data and the source synchronous clock signal outputted by the first circuit to the slave voltage domain range of the second circuit and output the valid data and the source synchronous clock signal after level conversion to the second circuit; and a second level conversion unit, configured to perform level conversion on the source synchronous handshake signal to a master voltage domain range of the first circuit and output the source synchronous handshake signal after level conversion to the first circuit(Koob: Paragraph 21, A second level shifter 164 may be coupled to receive the clock input 154, a third level shifter 168 may be coupled to receive the write enable input 158, and a fourth level shifter 170 may be coupled to receive the write address signal 160. The second level shifter 164 may be configured to level shift the clock signal 152 from a voltage level associated with the first voltage domain 108 to a voltage level associated with the second voltage domain 112. Similarly, the third level shifter 168 may be configured to level shift the write enable signal 156 from a voltage level associated with the first voltage domain 108 to a voltage level associated with the second voltage domain 112. The fourth level shifter 170 may be configured to level shift the write address signal 160 from a voltage level associated with the first voltage domain 108 to a voltage level associated with the second voltage domain 112).
Regarding claim 8, Basto and Koob disclose the source synchronous interface circuit according to claim 7, wherein the first level conversion unit comprises: a first level conversion sub-unit, configured to perform level conversion on the valid data outputted by the first circuit to the slave voltage domain range of the second circuit and output the valid data after level conversion to the second circuit; and a second level conversion sub-unit, configured to perform level conversion on the source synchronous clock signal outputted by the first circuit to the slave voltage domain range of the second circuit and output the source synchronous clock signal after level conversion to the second circuit(Koob: Paragraph 21, A second level shifter 164 may be coupled to receive the clock input 154, a third level shifter 168 may be coupled to receive the write enable input 158, and a fourth level shifter 170 may be coupled to receive the write address signal 160. The second level shifter 164 may be configured to level shift the clock signal 152 from a voltage level associated with the first voltage domain 108 to a voltage level associated with the second voltage domain 112. Similarly, the third level shifter 168 may be configured to level shift the write enable signal 156 from a voltage level associated with the first voltage domain 108 to a voltage level associated with the second voltage domain 112. The fourth level shifter 170 may be configured to level shift the write address signal 160 from a voltage level associated with the first voltage domain 108 to a voltage level associated with the second voltage domain 112).
Regarding claim 9, Basto and Koob disclose the source synchronous interface circuit according to claim 1, wherein a timing path in the first circuit converges within a master voltage domain range, and a timing path in the second circuit converges within the slave voltage domain range(Koob: Paragraph 4, A data storage device, such as an asynchronous first-in first-out (FIFO) buffer, that accepts input data at a data input from a first voltage domain and outputs data at a second domain uses a level shifter at the data input).
Claims 10-20 recite substantially similar limitations as claims 1-9 and thus taught by Basto and Koob, as explained above.
Conclusion
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/NIMESH G PATEL/ Primary Examiner, Art Unit 2185
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