Prosecution Insights
Last updated: April 19, 2026
Application No. 19/079,028

3D DATA IMAGING USING DRIVE SENSE CIRCUITS

Non-Final OA §DP
Filed
Mar 13, 2025
Examiner
ARONOVICH, OLGA
Art Unit
2629
Tech Center
2600 — Communications
Assignee
Sigmasense LLC
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
89%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
568 granted / 750 resolved
+13.7% vs TC avg
Moderate +14% lift
Without
With
+13.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
20 currently pending
Career history
770
Total Applications
across all art units

Statute-Specific Performance

§101
3.0%
-37.0% vs TC avg
§103
55.8%
+15.8% vs TC avg
§102
13.0%
-27.0% vs TC avg
§112
17.1%
-22.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 750 resolved cases

Office Action

§DP
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Current Status of Claims This action is a response to communication of March 13, 2025. Claims 1 to 7 are currently active in the application. Information Disclosure Statement The information disclosure statement (IDS) submitted on September 11, 2025 was filed before the mailing date of the first action on merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-7 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,254,154. Although the claims at issue are not identical, they are not patentably distinct from each other because both invention are related to computing device comprising an image sensing grid producing driving signal to the image when generate a capacitive image of the image sensing grid based on the received self-capacitances and the received mutual capacitances to generate a frame of image data regarding the item based on the capacitive image and a data reduction method. Instant application 19/079,028 Conflicting Patent 12,254,154 1. A computing device comprises: an image sensing grid operable to sense an item, wherein the image sensing grid includes a plurality of electrodes; a plurality of drive sense circuits, wherein: a first drive sense circuit of the plurality of drive sense circuits provides a first signal to a first electrode of the plurality of electrodes; a second drive sense circuit of the plurality of drive sense circuits provides the first signal and a second signal to a second electrode of the plurality of electrodes; the first drive sense circuit senses a self-capacitance of the first electrode and a mutual capacitance of the first and second electrodes; and the second drive sense circuit senses a self-capacitance of the second electrode; a processing module operably coupled to: receive the self-capacitance of at least some of the plurality of electrodes from at least some of the plurality of drive senses circuits to produced received self-capacitances; receive the mutual capacitance of at least some pairs of electrodes of the plurality of electrodes from a set of drive sense circuits of the plurality of drive sense circuit to produce receive mutual capacitances; generate a capacitive image of the image sensing grid based on the received self-capacitances and the received mutual capacitances; generate a frame of image data regarding the item based on the capacitive image and a data reduction method. 2. The computing device of claim 1 further comprises: the plurality of electrodes includes a first set of electrodes and a second set of electrodes, wherein the first set of electrodes is on a first layer of a substrate and the second set of electrodes is on a second layer of the substrate. 3. The computing device of claim 1 further comprises: a video graphics processing module operably coupled to convert the frame of image data into a frame of video graphics data. 4. The computing device of claim 1, wherein the processing module is further operable to generate the frame of image data regarding the item based on the capacitive image and a data reduction method by: determining whether a full grid of the self-capacitance and the mutual capacitance for the image sensing grid is to be processed; when the full grid is to be processed, determining whether data reduction can be lossy; when the data reduction can be lossy, selecting a lossy data reduction process to generate a data reduced frame of image data; determining whether the data reduced frame of image data is at a desired data rate; and when the data reduced frame of image data is at the desired data rate, outputting the data reduced frame of image data as the frame of image data. 5. The computing device of claim 4, wherein the processing module is further operable to generate the frame of image data regarding the item based on the capacitive image and a data reduction method by: when whether the data reduced frame of image data is not at the desired data rate, selecting a second lossy data reduction process to generate a second data reduced frame of image data; determining whether the second data reduced frame of image data is at a desired data rate; and when the second data reduced frame of image data is at the desired data rate, outputting the second data reduced frame of image data as the frame of image data. 6. The computing device of claim 4, wherein the processing module is further operable to generate the frame of image data regarding the item based on the capacitive image and a data reduction method by: when the data reduction cannot be lossy, selecting a lossless data reduction process to generate the data reduced frame of image data; and when the data reduced frame of image data is not at the desired data rate, selecting a second lossless data reduction process to generate a second data reduced frame of image data. 7. The computing device of claim 4, wherein the processing module is further operable to generate the frame of image data regarding the item based on the capacitive image and a data reduction method by: when less than the full grid is to be processed, determining one or more sections of the full grid to be processed. 1. A computing device comprises: an image sensing grid operable to sense an item; a plurality of drive sense circuits operable to: provide drive signals to the image sensing grid; detect an effect on one or more drive signals caused by the item being proximal to the image sensing grid; and generate drive sense data based on the detected effect of the one or more drive signals; and a processing module operable to: generate a frame of image data regarding the item based on the drive sense data in accordance with a data reduction method, wherein the frame of image data corresponds to a plurality of measures of effect the item had on at least some of the drive signals provided to the image sensing grid during a frame interval; and provide reduced three-dimensional image data to a data circuit, wherein the reduced three-dimensional image data corresponds to changes in the frame of image data from frame to frame, and wherein the data circuit produces processed image data. 2. The computing device of claim 1, wherein the image sensing grid comprises: a plurality of sensors arranged in a grid. 3. The computing device of claim 1, wherein the processing module is further operable to generate the frame of image data by: determining whether to reduce data size for the frame of image data; when the processing module determines to reduce the data size: selecting the data reduction method; and processing the drive sense data in accordance with the selected data reduction method to produce the frame of image data. 4. The computing device of claim 3, wherein the processing module is further operable to determine whether to reduce the data size by: determining that an output rate of the processing module and/or an output rate of the data circuit cannot support unreduced data requirements of the image sensing grid, wherein a data requirement of the image sensing grid includes one of: data resolution per frame, bits per frame, frame rate, or a desired use of image data. 5. The computing device of claim 3, wherein the processing module is further operable to select the data reduction method by: determining whether the data reduction scheme can be lossy based on the use; when the data reduction scheme can be lossy, selecting a lossy data reduction process from a plurality of data compression options; and when the data reduction scheme cannot be lossy, selecting a lossless data reduction process from the plurality of data compression options. 6. The computing device of claim 1 further comprises: the effect on a drive signal of the one or more drive signals is caused by an electrical characteristic of a sensor of the image sensing grid; the drive sense data for the drive signal includes a measure of the effect on the electrical characteristics of the sensor; and the image data corresponding to the sensor includes a measure of the electrical characteristics of the sensor. 7. The computing device of claim 1 further comprises: the data circuit is operably coupled to the processing module and is a component of the computing device. 8. The computing device of claim 7, wherein the data circuit is further operable to generate the frame of visual image data by: generating a heat map based on the frame of image data. 9. The computing device of claim 7, wherein the data circuit is further operable to: generate a plurality of frames of visual image data based on a plurality of frames of image data, wherein the plurality of frames of visual image data correspond to movement of the item on the image sensing grid. 10. The computing device of claim 7, wherein the data circuit is further operable to: generate a plurality of frames of visual image data based on a plurality of frames of image data, wherein the plurality of frames of visual image data correspond to topology of the item with respect to a surface of the image sensing grid. 11. A computer readable memory device comprises: a first memory section that stores operational instructions that, when executed by a processing module of a computing device, causes the processing module to: enable a plurality of drive sense circuits to provide drive signals to an image sensing grid; and receive drive sense data from the plurality of drive sense circuits, wherein the drive sense data includes an effect on a drive signal provided by a drive sense circuit of the plurality of drive sense circuits signals, wherein the effect is caused by an item being proximal to the image sensing grid; and a second memory section that stores operational instructions that, when executed by the processing module, causes the processing module to: generate a frame of image data regarding the item based on the drive sense data in accordance with a data reduction method, wherein the frame of image data corresponds to a plurality of measures of effect the item had on at least some of the drive signals provided to the image sensing grid during a frame interval; and provide reduced three-dimensional image data to a data circuit, wherein the reduced three-dimensional image data corresponds to changes in the frame of image data from frame to frame, and wherein the data circuit produces processed image data. 12. The computer readable memory device of claim 11, wherein the second memory section further stores operational instructions that, when executed by the processing module, causes the processing module to generate the frame of image data by: determining whether to reduce data size for the frame of image data; when the processing module determines to reduce the data size: selecting the data reduction method; and processing the drive sense data in accordance with the selected data reduction method to produce the frame of image data. 13. The computer readable memory device of claim 12, wherein the second memory section further stores operational instructions that, when executed by the processing module, causes the processing module to determine whether to reduce the data size by: determining that an output rate of the processing module and/or an output rate of the data circuit cannot support unreduced data requirements of the image sensing grid, wherein a data requirement of the image sensing grid includes one of: data resolution per frame, bits per frame, frame rate, or a desired use of image data. 14. The computer readable memory device of claim 12, wherein the second memory section further stores operational instructions that, when executed by the processing module, causes the processing module to select the data reduction method by: determining whether the data reduction scheme can be lossy based on the use; when the data reduction scheme can be lossy, selecting a lossy data reduction process from a plurality of data compression options; and when the data reduction scheme cannot be lossy, selecting a lossless data reduction process from the plurality of data compression options. 15. The computer readable memory device of claim 11 further comprises: the effect on a drive signal of the one or more drive signals is caused by an electrical characteristic of a sensor of the image sensing grid; the drive sense data for the drive signal includes a measure of the effect on the electrical characteristics of the sensor; and the image data corresponding to the sensor includes a measure of the electrical characteristics of the sensor. 16. The computer readable memory device of claim 11 further comprises: a third memory section that stores operational instructions that, when executed by the data circuit, causes the data circuit to: generate, as the frame of visual image data, a heat map based on the frame of image data. 17. The computer readable memory device of claim 16, wherein the third memory section further stores operational instructions that, when executed by the data circuit, causes the data circuit to: generate a plurality of frames of visual image data based on a plurality of frames of image data, wherein the plurality of frames of visual image data correspond to movement of the item on the image sensing grid. 18. The computer readable memory device of claim 16, wherein the third memory section further stores operational instructions that, when executed by the data circuit, causes the data circuit to: generate a plurality of frames of visual image data based on a plurality of frames of image data, wherein the plurality of frames of visual image data correspond to topology of the item with respect to a surface of the image sensing grid. Conclusion The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. US Patent 8,380,995 to Paul US Patent Publication Application 2012/0174213 to Geiger et al. US Patent Publication Application 2012/0110662 to Brosnan US Patent Publication Application 2011/0115604 to Sobel et al. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Olga V. Merkoulova whose telephone number is ((571)270-7796. The examiner can normally be reached on Mon-Fri. from 7:30-5:00. If attempts to reach the examiner by telephone are unsuccessful, the examiner's Supervisor, LunYi Lao can be reached on (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197/ (Tall-free). /OLGA V MERKOULOVA/Primary Examiner, Art Unit 2621
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Prosecution Timeline

Mar 13, 2025
Application Filed
Jan 09, 2026
Non-Final Rejection — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
89%
With Interview (+13.7%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 750 resolved cases by this examiner. Grant probability derived from career allow rate.

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