DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continuity
Examiner notes this application is a continuation of 17820986.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/13/2025, 5/22/2025 and 3/20/2026 have been considered by the examiner.
Claim Rejections - 35 USC § 112
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 10 recites an output voltage at the power input terminal, but the output voltage is from the power output terminal, not the power input terminal. The claim is indefinite when interpreted in light of the specification because, as Figure 1 and the specification make clear, the output voltage is from the power output terminal, not the power input terminal, making the claim unclear when interpreted in light of the specification as to which was intended. For the purpose of examination, the claim shall be interpreted as ‘wherein an output voltage at the power output terminal’.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 and 9-10 are rejected under 35 U.S.C. 102a2 as being anticipated by Jong (US 2022/0231601).
With respect to claim 1, Jong discloses a circuit comprising: a first high-side switch (Fig. 13 Q1) coupled to a first low-side switch (Fig. 13 Q2) at a first switch node (Fig. 13 node Q1-Q2); a second high-side switch (Fig. 13 Q5) coupled to a second low-side switch (Fig. 13 Q6) at a second switch node (Fig. 13 node Q5-Q6), the first switch node coupled (Fig. 13 coupled to VOUT) to the second switch node; a power input terminal (Fig. 13 terminal VIN) coupled to the first and second high-side switches; a third high-side switch (Fig. 13 Q11) coupled to a third low-side switch (Fig. 13 Q12) at a third switch node (Fig. 13 node Q11-Q12), the third low-side switch coupled to a ground (Fig. 13 ground symbol), wherein the third high-side switch is coupled (Fig. 13 mid) to the first low-side switch and to the second low-side switch; and a power output terminal (Fig. 13 terminal VOUT) coupled (Fig. 13 coupled through Cflyn and Ln) to the first switch node and to the third switch node.
With respect to claim 2, Jong discloses the circuit of claim 1, further comprising a controller (Fig. 13 702) arranged to generate signals (Fig. 13 SW1,AM; paragraph 96) to control conductivity states of the first high-side switch, the second high-side switch, and the third high-side switch, and the first low-side switch, the second low-side switch, and the third low-side switch.
With respect to claim 3, Jong discloses the circuit of claim 1, further comprising a first capacitor (Fig. 13 Cfly1) coupled to the first switch node.
With respect to claim 4, Jong discloses the circuit of claim 3, further comprising a first inductor (Fig. 13 L1) coupled between the first capacitor and the power output terminal.
With respect to claim 5, Jong discloses the circuit of claim 4, wherein the further comprising a second capacitor (Fig. 13 Cfly2) coupled to the second switch node.
With respect to claim 9, Jong discloses the circuit of claim 1, wherein the third switch node is coupled to the power output terminal through a second inductor (Fig. 13 L3).
With respect to claim 10, Jong discloses the circuit of claim 9, wherein an output voltage (Fig. 13 VOUT) at the power output terminal has a value that is lower (paragraph 112) than an input voltage (Fig. 13 Vin) at the power input terminal.
Allowable Subject Matter
Claims 11-20 are allowed, while Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 6, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the second capacitor is coupled to the power output terminal through the first inductor.
With respect to claim 7, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the first capacitor is coupled to the first inductor through a first switch.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 11, Jong discloses a method of operating a circuit, the method comprising: providing a first top buck converter circuit (Fig. 13 Q1,Q1) coupled to an input terminal (Fig. 13 terminal Vin); providing a second top buck converter circuit (Fig. 13 Q5,Q6) coupled to the input terminal (Fig. 13 terminal VIN), the first top buck converter circuit coupled to the second top buck converter circuit at a second (Fig. 13 mid) connection node; providing a bottom buck converter circuit (Fig. 13 Q11,Q12) coupled to the first top buck converter circuit and to the second top buck converter circuit at the second connection node (Fig. 13 mid); and providing an output terminal (Fig. 13 node VOUT) coupled (Fig. 13 coupled through L3) to the bottom buck converter circuit and to the first connection node (Fig. 13 coupled through Cfly1 and L1), but the prior art does not disclose, primarily, wherein the input terminal is not directly connected to the first connection node, and wherein the output terminal is coupled to the first connection node through only a first inductor.
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
