DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8, 13, and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dalla Longa et al. (USP 11,245,410).
Regarding claim 1, Dalla Longa et al. discloses an architecture in figure 1A that teaches: operating a digital-to-analog converter (101), DAC (106)), with a clock signal (110), the clock signal (110) having noise comprising jitter to be detected; feeding an output of the DAC to an input of a CT integrator (102); quantizing (104) a signal generated from the output of the CT integrator (Vintg); filtering (112), by a low pass filter (col.3 lines59-60), the quantized signal (Qout) such that the filtered output signal is directly proportional to the jitter in the clock signal; and detecting jitter based on the filtered output signal (see fig. 1A and descriptions).
Regarding claim 2, Dalla Longa also teaches operating DAC using an output of an analog to digital converter, ADC (see figures 1A and 2A) (output of ADC input to operating DAC).
Regarding claim 8, Dalla Longa also teach removing quantization noise by decimation filter (see figures 1A and 2A and descriptions).
Regarding claim 13, claim 13 is similar to claim 1 in system format. Therefore, claim 13 is rejected as well as rejected in claim 1, such as: Dalla Longa et al. discloses an architecture in figure 1A that teaches: operating a digital-to-analog converter (101), DAC (106)), with a clock signal (110), the clock signal (110) having noise comprising jitter to be detected; feeding an output of the DAC to an input of a CT integrator (102); quantizing (104) a signal generated from the output of the CT integrator (Vintg); filtering (112), by a low pass filter (col.3 lines59-60), the quantized signal (Qout) such that the filtered output signal is directly proportional to the jitter in the clock signal; and detecting jitter based on the filtered output signal (see fig. 1A and descriptions).
Regarding claim 16, Dalla Longa et al, teaches a system (which can be considered as an electronic component) supply clock signal (clk_in) to operation first DAC (106) (see figure 1A and 2A).
Regarding claim 17, Dalla Longa et al. teaches a system which can be an electronic component and which an electronic component is a digital to analog converter, DAC (see abstract and title).
Regarding claim 18, Dalla Longa et al teaches in figure 1A a continuous time delta sigma, CTSD, modulator including DAC, ADC and integrator (col. 3., line 42-67 and col. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Dalla Longa et al. as applied to claim 1 above, and further in view of Shu et al. (USP 11,265,010).
Regarding claim 7, Dalla Longa et al. fails to teach or suggest filtering comprising digital filter.
While, Shu et al. discloses in figure 1A a sigma delta architecture that teaches a digital filter (104) for filtering output of the quantizer.
Therefore, it would be obvious to an ordinary skill in the art at the time of effective filing of the invention to replace decimation filter with a digital filter to meet the design needs.
Claim 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dalla Longa et al. as applied to claim 1 above, and further in view of Ouzounov (USP 11,506,770) and Glunmac et al. (USP 10,743,812).
Regarding claim 19, Dalla Longa et al. fails to teach or suggest an architecture of figure 1A, 2A (Dalla Longa et al. discloses an architecture in figure 1A that teaches: operating a digital-to-analog converter (101), DAC (106)), with a clock signal (110), the clock signal (110) having noise comprising jitter to be detected; feeding an output of the DAC to an input of a CT integrator (102); quantizing (104) a signal generated from the output of the CT integrator (Vintg); filtering (112), by a low pass filter (col.3 lines59-60), the quantized signal (Qout) such that the filtered output signal is directly proportional to the jitter in the clock signal; and detecting jitter based on the filtered output signal (see fig. 1A and descriptions)) be used in transducer environment.
While, Ouzounov. discloses a technique using sigma delta architecture (similar to figures. 1A an/or 2A) in the transducer environment (see claims 2 and 3 and col. 2 and 3).
Therefore, it would be obvious to an ordinary skill in the art at the time of effective filing of the invention to implement architecture of figures 1A and/or 2A in transducer environment to meet the design needs.
Regarding claim 20, Dalla Longa and Ouzounov. et al. fail to teach or suggest input parameter to the transducer comprising one or more of crosstalk, power supply noise, electromagnetic interference, EMI, vibration, shock, change in termination.
While, Glunmac et al. teaches a vibration as an input for transducer (see col. 7, lines 21-36).
Therefore, it would be obvious to an ordinary skill in the art at the time of effective filing of the invention to implement vibration input for transducer teach by Glunmac et al to meet the design needs.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest object features, which is: wherein an average of the DAC output is zero at the input of the CT integrator when clock signal comprises no jitter or wherein an average of the DAC output deviated from zero by a known offset at the input of the CT integrator.
Claim 4 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest object features, which is: processing the filtered output signal to determine a presence of jitter and/or a quantity of jitter in the clock signal.
Claim 5 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest object features, which is: verifying that the clock signal comprises a predetermined level of jitter based on measuring an amplitude of the filtered output signal.
Claim 6 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest object features, which is: generating a confidence coefficient using the filtered output signal indicative of a level of jitter present in the clock signal.
Claim 9 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest object features, which is: one or more of: processing the filtered output signal to find a root mean square, RMS, value; averaging the filtered output signal using integration.
Claim 10 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest object features, which is: applying a scale factor to express the filtered output signal as a clock jitter level in time, frequency or phase units.
Claim 11 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest object features, which is: wherein the method comprises implementing a CT sigma delta modulator and shorting an input pin of the CT sigma delta modulator such that the input to the CT sigma delta modulator is zero.
Claim 12 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest object features, which is: wherein the method comprises feeding a square wave input signal to an input pin of the CT integrator, and optionally, wherein the method comprises modulating the square wave input using the CT integrator.
Claim 14 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest object features, which is: a second DAC coupled to an input of the CT integrator, wherein the second DAC is a continuous time DAC.
Claim 15 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest object features, which is: an analog-to-digital converter, ADC, wherein the ADC is coupled between the CT integrator and the first DAC and an output of the ADC is fed back to an input of the first DAC, and optionally, wherein an input pin of the CT integrator is configured to be shorted such that the input pin of the CT integrator is zero.
Cited References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845
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