DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
In paragraph 43, line 1, “310” should be -310a-.
Appropriate correction is required.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “211b” has been used to designate both the second UFP and a bridge controller.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 221b, 311a, 310.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 6, 10-12, and 14 are objected to because of the following informalities:
In claim 6, line 2, “circuit, the” should be -circuit, and the-.
In claim 10, line 3, “specification,” should be -specification, and-.
In claim 14, line 2, “circuit, the” should be -circuit, and the-.
Appropriate correction is required.
Referring to independent claim 1, Malladi’951 teaches a first interface circuit, comprising a first upstream facing port and a plurality of first downstream facing ports (binding of host upstream ports to device downstream ports, paragraph 51, lines 22-23) wherein the first upstream facing port is configured to couple to a host integrated circuit in a host (host upstream ports, paragraph 51, line 22); and a plurality of first artificial intelligence (AI) computing modules (ASIC circuits, FPGA units, and/or the like, implement an AI-based technique (e.g., a machine learning based methodology) to route the workloads, paragraph 51, lines 8-11), configured to couple to the first downstream facing ports to form an AI accelerator cluster (binding of host upstream ports to device downstream ports, paragraph 51, lines 22-23; cluster-level performance-based control and management capability whereby workloads can be routed automatically, paragraph 51, lines 2-4).
Malladi’951 does not appear to explicitly teach a docking station, adapted to be coupled to a host.
However, Regupathy’777 teaches a docking station (USB4 hub 104 can be (or can include) a docking station, see figure 1 and paragraph 28, lines 9-10), adapted to be coupled to a host (USB4 host 102 connected to a USB4 hub 104, see figure 1 and paragraph 28, lines 1-2).
Malladi’951 and Regupathy’777 are analogous because they are both drawn to the same inventive field of resource allocation.
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Malladi’951 and Regupathy’777 before them, to modify the interface circuit of Malladi’951 to include the docking station of Regupathy’777 by incorporating a USB hub configured to connect to a host.
The motivation for doing so would have been to combine multiple protocols onto a single physical interface so that the total speed and performance of the USB fabric can be dynamically shared not just between USB devices, but also PCIe or DP endpoints (paragraph 3, lines 3-9).
Therefore, it would have been obvious to combine Malladi’951 and Regupathy’777 to bring about the invention as claimed.
As to claim 2, Malladi’951 does not appear to explicitly teach the docking station according to claim 1, wherein the first interface circuit is configured to couple to the host integrated circuit through the first upstream facing port and a platform interface hub in the host based on a universal serial bus (USB) specification.
Regupathy’777 teaches the docking station according to claim 1, wherein the first interface circuit is configured to couple to the host integrated circuit through the first upstream facing port and a platform interface hub in the host based on a universal serial bus (USB) specification (USB4 host 102 connected to a USB4 hub 104, see figure 1 and paragraph 28, lines 1-2).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Malladi’951 and Regupathy’777 before them, to modify the interface circuit of Malladi’951 to include the docking station of Regupathy’777 by incorporating a USB hub configured to connect to a host.
The motivation for doing so would have been to combine multiple protocols onto a single physical interface so that the total speed and performance of the USB fabric can be dynamically shared not just between USB devices, but also PCIe or DP endpoints (paragraph 3, lines 3-9).
As to claim 3, Malladi’951 does not appear to explicitly teach the docking station according to claim 2, wherein the first AI computing modules are configured to couple to the first downstream facing ports based on the USB specification.
Regupathy’777 teaches the docking station according to claim 2, wherein the first AI computing modules are configured to couple to the first downstream facing ports based on the USB specification (USB4 hub 104 can be connected to a USB4 device 106 by a USB link, see figure 1 and paragraph 28, lines 2-3).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Malladi’951 and Regupathy’777 before them, to modify the interface circuit of Malladi’951 to include the docking station of Regupathy’777 by incorporating a USB hub configured to connect to a device.
The motivation for doing so would have been to combine multiple protocols onto a single physical interface so that the total speed and performance of the USB fabric can be dynamically shared not just between USB devices, but also PCIe or DP endpoints (paragraph 3, lines 3-9).
As to claim 4, Malladi’951 teaches the docking station according to claim 3, wherein each of the first Al computing modules comprises: an AI controller (management computing entity 202 that can be configured to operate in connection with multiple clusters, see figure 2 and paragraph 105, lines 7-9), coupled to a bridge controller (management computing entity 102 (to be described below in detail) can be configured to include a processing element (e.g., a processor, FPGA, ASIC, controller, etc.) that can monitor one or more parameters associated with ToR Ethernet switch 110, see figure 1A and paragraph 59, lines 1-7).
Malladi’951 does not appear to explicitly teach the bridge controller coupled to a corresponding one of the first downstream facing ports based on the USB specification.
However, Regupathy’777 teaches the bridge controller coupled to a corresponding one of the first downstream facing ports based on the USB specification (USB4 host 102 connected to a USB4 hub 104, see figure 1 and paragraph 28, lines 1-2; USB4 hub 104 can be connected to a USB4 device 106 by a USB link, see figure 1 and paragraph 28, lines 2-3).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Malladi’951 and Regupathy’777 before them, to modify the interface circuit of Malladi’951 to include the bridge controller connection of Regupathy’777 by incorporating a USB hub configured to connect to a device.
The motivation for doing so would have been to combine multiple protocols onto a single physical interface so that the total speed and performance of the USB fabric can be dynamically shared not just between USB devices, but also PCIe or DP endpoints (paragraph 3, lines 3-9).
Allowable Subject Matter
Claims 5-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 5, the prior art of record does not appear to anticipate, explicitly teach, or fairly suggest a plurality of second Al computing modules, configured to couple to the second downstream facing ports, so that the first Al computing modules and the second Al computing modules form the Al accelerator cluster.
Cao et al. (CN-115687229-A) discloses dividing the partial data set of the AI model distributed by the server into multiple data subsets of the same size, with each data subset distributed to an AI training board card. However, this does not appear to explicitly teach the subject matter determined to be allowable.
Zhao et al. (CN-110708185-A) discloses each artificial intelligence processor connected with the downstream port of a PCIe Switch in the PCIe interconnection topology tree. However, this does not appear to explicitly teach the subject matter determined to be allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cao et al. (CN-115687229-A) discloses dividing the partial data set of the AI model distributed by the server into multiple data subsets of the same size, with each data subset distributed to an AI training board card.
Zhao et al. (CN-110708185-A) discloses each artificial intelligence processor connected with the downstream port of a PCIe Switch in the PCIe interconnection topology tree.
However, this does not appear to explicitly teach the subject matter determined to be allowable.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN B ROCHE whose telephone number is (571)270-1721. The examiner can normally be reached Monday-Friday, 10:30 - 7.
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/J.B.R/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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