DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 17-20 are rejected under 35 U.S.C. 101 because the claims are directed to a “computer readable storage media”.
The term "computer readable storage media" has not been further defined in the specification, and as such the specification does not limit the claims to only encompassing statutory subject matter. The United States Patent and Trademark Office (USPTO) is obliged to give claims their broadest reasonable interpretation consistent with the specification during proceedings before the USPTO. See In re Zletz, 893 F.2d 319 (Fed. Cir. 1989) (during patent examination the pending claims must be interpreted as broadly as their terms reasonably allow). The broadest reasonable interpretation of a claim drawn to a computer readable medium (also called machine readable medium and other such variations) typically covers forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer readable media, particularly when the specification is silent. See MPEP 2111.01. When the broadest reasonable interpretation of a claim covers a signal per se, the claim must be rejected under 35 U.S.C. § 101 as covering non-statutory subject matter. See In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007) (transitory embodiments are not directed to statutory subject matter) and Interim Examination Instructions for Evaluating Subject Matter Eligibility Under 35 U.S.C. § 101, Aug. 24, 2009; p. 2.
The USPTO recognizes that applicants may have claims directed to computer readable media that cover signals per se, which the USPTO must reject under 35 U.S.C. § 101 as covering both non-statutory subject matter and statutory subject matter. In an effort to assist the patent community in overcoming a rejection or potential rejection under 35 U.S.C. § 101 in this situation, the USPTO suggests the following approach. A claim drawn to such a computer readable medium that covers both transitory and non-transitory embodiments may be amended to narrow the claim to cover only statutory embodiments to avoid a rejection under 35 U.S.C. § 101 by adding the limitation "non-transitory" to the claim. Cf. Animals- Patentability, 1077 Off. Gaz. Pat. Office 24 (April 21, 1987) (suggesting that applicants add the limitation "non-human" to a claim covering a multi-cellular organism to avoid a rejection under 35 U.S.C. § 101). Such an amendment would typically not raise the issue of new matter, even when the specification is silent because the broadest reasonable interpretation relies on the ordinary and customary meaning that includes signals per se. The limited situations in which such an amendment could raise issues of new matter occur, for example, when the specification does not support a non-transitory embodiment because a signal per se is the only viable embodiment such that the amended claim is impermissibly broadened beyond the supporting disclosure. See, e.g., Gentry Gallery, Inc. v. Berkline Corp., 134 F.3d 1473 (Fed. Cir. 1998).
Therefore, applicant is advised to clarify the claimed definition of the term "computer readable storage media".
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lercari et al. (US Patent 11,586,385).
With regard to Claim 1, Lercari teaches a method comprising:
mapping different ranges of logical block addresses, of a flash translation layer of a storage device, to different segments (Col. 17 ll. 13-17: “The memory controller for a given storage drive can optionally apply address translation (e.g., a flash translation layer or FTL) across an entire drive or on a basis restricted to a given logical or physical structure.” Col. 36 ll. 12-18: “the user/designer to specify, for each block device to be allocated, whether the LBA range of the block device is to be uniformly sequenced among the hierarchical structures of the flash storage region to be allocated (e.g., channels, dies, erase units, pages) thus establishing a uniform address space layout (ASL) for the block device...” Col. 38 ll. 13-18: “The configuration storage (Zn/BD Config) includes a lookup table (LUT) that is indexed by an identifier (Id which may be, for example, a namespace or other handle or identifier) and holds, for example and without limitation, a specification of the one or more channels spanned by the block device.” Col. 38 ll. 21-22: “For instance, a first block device (BD0) is seen as spanning channels 0 and 1,” wherein the “block devices” are the “segments”. Col. 38 ll. 55-61: “Continuing with FIG. 4B, each entry within the lookup table LUT additionally includes an index to a respective set of one or more entries within an ASL lookup table (ASL LUT), with each ASL lookup table entry including ASL (address space layout) parameterizations and feature control settings for the complete or partial LBA range of the corresponding block device or zone.”);
mapping the different segments to different channels of the storage device (Fig. 4B: LUT showing the block devices, i.e. segments, having IDs 0-4 being mapped to Channels 0-1, 2-3, 0, 1 and 0-15 respectively.);
receiving a command to perform a write operation on the storage device, wherein the command identifies a range of logical block addresses (Col. 11 ll. 50-57: “The storage drive and/or its memory controller includes logic that maintains and updates this metadata in the course of performing various memory operations, including read and/or write operations. For example, LBA usage information can be kept and automatically updated by the storage drive as it receives and executes a new write request relating to an LBA.”);
identifying one or more segments, of the different segments, mapped to the range of logical block addresses; and performing the write operation using one or more channels, of the different channels, mapped to the identified one or more segments (Col. 25 ll. 19-20: “The memory controller also has logic 317 that performs various functions.” Col. 25 ll. 37-43: “the logic 317 can also perform functions such as address translation (e.g., at any one or more structural tiers within the memory) and write and read (i.e., data access) control and/or address assignment and various maintenance operations, and it can send associated commands to memory dies via a second interface 319 in order to accomplish these various functions.” Col. 38 ll. 46-48: “the channel and die identifiers recorded within the lookup table LUT correspond one-for-one with underlying physical channels and dies within the storage drive.” Col. 28 ll. 34-40: “To perform input/output (IO) operations, controller firmware interacts with the depicted flash memory interface 364 to translate various host system-issued requests into flash memory operation commands, with these commands being transmitted by the memory controller via one or more channels to one or more memory dies on each channel.”).
With regard to Claim 2, Lercari teaches the method of claim 1, wherein mapping the different segments to the different channels comprises:
mapping a first segment of the different segments to a first channel and a second channel of the different channels (Fig. 4B: LUT showing the block device with ID 0 being mapped to Channels 0-1.); and
mapping a second segment of the different segments to a third channel and a fourth channel of the different channels (Fig. 4B: LUT showing the block device with ID 1 being mapped to Channels 2-3.).
With regard to Claim 3, Lercari teaches the method of claim 2, wherein the first channel and the second channel are not sequential channels, and wherein the third channel and the fourth channel are not sequential channels (Fig. 4B: LUT showing that the assignment of channels may be in any configuration, i.e. including non-consecutive channels, as shown by the block device with ID 4 being mapped to Channels 0-15, which includes non-consecutive channels such as Channel 0 and 2. Further, Col. 65 ll. 17-24: “In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, device geometries and numbers of hierarchical structural elements (e.g., channels, dies, planes, erase units, pages, etc.), component circuits or devices and the like may be different from those described above.”).
With regard to Claim 4, Lercari teaches the method of claim 1, wherein mapping the different ranges of logical block addresses to the different segments comprises:
mapping a first range of logical block addresses to a first segment of the different segments; and mapping a second range of logical block addresses to a second segment of the different segments (Col. 38 ll. 55-61: “Continuing with FIG. 4B, each entry within the lookup table LUT additionally includes an index to a respective set of one or more entries within an ASL lookup table (ASL LUT), with each ASL lookup table entry including ASL (address space layout) parameterizations and feature control settings for the complete or partial LBA range of the corresponding block device or zone.”).
With regard to Claim 5, Lercari teaches the method of claim 1, wherein performing the write operation comprises:
performing the write operation on a first lower page of a first storage medium using a first channel of the one or more channels of a first segment of the one or more segments; and performing the write operation on a first lower page of a second storage medium using a first channel of the one or more channels of a second segment of one or more segments (Col. 11 ll. 50-57: “The storage drive and/or its memory controller includes logic that maintains and updates this metadata in the course of performing various memory operations, including read and/or write operations. For example, LBA usage information can be kept and automatically updated by the storage drive as it receives and executes a new write request relating to an LBA.” Col. 43 ll. 26-32: “As before, for example, BD0 and BD1 are seen to be identical in capacity, but to respectively present eight page and single page write frontiers (e.g., as introduced above, BD0 and BD1 can be configured to have four dies with zone 0 having double page striping across all dies), and with BD1 being written one page at a time.” Col. 43 ll. 40-46: “Because LBAs are written in this assumed implementation as a function of dedicated requests, because data is written into an erase unit of flash memory one page at a time, and because writes might arrive out of order, buffering capability is structured in this embodiment so as to accumulate at least double the write frontier for each of these block devices/zones,” wherein Fig. 4B, as discussed above, discloses further details regarding the particular channels and storage die, i.e. “storage medium,” used with each of the block devices, i.e. “segments”.).
With regard to Claim 6, Lercari teaches the method of claim 5, wherein performing the write operation within the first segment comprises:
performing the write operation on a first lower page of a third storage medium using a second channel of the first segment after performing the write operation on the first lower page of the first storage medium; and performing the write operation on a first middle page of the first storage medium using the first channel after performing the write operation on the first lower page of the third storage medium (Col. 11 ll. 50-57: “The storage drive and/or its memory controller includes logic that maintains and updates this metadata in the course of performing various memory operations, including read and/or write operations. For example, LBA usage information can be kept and automatically updated by the storage drive as it receives and executes a new write request relating to an LBA.” Col. 43 ll. 26-32: “As before, for example, BD0 and BD1 are seen to be identical in capacity, but to respectively present eight page and single page write frontiers (e.g., as introduced above, BD0 and BD1 can be configured to have four dies with zone 0 having double page striping across all dies), and with BD1 being written one page at a time.” Col. 43 ll. 40-46: “Because LBAs are written in this assumed implementation as a function of dedicated requests, because data is written into an erase unit of flash memory one page at a time, and because writes might arrive out of order, buffering capability is structured in this embodiment so as to accumulate at least double the write frontier for each of these block devices/zones,” wherein Fig. 4B, as discussed above, discloses further details regarding the particular channels and storage die, i.e. “storage medium,” used with each of the block devices, i.e. “segments”.).
With regard to Claim 7, Lercari teaches the method of claim 1, comprising:
mapping the different ranges of logical block addresses to the different segments and mapping the different segments to the different channels to maintain a size of entries, of a logical to physical table, independently of a size of the storage device, wherein the entries are associated with the logical block addresses (See the LUT disclosed in Fig. 4B as discussed above. Further, Col. 51 ll. 16-19: “For embodiments which support address space layout (ASL) configuration, note that a hardware-based address translation circuit such as depicted in FIG. 9C can be used to automatically map LAs to PA” and Col. 51 ll. 39-47: “As illustrated in FIG. 9C by numeral 961, where translation is performed by the storage drive, hardware (or instructional) logic can obtain ASL parameters 963 and a LBA value 965, and combine both of these values in circuit 967 to obtain a physical address (see e.g., the ASL LUT parameters of FIG. 4B...); the result of this calculation is a flash address tuple 969 identifying a physical address in flash,” wherein the size of the “entries, of a logical to physical table” in Lercari is not indicated as being dependent on the “size of the storage device”.).
With regard to Claim 8, Lercari teaches the method of claim 1, comprising:
mapping the different ranges of logical block addresses to the different segments and mapping the different segments to the different channels to maintain a size of a logical to physical table independently of a size of the storage device, wherein the logical to physical table is associated with the logical block addresses (See the LUT disclosed in Fig. 4B as discussed above. Further, Col. 51 ll. 16-19: “For embodiments which support address space layout (ASL) configuration, note that a hardware-based address translation circuit such as depicted in FIG. 9C can be used to automatically map LAs to PA” and Col. 51 ll. 39-47: “As illustrated in FIG. 9C by numeral 961, where translation is performed by the storage drive, hardware (or instructional) logic can obtain ASL parameters 963 and a LBA value 965, and combine both of these values in circuit 967 to obtain a physical address (see e.g., the ASL LUT parameters of FIG. 4B...); the result of this calculation is a flash address tuple 969 identifying a physical address in flash,” wherein the size of the “size of a logical to physical table” in Lercari is not indicated as being dependent on the “size of the storage device”.).
With regard to Claims 9-16, these claims are equivalent in scope to Claims 1, 8, 7, 5, 6, 2, 3 and 4 as respectively rejected above, merely having a different independent claim type, and as such Claims 9-16 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 1, 8, 7, 5, 6, 2, 3 and 4 respectively.
With further regard to Claim 9, the claim recites additional elements not specifically addressed in the rejection of Claim 1. The Lercari reference also anticipates these additional elements of Claim 9, for example, wherein the system comprises:
a controller, of a storage device (Fig. 2A: Controller 245. Col. 28 ll. 59-63: “FIG. 3F shows a block diagram of a flash memory controller 372, for example, used as controller 245 from FIG. 2A; more particularly, FIG. 3F is used to show how logic functions can be implemented using hardware and firmware logic 369.”).
With regard to Claims 17-19, these claims are equivalent in scope to Claims 1-2 and 5 rejected above, merely having a different independent claim type, and as such Claims 17-19 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 1-2 and 5.
With further regard to Claim 17, the claim recites additional elements not specifically addressed in the rejection of Claim 1. The Lercari reference also anticipates these additional elements of Claim 17, for example, wherein Lercari teaches:
A computer program product comprising: one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media (Col. 4 ln. 67 - Col. 5 ln. 10: “The description set forth below exemplifies techniques that can be practiced... in another embodiment as techniques implemented in logic (e.g., in instructional logic such as software stored on non-transitory media), and in yet another embodiment by a combination of one or more of these things, perhaps cooperating with one or more other devices or circuits”).
With regard to Claim 20, Lercari teaches the computer program product of claim 17, wherein the program instructions comprise:
program instructions to alternate between segments based on a range of logical block addresses of the write command (Col. 28 Ll. 46-58: “Each die can have one or more planes 370, each with independent control and data registers 371, so that each die is capable of performing multiple IO commands simultaneously. Note that LBAs and even zones can be striped across multiple planes (or dies) if desired for the particular implementation. For example, using the techniques of this disclosure, it is possible to write a set of LBAs across planes by ensuring physical addressing of pages written to respective planes in a manner consistent with device multi-plane addressing limitations; such a scheme, if used, permits reading of related data at the same time, for example, by simultaneously reading all planes associated with a given set of memory cells.”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Chang et al. (US PGPUB 2012/0079170) discloses a method for performing block management, including obtaining at least one portion of a plurality of address-to-channel mapping relationships, for use of writing/programming operations; and according to at least one address-to-channel mapping relationship of the plurality of address-to-channel mapping relationships, programming at least one page of data into the Flash memory through at least one channel in a page mode.
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/NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 June 27, 2026
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